From: Caisking <Casiking@zhihuishixun.com>
Date: Thu, 24 Jul 2025 02:24:58 +0000 (+0800)
Subject: 增加gui的psram与线程数
X-Git-Url: http://git.snicker.com.cn/css/static/gitweb.css?a=commitdiff_plain;h=0d7bdfd8c3a200d1e6751f4ef4563e1c25436f64;p=mirrors%2FFD230.git

增加gui的psram与线程数
---

diff --git a/code/sdk/drivers/boards/brandy_evb/memory_config/include/psram_32.h b/code/sdk/drivers/boards/brandy_evb/memory_config/include/psram_32.h
index 4989f88a0..87b9845e5 100755
--- a/code/sdk/drivers/boards/brandy_evb/memory_config/include/psram_32.h
+++ b/code/sdk/drivers/boards/brandy_evb/memory_config/include/psram_32.h
@@ -45,10 +45,10 @@
 
 /* VAU Linked List Address NON Cache */
 #define PSRAM_DISP_VAU_NODE_ADDR            (PSRAM_GUI_MEM_POOL_ADDR + PSRAM_GUI_MEM_POOL_SIZE)
-#define PSRAM_DISP_VAU_NODE_LENGTH          psram_align_size(0x80000, POOL_ADDR_ALIGNSIZE)
+#define PSRAM_DISP_VAU_NODE_LENGTH          psram_align_size(0x80000+0x380000, POOL_ADDR_ALIGNSIZE)
 
 /* reserve */
 #define PSRAM_RESERVE_ADDR                  (PSRAM_DISP_VAU_NODE_ADDR + PSRAM_DISP_VAU_NODE_LENGTH)
-#define PSRAM_RESERVE_ADDR_LENGTH           psram_align_size(0x380000, POOL_ADDR_ALIGNSIZE)
+#define PSRAM_RESERVE_ADDR_LENGTH           psram_align_size(0x0, POOL_ADDR_ALIGNSIZE)
 
 #endif // PSRAM_H
diff --git a/code/sdk/kernel/liteos/liteos_v207.1.0/Huawei_LiteOS/tools/build/config/brandy.config b/code/sdk/kernel/liteos/liteos_v207.1.0/Huawei_LiteOS/tools/build/config/brandy.config
index 8945b187a..09764717b 100755
--- a/code/sdk/kernel/liteos/liteos_v207.1.0/Huawei_LiteOS/tools/build/config/brandy.config
+++ b/code/sdk/kernel/liteos/liteos_v207.1.0/Huawei_LiteOS/tools/build/config/brandy.config
@@ -76,7 +76,7 @@ LOSCFG_TASK_JOINABLE=y
 LOSCFG_BASE_CORE_TSK_MONITOR=y
 LOSCFG_TASK_STACK_STATIC_ALLOCATION=y
 LOSCFG_TASK_STACK_DYNAMIC_ALLOCATION=y
-LOSCFG_BASE_CORE_TSK_LIMIT=72
+LOSCFG_BASE_CORE_TSK_LIMIT=100
 LOSCFG_BASE_CORE_TSK_MIN_STACK_SIZE=1024
 LOSCFG_BASE_CORE_TSK_DEFAULT_STACK_SIZE=2048
 LOSCFG_BASE_CORE_TSK_SWTMR_STACK_SIZE=3072