From 56b1839b6f7dba556552324c7c68b1166202fbfc Mon Sep 17 00:00:00 2001 From: SnickerSun Date: Thu, 30 May 2024 09:52:26 +0800 Subject: [PATCH] =?utf8?q?=E4=BF=AE=E5=A4=8DPSRAM=20=E8=AE=BE=E7=BD=AE?= =?utf8?q?=E6=88=9016MB=20=E6=97=B6=20=E4=B8=8D=E7=94=9F=E6=95=88=E7=9A=84?= =?utf8?q?=E9=97=AE=E9=A2=98=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit --- .../brandy_evb/memory_config/include/psram.h | 35 +- .../drivers/chips/brandy/config/pmp_config.c | 302 +++++++++--------- .../common/include/graphic_hardware_config.h | 1 + 3 files changed, 170 insertions(+), 168 deletions(-) diff --git a/code/sdk/drivers/boards/brandy_evb/memory_config/include/psram.h b/code/sdk/drivers/boards/brandy_evb/memory_config/include/psram.h index c3a73f593..e9aa73477 100644 --- a/code/sdk/drivers/boards/brandy_evb/memory_config/include/psram.h +++ b/code/sdk/drivers/boards/brandy_evb/memory_config/include/psram.h @@ -1,17 +1,18 @@ -/* - * Copyright (c) @CompanyNameMagicTag 2021-2022. All rights reserved. - * Description: psram memory configurations - * Author: @CompanyNameTag - * Create: 2022-03-09 - */ - -#ifndef PSRAM_H -#define PSRAM_H - -#if PSRAM_DENSITY_MB == 16 -#include "psram_16.h" -#else /* PSRAM_DENSITY_MB == 32 */ -#include "psram_32.h" -#endif - -#endif // PSRAM_H +/* + * Copyright (c) @CompanyNameMagicTag 2021-2022. All rights reserved. + * Description: psram memory configurations + * Author: @CompanyNameTag + * Create: 2022-03-09 + */ + +#ifndef PSRAM_H +#define PSRAM_H + +#include "product.h" +#if PSRAM_DENSITY_MB == 16 +#include "psram_16.h" +#else /* PSRAM_DENSITY_MB == 32 */ +#include "psram_32.h" +#endif + +#endif // PSRAM_H diff --git a/code/sdk/drivers/chips/brandy/config/pmp_config.c b/code/sdk/drivers/chips/brandy/config/pmp_config.c index 6d7a37eaf..4429a633b 100644 --- a/code/sdk/drivers/chips/brandy/config/pmp_config.c +++ b/code/sdk/drivers/chips/brandy/config/pmp_config.c @@ -1,151 +1,151 @@ -/* - * Copyright (c) @CompanyNameMagicTag 2021-2022. All rights reserved. - * Description: chip pmp init config file. - */ -#include "pmp_config.h" -#include "stdbool.h" -#include "drv_pmp.h" -#include "memory_config.h" - -#define L2MEM_DSP_ADDR_START 0x60100000 -#define L2MEM_DSP_ADDR_LEN 0x100000 - -#define L2MEM_GPU_ADDR_START 0x60240000 -#define L2MEM_GPU_ADDR_LEN 0x20000 - -#if PSRAM_DENSITY_MB == 16 -#define PSRAM_ADDR_START 0x6C000000 -#define PSRAM_ADDR_LEN 0x800000 -#define PSRAM_SECOND_ADDR_START 0x6C800000 -#define PSRAM_SECOND_ADDR_LEN 0x800000 -#else /* PSRAM_DENSITY_MB == 32 */ -#define PSRAM_ADDR_START 0x6C000000 -#define PSRAM_ADDR_LEN 0x1000000 -#define PSRAM_SECOND_ADDR_START 0x6D000000 -#define PSRAM_SECOND_ADDR_LEN 0x1000000 -#endif - -#define NOR_FLASH_ADDR_START FLASH_START -#define NOR_FLASH_ADDR_LEN FLASH_LENGTH - -#define BOOTROM_PMP_LENGTH 0x10000 -#define ITCM_PMP_LENGTH 0x10000 -#define ITCM_PMP_SECOND_LENGTH 0x20000 -#define DTCM_PMP_LENGTH 0x80000 - -typedef enum { - BOOTROM_IDX = 0, - ITCM_IDX = 1, - ITCM_SECOND_IDX = 2, - DTCM_IDX = 3, - L2RAM_DSP_IDX = 4, - L2RAM_GPU_IDX = 5, -#ifdef CONFIG_PSRAM_SUPPORT - PSRAM_IDX, - PSRAM_SECOND_IDX, -#endif - NOR_FLASH_IDX, - MAX_REGION_NUM -} region_index_t; - -pmp_conf_t g_region_attr[MAX_REGION_NUM]; - -static void pmp_init_config(void) -{ - /* bootrom 不可读不可写不可执行 */ - g_region_attr[BOOTROM_IDX].idx = BOOTROM_IDX; - g_region_attr[BOOTROM_IDX].addr = ROM_START; - g_region_attr[BOOTROM_IDX].size = BOOTROM_PMP_LENGTH; - g_region_attr[BOOTROM_IDX].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE; - g_region_attr[BOOTROM_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_READ_ONLY_NEXECUTE; - g_region_attr[BOOTROM_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; - g_region_attr[BOOTROM_IDX].conf.lock = true; - - /* ITCM 第一段 可读可执行不可写 */ - g_region_attr[ITCM_IDX].idx = ITCM_IDX; - g_region_attr[ITCM_IDX].addr = APP_ITCM_ORIGIN; - g_region_attr[ITCM_IDX].size = ITCM_PMP_LENGTH; - g_region_attr[ITCM_IDX].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE; - g_region_attr[ITCM_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_READ_ONLY_EXECUTE; - g_region_attr[ITCM_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; - g_region_attr[ITCM_IDX].conf.lock = true; - - /* ITCM 第二段 可读可执行不可写 */ - g_region_attr[ITCM_SECOND_IDX].idx = ITCM_SECOND_IDX; - g_region_attr[ITCM_SECOND_IDX].addr = (APP_ITCM_ORIGIN + ITCM_PMP_LENGTH); - g_region_attr[ITCM_SECOND_IDX].size = ITCM_PMP_SECOND_LENGTH; - g_region_attr[ITCM_SECOND_IDX].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE; - g_region_attr[ITCM_SECOND_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_READ_ONLY_EXECUTE; - g_region_attr[ITCM_SECOND_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; - g_region_attr[ITCM_SECOND_IDX].conf.lock = true; - - /* DTCM 可读可写不可执行 */ - g_region_attr[DTCM_IDX].idx = DTCM_IDX; - g_region_attr[DTCM_IDX].addr = APP_DTCM_ORIGIN; - g_region_attr[DTCM_IDX].size = DTCM_PMP_LENGTH; - g_region_attr[DTCM_IDX].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE; - g_region_attr[DTCM_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_RW_NEXECUTE; - g_region_attr[DTCM_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; - g_region_attr[DTCM_IDX].conf.lock = true; - - /* DSP L2MEM 可读可执行可写 打开cache属性 */ - g_region_attr[L2RAM_DSP_IDX].idx = L2RAM_DSP_IDX; - g_region_attr[L2RAM_DSP_IDX].addr = L2MEM_DSP_ADDR_START; - g_region_attr[L2RAM_DSP_IDX].size = L2MEM_DSP_ADDR_LEN; -#ifdef MEMORY_MINI - g_region_attr[L2RAM_DSP_IDX].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE; -#else - g_region_attr[L2RAM_DSP_IDX].conf.pmp_attr = PMP_ATTR_WRITEBACK_RWALLOCATE; -#endif - g_region_attr[L2RAM_DSP_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_RW_EXECUTE; - g_region_attr[L2RAM_DSP_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; - g_region_attr[L2RAM_DSP_IDX].conf.lock = true; - - /* GPU L2MEM 可读可执行可写 打开cache属性 */ - g_region_attr[L2RAM_GPU_IDX].idx = L2RAM_GPU_IDX; - g_region_attr[L2RAM_GPU_IDX].addr = L2MEM_GPU_ADDR_START; - g_region_attr[L2RAM_GPU_IDX].size = L2MEM_GPU_ADDR_LEN; -#ifdef MEMORY_MINI - g_region_attr[L2RAM_GPU_IDX].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE; -#else - g_region_attr[L2RAM_GPU_IDX].conf.pmp_attr = PMP_ATTR_WRITEBACK_RWALLOCATE; -#endif - g_region_attr[L2RAM_GPU_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_RW_EXECUTE; - g_region_attr[L2RAM_GPU_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; - g_region_attr[L2RAM_GPU_IDX].conf.lock = true; - -#ifdef CONFIG_PSRAM_SUPPORT - /* PSRAM 第一段 可读可写不可执行 打开cache属性 */ - g_region_attr[PSRAM_IDX].idx = PSRAM_IDX; - g_region_attr[PSRAM_IDX].addr = PSRAM_ADDR_START; - g_region_attr[PSRAM_IDX].size = PSRAM_ADDR_LEN; - g_region_attr[PSRAM_IDX].conf.pmp_attr = PMP_ATTR_WRITEBACK_NO_ALLOCATE; - g_region_attr[PSRAM_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_RW_NEXECUTE; - g_region_attr[PSRAM_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; - g_region_attr[PSRAM_IDX].conf.lock = true; - - /* PSRAM 第二段 可读可写不可执行 关闭cache属性 */ - g_region_attr[PSRAM_SECOND_IDX].idx = PSRAM_SECOND_IDX; - g_region_attr[PSRAM_SECOND_IDX].addr = PSRAM_SECOND_ADDR_START; - g_region_attr[PSRAM_SECOND_IDX].size = PSRAM_SECOND_ADDR_LEN; - g_region_attr[PSRAM_SECOND_IDX].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE; - g_region_attr[PSRAM_SECOND_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_RW_NEXECUTE; - g_region_attr[PSRAM_SECOND_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; - g_region_attr[PSRAM_SECOND_IDX].conf.lock = true; -#endif - - /* Flash 可读不可写可执行 打开cache属性 */ - g_region_attr[NOR_FLASH_IDX].idx = NOR_FLASH_IDX; - g_region_attr[NOR_FLASH_IDX].addr = NOR_FLASH_ADDR_START; - g_region_attr[NOR_FLASH_IDX].size = NOR_FLASH_ADDR_LEN; - g_region_attr[NOR_FLASH_IDX].conf.pmp_attr = PMP_ATTR_WRITEBACK_RWALLOCATE; - g_region_attr[NOR_FLASH_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_READ_ONLY_EXECUTE; - g_region_attr[NOR_FLASH_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; - g_region_attr[NOR_FLASH_IDX].conf.lock = true; -} - -void pmp_init(void) -{ - pmp_init_config(); - uapi_pmp_config(g_region_attr, MAX_REGION_NUM); -} +/* + * Copyright (c) @CompanyNameMagicTag 2021-2022. All rights reserved. + * Description: chip pmp init config file. + */ +#include "pmp_config.h" +#include "stdbool.h" +#include "drv_pmp.h" +#include "memory_config.h" +#include "product.h" +#define L2MEM_DSP_ADDR_START 0x60100000 +#define L2MEM_DSP_ADDR_LEN 0x100000 + +#define L2MEM_GPU_ADDR_START 0x60240000 +#define L2MEM_GPU_ADDR_LEN 0x20000 + +#if PSRAM_DENSITY_MB == 16 +#define PSRAM_ADDR_START 0x6C000000 +#define PSRAM_ADDR_LEN 0x800000 +#define PSRAM_SECOND_ADDR_START 0x6C800000 +#define PSRAM_SECOND_ADDR_LEN 0x800000 +#else /* PSRAM_DENSITY_MB == 32 */ +#define PSRAM_ADDR_START 0x6C000000 +#define PSRAM_ADDR_LEN 0x1000000 +#define PSRAM_SECOND_ADDR_START 0x6D000000 +#define PSRAM_SECOND_ADDR_LEN 0x1000000 +#endif + +#define NOR_FLASH_ADDR_START FLASH_START +#define NOR_FLASH_ADDR_LEN FLASH_LENGTH + +#define BOOTROM_PMP_LENGTH 0x10000 +#define ITCM_PMP_LENGTH 0x10000 +#define ITCM_PMP_SECOND_LENGTH 0x20000 +#define DTCM_PMP_LENGTH 0x80000 + +typedef enum { + BOOTROM_IDX = 0, + ITCM_IDX = 1, + ITCM_SECOND_IDX = 2, + DTCM_IDX = 3, + L2RAM_DSP_IDX = 4, + L2RAM_GPU_IDX = 5, +#ifdef CONFIG_PSRAM_SUPPORT + PSRAM_IDX, + PSRAM_SECOND_IDX, +#endif + NOR_FLASH_IDX, + MAX_REGION_NUM +} region_index_t; + +pmp_conf_t g_region_attr[MAX_REGION_NUM]; + +static void pmp_init_config(void) +{ + /* bootrom 不可读不可写不可执行 */ + g_region_attr[BOOTROM_IDX].idx = BOOTROM_IDX; + g_region_attr[BOOTROM_IDX].addr = ROM_START; + g_region_attr[BOOTROM_IDX].size = BOOTROM_PMP_LENGTH; + g_region_attr[BOOTROM_IDX].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE; + g_region_attr[BOOTROM_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_READ_ONLY_NEXECUTE; + g_region_attr[BOOTROM_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; + g_region_attr[BOOTROM_IDX].conf.lock = true; + + /* ITCM 第一段 可读可执行不可写 */ + g_region_attr[ITCM_IDX].idx = ITCM_IDX; + g_region_attr[ITCM_IDX].addr = APP_ITCM_ORIGIN; + g_region_attr[ITCM_IDX].size = ITCM_PMP_LENGTH; + g_region_attr[ITCM_IDX].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE; + g_region_attr[ITCM_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_READ_ONLY_EXECUTE; + g_region_attr[ITCM_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; + g_region_attr[ITCM_IDX].conf.lock = true; + + /* ITCM 第二段 可读可执行不可写 */ + g_region_attr[ITCM_SECOND_IDX].idx = ITCM_SECOND_IDX; + g_region_attr[ITCM_SECOND_IDX].addr = (APP_ITCM_ORIGIN + ITCM_PMP_LENGTH); + g_region_attr[ITCM_SECOND_IDX].size = ITCM_PMP_SECOND_LENGTH; + g_region_attr[ITCM_SECOND_IDX].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE; + g_region_attr[ITCM_SECOND_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_READ_ONLY_EXECUTE; + g_region_attr[ITCM_SECOND_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; + g_region_attr[ITCM_SECOND_IDX].conf.lock = true; + + /* DTCM 可读可写不可执行 */ + g_region_attr[DTCM_IDX].idx = DTCM_IDX; + g_region_attr[DTCM_IDX].addr = APP_DTCM_ORIGIN; + g_region_attr[DTCM_IDX].size = DTCM_PMP_LENGTH; + g_region_attr[DTCM_IDX].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE; + g_region_attr[DTCM_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_RW_NEXECUTE; + g_region_attr[DTCM_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; + g_region_attr[DTCM_IDX].conf.lock = true; + + /* DSP L2MEM 可读可执行可写 打开cache属性 */ + g_region_attr[L2RAM_DSP_IDX].idx = L2RAM_DSP_IDX; + g_region_attr[L2RAM_DSP_IDX].addr = L2MEM_DSP_ADDR_START; + g_region_attr[L2RAM_DSP_IDX].size = L2MEM_DSP_ADDR_LEN; +#ifdef MEMORY_MINI + g_region_attr[L2RAM_DSP_IDX].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE; +#else + g_region_attr[L2RAM_DSP_IDX].conf.pmp_attr = PMP_ATTR_WRITEBACK_RWALLOCATE; +#endif + g_region_attr[L2RAM_DSP_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_RW_EXECUTE; + g_region_attr[L2RAM_DSP_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; + g_region_attr[L2RAM_DSP_IDX].conf.lock = true; + + /* GPU L2MEM 可读可执行可写 打开cache属性 */ + g_region_attr[L2RAM_GPU_IDX].idx = L2RAM_GPU_IDX; + g_region_attr[L2RAM_GPU_IDX].addr = L2MEM_GPU_ADDR_START; + g_region_attr[L2RAM_GPU_IDX].size = L2MEM_GPU_ADDR_LEN; +#ifdef MEMORY_MINI + g_region_attr[L2RAM_GPU_IDX].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE; +#else + g_region_attr[L2RAM_GPU_IDX].conf.pmp_attr = PMP_ATTR_WRITEBACK_RWALLOCATE; +#endif + g_region_attr[L2RAM_GPU_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_RW_EXECUTE; + g_region_attr[L2RAM_GPU_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; + g_region_attr[L2RAM_GPU_IDX].conf.lock = true; + +#ifdef CONFIG_PSRAM_SUPPORT + /* PSRAM 第一段 可读可写不可执行 打开cache属性 */ + g_region_attr[PSRAM_IDX].idx = PSRAM_IDX; + g_region_attr[PSRAM_IDX].addr = PSRAM_ADDR_START; + g_region_attr[PSRAM_IDX].size = PSRAM_ADDR_LEN; + g_region_attr[PSRAM_IDX].conf.pmp_attr = PMP_ATTR_WRITEBACK_NO_ALLOCATE; + g_region_attr[PSRAM_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_RW_NEXECUTE; + g_region_attr[PSRAM_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; + g_region_attr[PSRAM_IDX].conf.lock = true; + + /* PSRAM 第二段 可读可写不可执行 关闭cache属性 */ + g_region_attr[PSRAM_SECOND_IDX].idx = PSRAM_SECOND_IDX; + g_region_attr[PSRAM_SECOND_IDX].addr = PSRAM_SECOND_ADDR_START; + g_region_attr[PSRAM_SECOND_IDX].size = PSRAM_SECOND_ADDR_LEN; + g_region_attr[PSRAM_SECOND_IDX].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE; + g_region_attr[PSRAM_SECOND_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_RW_NEXECUTE; + g_region_attr[PSRAM_SECOND_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; + g_region_attr[PSRAM_SECOND_IDX].conf.lock = true; +#endif + + /* Flash 可读不可写可执行 打开cache属性 */ + g_region_attr[NOR_FLASH_IDX].idx = NOR_FLASH_IDX; + g_region_attr[NOR_FLASH_IDX].addr = NOR_FLASH_ADDR_START; + g_region_attr[NOR_FLASH_IDX].size = NOR_FLASH_ADDR_LEN; + g_region_attr[NOR_FLASH_IDX].conf.pmp_attr = PMP_ATTR_WRITEBACK_RWALLOCATE; + g_region_attr[NOR_FLASH_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_READ_ONLY_EXECUTE; + g_region_attr[NOR_FLASH_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT; + g_region_attr[NOR_FLASH_IDX].conf.lock = true; +} + +void pmp_init(void) +{ + pmp_init_config(); + uapi_pmp_config(g_region_attr, MAX_REGION_NUM); +} diff --git a/code/sdk/middleware/services/gui/hal/common/include/graphic_hardware_config.h b/code/sdk/middleware/services/gui/hal/common/include/graphic_hardware_config.h index c37d62b8f..1a95670c7 100644 --- a/code/sdk/middleware/services/gui/hal/common/include/graphic_hardware_config.h +++ b/code/sdk/middleware/services/gui/hal/common/include/graphic_hardware_config.h @@ -17,6 +17,7 @@ #define GRAPHIC_HARDWARE_CONFIG_H #include "memory_config_common.h" +#include "product.h" #ifdef CONFIG_PSRAM_SUPPORT #include "psram.h" #endif -- 2.17.1