#include <math.h>\r
\r
#include "tyhx_hrs_custom.h"\r
-// #include "tyhx_mems.h"\r
+//#include "tyhx_mems.h"\r
\r
#ifdef CHIP_HX3695\r
#include "hx3695.h"\r
#include "hx3695_check_touch.h"\r
#endif\r
#include "hx3695_factory_test.h"\r
+//#include "app_ble_factory_test.h"\r
+\r
+// #include "ui.h"\r
+// #include "app_heart_rate.h"\r
+// #include "lv_dev.h"\r
+// #include "app_task.h"\r
\r
FT_CUSTOM_RESULTS_t hrsresult ={0};\r
\r
int16_t gsen_fifo_y[64]={0};\r
int16_t gsen_fifo_z[64]={0};\r
\r
+\r
#ifdef SPO2_VECTOR\r
#include "spo2_vec.h"\r
uint32_t spo2_send_cnt = 0;\r
#ifdef HRV_TESTVEC\r
#include "hrv_testvec.h"\r
#endif\r
-\r
+// #include "sys_init.h"\r
+// #include "cwm_api.h"\r
int32_t s_buf[256];\r
uint32_t cnt_num = 0;\r
uint32_t phase3_rdy_num = 0;\r
uint8_t spo2_phase_num= 4;\r
uint8_t hrv_phase_num = 4;\r
extern uint8_t data_count;\r
-// extern uint8_t hr_no_living_dur;\r
-uint8_t hr_no_living_dur;\r
-// extern int tyhx_long_timer_tick; \r
+extern uint8_t hr_no_living_dur;\r
+extern uint8_t spo2_no_living_dur;\r
+\r
+extern int tyhx_long_timer_tick; \r
//spo2 agc\r
const uint8_t hx3695_spo2_agc_red_idac = RED_AGC_OFFSET;\r
const uint8_t hx3695_spo2_agc_ir_idac = IR_AGC_OFFSET;\r
uint8_t read_fifo_first_flg = 0;\r
\r
//HRS_INFRARED_THRES\r
-const int32_t hrs_ir_unwear_thres = 4000;\r
-const int32_t hrs_ir_wear_thres = 5000;\r
+const int32_t hrs_ir_unwear_thres = 8000;\r
+const int32_t hrs_ir_wear_thres = 10000;\r
//HRV_INFRARED_THRES\r
-const int32_t hrv_ir_unwear_thres = 4000; //demo143b 25000\r
-const int32_t hrv_ir_wear_thres = 5000;\r
+const int32_t hrv_ir_unwear_thres = 8000; //demo143b 25000\r
+const int32_t hrv_ir_wear_thres = 10000;\r
//SPO2_INFRARED_THRES\r
-const int32_t spo2_ir_unwear_thres = 4000; //demo143b 25000 30000\r
-const int32_t spo2_ir_wear_thres = 5000;\r
+const int32_t spo2_ir_unwear_thres = 8000; //demo143b 25000 30000\r
+const int32_t spo2_ir_wear_thres = 10000;\r
const uint8_t spo2_ir_wear_offset = 15;\r
//CHECK_WEAR_MODE_THRES\r
-const int32_t check_mode_unwear_thre = 20000;\r
-const int32_t check_mode_wear_thre = 30000;\r
+const int32_t check_mode_unwear_thre = 8000;\r
+const int32_t check_mode_wear_thre = 10000;\r
+\r
\r
uint8_t alg_ram[11 * 1024] __attribute__((aligned(4)));\r
//uint8_t alg_ram[10] = {0};\r
const uint16_t MEAN_NUM = 32; //the length of smooth-average ;the value of MEAN_NUM can be given only 256 and 512\r
const uint8_t G_SENSOR = 0; //if =1, open the gsensor mode\r
const uint8_t SPO2_GSEN_POW_THRE = 150; //gsen pow judge move, range:0-200;\r
-const uint32_t SPO2_BASE_LINE_INIT = 135500; //spo2 baseline init, = 103000 + ratio(a variable quantity,depends on different cases)*SPO2_SLOPE\r
+const uint32_t SPO2_BASE_LINE_INIT = 138000; //spo2 baseline init, = 103000 + ratio(a variable quantity,depends on different cases)*SPO2_SLOPE\r
const int32_t SOP2_DEGLITCH_THRE = 100000; //remove signal glitch over this threshold\r
const int32_t SPO2_REMOVE_JUMP_THRE = 50000; //remove signal jump over this threshold\r
const uint32_t SPO2_SLOPE = 50000; //increase this slope, spo2 reduce more\r
static int32_t cali_data_cnt = 0;\r
#endif\r
\r
-\r
-\r
// us 延时函数， 客户需填写\r
void hx3695_delay_us(uint32_t us)\r
{\r
}\r
\r
// i2c 连读函数， 客户需填写\r
-bool hx3695_brust_read_reg(uint8_t addr, uint8_t *buf, uint8_t length)\r
+bool hx3695_brust_read_reg(uint8_t addr, uint8_t *buf, uint16_t length)\r
{\r
//TYHX_LOG("brust read\r\n");\r
tyhx_read_regs(addr,buf,length);\r
return true;\r
}\r
\r
-\r
+void Efuse_Mode_Check(void)\r
+{\r
+#if 1//def TEST_RELEASE_USE\r
+ PRINT("@@@@@@@@@ Efuse_Mode_Check\r\n");\r
+ uint8_t REG_50_E, REG_51_E, REG_52_E, REG_53_E;\r
+ \r
+ hx3695_write_reg(0x5c, 0x08) ; //0x5c\r
+ hx3695_write_reg(0x5d, 0x02) ; //0x5d\r
+ hx3695_delay_us(10);\r
+ \r
+ hx3695_write_reg(0x5a,0x10); //0x5A\r
+ \r
+ hx3695_write_reg(0x5b,0x04);\r
+ hx3695_write_reg(0x5b,0x00);\r
+ hx3695_delay_us(10);\r
+ hx3695_write_reg(0x5b,0x44);\r
+ hx3695_write_reg(0x5b,0x40);\r
+ \r
+ REG_50_E = hx3695_read_reg(0x50);\r
+ REG_51_E = hx3695_read_reg(0x51);\r
+ REG_52_E = hx3695_read_reg(0x52);\r
+ REG_53_E = hx3695_read_reg(0x53);\r
+ \r
+ hx3695_write_reg(0x5a,0x20); //0x5A\r
+ hx3695_write_reg(0x50,REG_50_E);\r
+ hx3695_write_reg(0x51,REG_51_E);\r
+ hx3695_write_reg(0x52,REG_52_E);\r
+ hx3695_write_reg(0x53,REG_53_E);\r
+\r
+ TYHX_LOG("EFUSE MC2: 0x50=0x%2x 0x51= 0x%2x 0x52= 0x%2x 0x53= 0x%2x \r\n",REG_50_E,REG_51_E,REG_52_E,REG_53_E);\r
+ \r
+ hx3695_write_reg(0x5a,0x00); \r
+ hx3695_write_reg(0x5c,0x00); //0x5c\r
+ hx3695_write_reg(0x5d,0x00); //0x5d\r
+#endif \r
+}\r
+bool Efuse_judge(void)\r
+{\r
+ uint8_t REG_50, REG_51, REG_52, REG_53,REG_50_A;\r
+ \r
+ REG_50 = hx3695_read_reg(0x50); //32k\r
+ REG_51 = hx3695_read_reg(0x51);\r
+ REG_52 = hx3695_read_reg(0x52); \r
+ REG_53 = hx3695_read_reg(0x53); //bit<7> efuse trim flg ==1\r
+ \r
+// hx3695_write_reg(0x5d,0x00); \r
+// hx3695_write_reg(0x5a,0x20); \r
+// REG_50_A=REG_50+1;\r
+// hx3695_write_reg(0x50,REG_50_A); // REG_50+1 \r
+// TYHX_LOG("EFUSE 0x50=%x \r\n",REG_50_A);\r
+// hx3695_write_reg(0x50,REG_51); \r
+// hx3695_write_reg(0x50,REG_52); \r
+// hx3695_write_reg(0x50,REG_53); \r
+ \r
+ TYHX_LOG("EFUSE MC1 :0x50=0x%2x 0x51= 0x%2x 0x52= 0x%2x 0x53= 0x%2x \r\n",REG_50,REG_51,REG_52,REG_53);\r
+ if ((REG_50 == 0x40) && (REG_51 ==0x50) && (REG_52 ==0x10) && (REG_53 ==0x22))\r
+ { \r
+ Efuse_Mode_Check(); \r
+ TYHX_LOG("this chip is before MC \r\n"); \r
+ }\r
+ else\r
+ {\r
+ TYHX_LOG("EFUSE MC3 :0x50=0x%2x 0x51= 0x%2x 0x52= 0x%2x 0x53= 0x%2x \r\n",REG_50,REG_51,REG_52,REG_53);\r
+ TYHX_LOG("this chip is after MC \r\n");\r
+ }\r
+ return true;\r
+}\r
\r
uint32_t hx3695_timers_start(void)\r
{\r
}\r
#endif\r
\r
-\r
-\r
-#define RA_MEM_WRDATA_7_0 0x50\r
-#define RA_MEM_WRDATA_15_8 0x51\r
-#define RA_MEM_WRDATA_23_16 0x52\r
-#define RA_MEM_WRDATA_31_24 0x53\r
-#define RA_MEM_WRDATA_39_32 0x54\r
-#define RA_MEM_WRDATA_47_40 0x55\r
-#define RA_MEM_WRDATA_55_48 0x56\r
-#define RA_MEM_WRDATA_63_56 0x57\r
-#define RA_MEM_PWE_PULSE_CYCLE7_0 0x58\r
-#define RA_MEM_PWE_PULSE_CYCLE10_8 0x59\r
-#define RA_MEM_GLOBAL_CTRL 0x5A\r
-#define RA_MEM_MANNUAL_CTRL 0x5B\r
-#define RA_DEBUG_CFG0 0x5C\r
-#define RA_DEBUG_CFG1 0x5D\r
-\r
-uint8_t REG_50_E, REG_51_E, REG_52_E, REG_53_E;\r
-\r
-void Efuse_Mode_Check(void)\r
-{\r
- uint8_t efuse0, efuse1, efuse2, efuse3;\r
- \r
- hx3695_write_reg(RA_DEBUG_CFG0, 0x8) ; //0x5c\r
- hx3695_write_reg(RA_DEBUG_CFG1, 0x2) ; //0x5d\r
- hx3695_delay_us(1000);\r
- \r
- hx3695_write_reg(RA_MEM_GLOBAL_CTRL,0x10); //0x5A\r
-// delay_us(2000);\r
- \r
- hx3695_write_reg(RA_MEM_MANNUAL_CTRL,0x04);\r
- hx3695_write_reg(RA_MEM_MANNUAL_CTRL,0x00);\r
- \r
- hx3695_write_reg(RA_MEM_MANNUAL_CTRL,0x44);\r
- hx3695_write_reg(RA_MEM_MANNUAL_CTRL,0x40);\r
- \r
- REG_50_E = hx3695_read_reg(0x50);\r
- REG_51_E = hx3695_read_reg(0x51);\r
- REG_52_E = hx3695_read_reg(0x52);\r
- REG_53_E = hx3695_read_reg(0x53);\r
-\r
-// AGC_LOG("0x50=0x%x\r\n", REG_50_E);\r
-// hal_gpt_delay_ms(100);\r
-// AGC_LOG("0x51=0x%x\r\n", REG_51_E);\r
-// hal_gpt_delay_ms(100);\r
-// AGC_LOG("0x52=0x%x\r\n", REG_52_E);\r
-// hal_gpt_delay_ms(100);\r
-// AGC_LOG("0x53=0x%x\r\n", REG_53_E);\r
-// hal_gpt_delay_ms(100);\r
- \r
- hx3695_write_reg(RA_MEM_GLOBAL_CTRL,0x20); //0x5A\r
- hx3695_write_reg(0x50,REG_50_E);\r
- hx3695_write_reg(0x51,REG_51_E);\r
- hx3695_write_reg(0x52,REG_52_E);\r
- hx3695_write_reg(0x53,REG_53_E);\r
-\r
- \r
- hx3695_write_reg(RA_MEM_GLOBAL_CTRL,0x0);\r
- \r
- hx3695_write_reg(RA_DEBUG_CFG0, 0x0); //0x5c\r
- hx3695_write_reg(RA_DEBUG_CFG1, 0x0); //0x5d\r
-\r
-}\r
bool hx3695_chip_check(void)\r
{\r
uint8_t i = 0;\r
uint8_t chip_id = 0;\r
for(i=0; i<5; i++)\r
{\r
- hx3695_write_reg(0x5c, 0x00);\r
+ hx3695_ppg_on();\r
hx3695_delay_ms(5);\r
chip_id = hx3695_read_reg(0x00);\r
\r
if (chip_id == 0x65)\r
{\r
- TYHX_LOG("hx3695_chip_check ok chip_id: 0x%x \r\n",chip_id);\r
- Efuse_Mode_Check();\r
+ printf("hx3695_chip_check ok chip_id: 0x%x \r\n",chip_id);\r
+ //Efuse_Mode_Check();\r
return true;\r
}\r
}\r
\r
- TYHX_LOG(" hx3695_chip_check fail! chip_id: 0x%x \r\n", chip_id);\r
+ printf(" hx3695_chip_check fail! chip_id: 0x%x \r\n", chip_id);\r
\r
return false;\r
}\r
uint8_t chip_id = 0;\r
for(i=0; i<5; i++)\r
{\r
- hx3695_write_reg(0x5c, 0x00);\r
- hx3695_delay_ms(5);\r
+ hx3695_ppg_on();\r
chip_id = hx3695_read_reg(0x00);\r
\r
if (chip_id == 0x65)\r
{\r
- TYHX_LOG("hx3695_chip_check ok chip_id: 0x%x \r\n",chip_id);\r
+ printf("hx3695_chip_check ok chip_id: 0x%x \r\n",chip_id);\r
return chip_id;\r
}\r
}\r
\r
- TYHX_LOG(" hx3695_chip_check fail! chip_id: 0x%x \r\n", chip_id);\r
+ printf(" hx3695_chip_check fail! chip_id: 0x%x \r\n", chip_id);\r
\r
return chip_id;\r
}\r
\r
uint16_t hx3695_read_fifo_data(int32_t *buf, uint8_t phase_num, uint8_t sig)\r
{\r
- uint8_t data_flg_start = 0;\r
- uint8_t data_flg_end = 0;\r
+ uint8_t data_flg_start = 0;\r
+ uint8_t data_flg_end = 0;\r
// int32_t data;\r
- uint8_t databuf[3];\r
- uint32_t ii=0;\r
+ uint8_t databuf[3];\r
+ uint32_t ii=0;\r
uint16_t data_len_h = 0;\r
uint16_t data_len_l = 0;\r
uint16_t fifo_data_length = 0;\r
data_len_h = hx3695_read_reg(0x21);\r
data_len_l = hx3695_read_reg(0x20);\r
fifo_data_length = (((data_len_h&0x01)<<8)|data_len_l);\r
-// AGC_LOG("fifo_data_length = %d\r\n", fifo_data_length); \r
+// SEGGER_RTT_printf(0,"fifo_data_length = %d\r\n", fifo_data_length); \r
if(fifo_data_length<2*phase_num)\r
{\r
return 0;\r
}\r
fifo_read_length = ((fifo_data_length-phase_num)/phase_num)*phase_num;\r
-// AGC_LOG("fifo_data_length_change = %d\r\n", fifo_read_length);\r
+// SEGGER_RTT_printf(0,"fifo_data_length_change = %d\r\n", fifo_read_length);\r
fifo_read_bytes = fifo_read_length*3;\r
if(read_fifo_first_flg == 1)\r
{\r
hx3695_brust_read_reg(0x22, fifo_data_buf, fifo_read_bytes); \r
// for(ii=0; ii<fifo_read_bytes; ii++)\r
// {\r
-// AGC_LOG("%d/%d, %d\r\n", ii+1,fifo_read_bytes,fifo_data_buf[ii]); \r
+// SEGGER_RTT_printf(0,"%d/%d, %d\r\n", ii+1,fifo_read_bytes,fifo_data_buf[ii]); \r
// }\r
for(ii=0; ii<fifo_read_length; ii++)\r
{\r
buf[ii] = (int32_t)(fifo_data_buf[ii*3]|(fifo_data_buf[ii*3+1]<<8)|((fifo_data_buf[ii*3+2]&0x1f)<<16));\r
}\r
}\r
- AGC_LOG("fifo_length = %d/%d, %d %d\r\n", ii+1,fifo_read_length,buf[ii],fifo_data_buf[ii*3+2]>>5); \r
+ SEGGER_RTT_printf(0,"fifo_length = %d/%d, %d %d\r\n", ii+1,fifo_read_length,buf[ii],fifo_data_buf[ii*3+2]>>5); \r
}\r
data_flg_start = fifo_data_buf[2]>>5;\r
data_flg_end = fifo_data_buf[fifo_read_bytes-1]>>5;\r
} \r
for(ii=0; ii<fifo_out_length; ii++)\r
{\r
-// AGC_LOG("fifo_buf %d/%d, %d\r\n", ii+1,fifo_out_length,buf[ii]); \r
+// SEGGER_RTT_printf(0,"fifo_buf %d/%d, %d\r\n", ii+1,fifo_out_length,buf[ii]); \r
}\r
fifo_out_length = fifo_out_length+phase_num-data_flg_end - 1;\r
fifo_out_count = fifo_out_length/phase_num;\r
{\r
\r
hx3695_delay_ms(5);\r
- hx3695_write_reg(0x5c, 0x02);\r
+ hx3695_write_reg(0x02, 0x01);\r
}\r
\r
void hx3695_ppg_on(void)\r
{\r
- hx3695_write_reg(0x5c, 0x00);\r
+ hx3695_write_reg(0x02, 0x00);\r
hx3695_delay_ms(5);\r
}\r
\r
void hx3695_hrs_ppg_init(void) // ppg fs=25hz, phase conversion ready interupt en\r
{\r
uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
- uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */\r
+ uint32_t prf_clk_num = 32000/sample_rate*24/25; /*period in clk num, num = Fclk/fs */\r
\r
-// uint16_t fifo_watermark= 81 ;\r
+ uint16_t fifo_watermark= 81 ;\r
uint8_t adc_rst_post_num=0; /* 00=16,01=32,10=64,11=128*/ \r
- uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
+ uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/\r
uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/\r
- uint8_t phase7_8_internal = 0; /* phase7 and phase8 prf internal cfg */\r
+ uint8_t phase7_8_internal = 0; /* phase7 and phase8 prf internal cfg */\r
\r
uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase5_enable = 1; /*phase5_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase6_enable = 1; /*phase6_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase7_enable = 1; /*phase7_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ \r
\r
uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- \r
- uint8_t phase1_mux_sel = 0; /* sel phase1*/\r
- uint8_t phase2_mux_sel = 1; /* sel phase2*/\r
- uint8_t phase3_mux_sel = 2; /* sel phase3*/\r
- uint8_t phase4_mux_sel = 3; /* sel phase4*/\r
- uint8_t phase5_mux_sel = 4; /* sel phase5*/\r
- uint8_t phase6_mux_sel = 5; /* sel phase6*/\r
- uint8_t phase7_mux_sel = 6; /* sel phase7*/\r
- uint8_t phase8_mux_sel = 7; /* sel phase8*/\r
+ uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ \r
+ uint8_t phase1_mux_sel = 0; /* sel phase1*/\r
+ uint8_t phase2_mux_sel = 1; /* sel phase2*/\r
+ uint8_t phase3_mux_sel = 2; /* sel phase3*/\r
+ uint8_t phase4_mux_sel = 3; /* sel phase4*/\r
+ uint8_t phase5_mux_sel = 4; /* sel phase5*/\r
+ uint8_t phase6_mux_sel = 5; /* sel phase6*/\r
+ uint8_t phase7_mux_sel = 6; /* sel phase7*/\r
+ uint8_t phase8_mux_sel = 7; /* sel phase8*/\r
\r
\r
- uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
uint8_t phase1_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */\r
uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */\r
- uint8_t phase1_pd_sel = 0x0F; //0x03 /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase1_pd_sel = HRS_PD; //0x03 /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase1_ldr2_cur = 0;\r
-// uint8_t phase1_of_idac1_cur = 0;\r
-// uint8_t phase1_of_idac2_cur = 0;\r
+ uint8_t phase1_ldr2_cur = 0;\r
uint8_t phase1_ad_inr_ctrl = 3;\r
uint8_t phase1_ad_of_idac_ctrl = 0;\r
-// uint8_t afe_offset = 0;\r
- uint8_t phase1_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase1_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
\r
\r
- uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
uint8_t phase2_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase2_led_drv1_cha_sel = 0x50; //0x10 //GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase2_led_drv1_cha_sel = GREEN_LED_SLE; //0x10 //GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase2_led_drv2_cha_sel = 0;\r
- uint8_t phase2_pd_sel = 0x0F; //0x0C //0x03 /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase2_pd_sel = HRS_PD; //0x0C //0x03 /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase2_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase2_ldr2_cur = 0;\r
-// uint8_t phase2_of_idac1_cur = 0;\r
-// uint8_t phase2_of_idac2_cur = 0;\r
+ uint8_t phase2_ldr2_cur = 0;\r
uint8_t phase2_ad_inr_ctrl = 3;\r
uint8_t phase2_ad_of_idac_ctrl = 0;\r
-// uint8_t phase2_afe_offset = 0;\r
- uint8_t phase2_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase2_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
\r
uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
uint8_t phase3_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase3_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase3_led_drv2_cha_sel = 0;\r
- uint8_t phase3_pd_sel = 0x0F; //0x03 /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase3_pd_sel = HRS_PD; //0x03 /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase3_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase3_ldr2_cur = 0;\r
-// uint8_t phase3_of_idac1_cur = 0;\r
-// uint8_t phase3_of_idac2_cur = 0;\r
+ uint8_t phase3_ldr2_cur = 0;\r
uint8_t phase3_ad_inr_ctrl = 3;\r
uint8_t phase3_ad_of_idac_ctrl = 0;\r
-// uint8_t phase3_afe_offset = 0;\r
- uint8_t phase3_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase3_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
\r
uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
uint8_t phase4_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase4_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase4_led_drv2_cha_sel = 0;\r
- uint8_t phase4_pd_sel = 0x0F; //0x0C /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase4_pd_sel = HRS_PD; //0x0C /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase4_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase5_led_drv1_cha_sel = 0x50; //0x10 /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase5_led_drv1_cha_sel = 0; //0x10 /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase5_led_drv2_cha_sel = 0;\r
- uint8_t phase5_pd_sel = 0x0F; //0x0C /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase5_pd_sel = HRS_PD; //0x0C /* 1 = pd1; 2 = pd2; */\r
uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase6_led_drv2_cha_sel = 0;\r
- uint8_t phase6_pd_sel = 0x0F; //0x0C /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase6_pd_sel = HRS_PD; //0x0C /* 1 = pd1; 2 = pd2; */\r
uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase7_led_drv2_cha_sel = 0;\r
- uint8_t phase7_pd_sel = 0x02; //0x0C /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase7_pd_sel = SPO2_PD; //0x0C /* 1 = pd1; 2 = pd2; */\r
uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase8_led_drv1_cha_sel = 0x20; //0x40 //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase8_led_drv1_cha_sel = IR_LED_SLE; //0x40 //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase8_led_drv2_cha_sel = 0;\r
- uint8_t phase8_pd_sel = 0x02; //0x0C /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase8_pd_sel = SPO2_PD; //0x0C /* 1 = pd1; 2 = pd2; */\r
uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase8_ldr1_cur = 32; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
hx3695_write_reg(0X6c, 0X00); \r
hx3695_write_reg(0X6d, 0X37); \r
hx3695_write_reg(0X6e, 0X82); \r
- hx3695_write_reg(0X6f, 0X08);\r
+ hx3695_write_reg(0X6f, 0X00);\r
/////////FIFO and adc conversion ready config////////\r
/////////FIFO and adc conversion ready config////////\r
#if defined(PPG_INT_MODE)\r
hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
+ 0011=p4;0100=p5;0101=p6;0110=p7;\ bits<7> fifo enble\r
hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear\r
hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int\r
#elif defined(INT_MODE) //FIFO_ALL_MOST_FULL)\r
hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark\r
hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] \r
hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear\r
hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
\r
#else\r
- hx3695_write_reg(0X1b, 0x92); // bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\r
- // 0011=p4;0100=p5;0101=p6;0110=p7;\r
- // bits<7> fifo enble \r
+ hx3695_write_reg(0X1b, 0x92); \r
+ \r
hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int\r
\r
#endif\r
void hx3695_spo2_ppg_init(void) //20200615 ericy ppg fs=25hz, phase3 conversion ready interupt en\r
{\r
uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
- uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */\r
+ uint32_t prf_clk_num = 32000/sample_rate*24/25; /*period in clk num, num = Fclk/fs */\r
\r
-// uint16_t fifo_watermark= 250 ;\r
+ uint16_t fifo_watermark= 250 ;\r
uint8_t adc_rst_post_num=0; /* 00=16,01=32,10=64,11=128*/ \r
uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/\r
uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */\r
uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */\r
- uint8_t phase1_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase1_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
uint8_t phase2_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase2_led_drv1_cha_sel = 0X50; //GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase2_led_drv1_cha_sel = GREEN_LED_SLE; //GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase2_led_drv2_cha_sel = 0x00;\r
- uint8_t phase2_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase2_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase2_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase3_led_drv1_cha_sel = 0; //RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase3_led_drv2_cha_sel = 0;\r
- uint8_t phase3_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase3_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase3_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
uint8_t phase4_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase4_led_drv1_cha_sel = 0x80; //0x20 //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase4_led_drv1_cha_sel = RED_LED_SLE; //0x20 //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase4_led_drv2_cha_sel = 0;\r
- uint8_t phase4_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase4_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase4_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase5_led_drv1_cha_sel = 0x00; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase5_led_drv2_cha_sel = 0;\r
- uint8_t phase5_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase5_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase6_led_drv1_cha_sel = 0x20; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase6_led_drv1_cha_sel = IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase6_led_drv2_cha_sel = 0;\r
- uint8_t phase6_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase6_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase7_led_drv2_cha_sel = 0;\r
- uint8_t phase7_pd_sel = 0x02; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase7_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase8_led_drv1_cha_sel = 0x20; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase8_led_drv1_cha_sel = IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase8_led_drv2_cha_sel = 0;\r
- uint8_t phase8_pd_sel = 0x02; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase8_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase8_ldr1_cur = 20; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase8_ldr1_cur = 32; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase8_ldr2_cur = 0;\r
// uint8_t phase8_of_idac1_cur = 0;\r
// uint8_t phase8_of_idac2_cur = 0;\r
hx3695_write_reg(0X6c, 0X00); \r
hx3695_write_reg(0X6d, 0X37); \r
hx3695_write_reg(0X6e, 0X82); \r
- hx3695_write_reg(0X6f, 0X08);\r
+ hx3695_write_reg(0X6f, 0X00);\r
/////////FIFO and adc conversion ready config////////\r
/////////FIFO and adc conversion ready config////////\r
#if defined(PPG_INT_MODE)\r
hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
+ 0011=p4;0100=p5;0101=p6;0110=p7;\ bits<7> fifo enble\r
hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear\r
hx3695_write_reg(0X38, 0x08); // int sel,00=close almost full int,04=enable almost full int\r
#elif defined(INT_MODE) //(FIFO_ALL_MOST_FULL)\r
hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
\r
#else\r
- hx3695_write_reg(0X1b, 0x91);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\r
- // 0011=p4;0100=p5;0101=p6;0110=p7;\r
- // bits<7> fifo enble \r
+ hx3695_write_reg(0X1b, 0x91);\r
hx3695_write_reg(0X36, 0x00); \r
\r
hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int\r
void hx3695_hrv_ppg_init(void) //20200615 ericy ppg fs=25hz, phase3 conversion ready interupt en\r
{\r
uint16_t sample_rate = 125; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
- uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */\r
+ uint32_t prf_clk_num = 32000/sample_rate*24/25; /*period in clk num, num = Fclk/fs */\r
\r
-;\r
uint8_t adc_rst_post_num=0; /* 00=16,01=32,10=64,11=128*/ \r
uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/\r
uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/\r
uint8_t phase7_8_internal = 0; /* phase7 and phase8 prf internal cfg */\r
\r
+ uint16_t fifo_watermark= 164 ;\r
uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ \r
hx3695_write_reg(0X6c, 0X00); \r
hx3695_write_reg(0X6d, 0X37); \r
hx3695_write_reg(0X6e, 0X82); \r
- hx3695_write_reg(0X6f, 0X08);\r
+ hx3695_write_reg(0X6f, 0X00);\r
/////////FIFO and adc conversion ready config////////\r
/////////FIFO and adc conversion ready config////////\r
#if defined(PPG_INT_MODE)\r
0011=p4;0100=p5;0101=p6;0110=p7;\\r
bits<7> fifo enble\r
hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear\r
hx3695_write_reg(0X38, 0x08); // int sel,00=close almost full int,04=enable almost full int\r
#elif defined(INT_MODE) //(FIFO_ALL_MOST_FULL)\r
hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
\r
#else\r
- hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\r
- // 0011=p4;0100=p5;0101=p6;0110=p7;\r
- // bits<7> fifo enble \r
+ hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
+ 0011=p4;0100=p5;0101=p6;0110=p7;\\r
+ bits<7> fifo enble \r
hx3695_write_reg(0X36, 0x00); \r
\r
hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int\r
#ifdef CHECK_TOUCH_LIB\r
void hx3695_check_touch_init(void) //\r
{ \r
- uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
- uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */\r
+ uint16_t sample_rate = 5; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
+ uint32_t prf_clk_num = 32000/sample_rate*24/25; /*period in clk num, num = Fclk/fs */\r
\r
-// uint16_t fifo_watermark= 250 ;\r
+ uint16_t fifo_watermark= 250 ;\r
uint8_t adc_rst_post_num= 0; /* 00=16,01=32,10=64,11=128*/ \r
uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/\r
uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */\r
uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */\r
- uint8_t phase1_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase1_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase2_led_drv1_cha_sel = 0; //GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase2_led_drv2_cha_sel = 0;\r
- uint8_t phase2_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase2_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase2_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase3_led_drv1_cha_sel = 0; //RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase3_led_drv2_cha_sel = 0;\r
- uint8_t phase3_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase3_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase3_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase4_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase4_led_drv2_cha_sel = 0;\r
- uint8_t phase4_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase4_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase4_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase5_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase5_led_drv2_cha_sel = 0;\r
- uint8_t phase5_pd_sel = 4; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase5_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
\r
uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase6_tia_cap = SPO2_PD; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase6_led_drv2_cha_sel = 0;\r
uint8_t phase6_pd_sel = 4; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase7_led_drv2_cha_sel = 0;\r
- uint8_t phase7_pd_sel = 0x00; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase7_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase8_led_drv1_cha_sel = 0x20;//0x40; //IR_LED_SLE /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase8_led_drv1_cha_sel = IR_LED_SLE;//0x40; //IR_LED_SLE /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase8_led_drv2_cha_sel = 0;\r
- uint8_t phase8_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase8_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase8_ldr1_cur = 20; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase8_ldr1_cur = 32; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
uint8_t phase8_ldr2_cur = 0;\r
// uint8_t phase8_of_idac1_cur = 0;\r
// uint8_t phase8_of_idac2_cur = 0;\r
hx3695_write_reg(0X6c, 0X00); \r
hx3695_write_reg(0X6d, 0X37); \r
hx3695_write_reg(0X6e, 0X82); \r
- hx3695_write_reg(0X6f, 0X08);\r
+ hx3695_write_reg(0X6f, 0X00);\r
/////////FIFO and adc conversion ready config////////\r
/////////FIFO and adc conversion ready config////////\r
#if defined(PPG_INT_MODE)\r
0011=p4;0100=p5;0101=p6;0110=p7;\\r
bits<7> fifo enble\r
hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear\r
- hx3695_write_reg(0X38, 0x08); // int sel,00=close almost full int,04=enable almost full int\r
+ hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int\r
#elif defined(INT_MODE) //(FIFO_ALL_MOST_FULL)\r
hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
0011=p4;0100=p5;0101=p6;0110=p7;\\r
hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
\r
#else\r
- hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\r
- // 0011=p4;0100=p5;0101=p6;0110=p7;\r
- // bits<7> fifo enble \r
- hx3695_write_reg(0X36, 0x00); //intrupt \r
+ hx3695_write_reg(0X1b, 0x92);\r
+\r
+ hx3695_write_reg(0X36, 0x00); \r
\r
hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int\r
\r
bool hx3695_init(WORK_MODE_T mode)\r
{\r
hx3695_msg_callback_t func;\r
- TYHX_LOG(" hx3695_init mode : %d \n", mode);\r
+\r
+ TYHX_LOG("this chip hx3695_init mode: %d !! \r\n", mode);\r
\r
+ hx3695_ppg_on();\r
+\r
+ Efuse_judge(); //MC前后芯片判断\r
+ // Efuse_Mode_Check();\r
work_mode_flag = mode;\r
hx3695_data_reset();\r
hx3695_vin_check(3800);\r
case HRS_MODE:\r
TYHX_LOG(" hx3695_init mode : HRS_MODE \n");\r
#ifdef HRS_ALG_LIB\r
- tyhx_hrs_set_alg_para(NORMAL_MODE, 150, 1);\r
-\r
- tyhx_hrs_set_living(1, 15, 30);\r
+ tyhx_hrs_set_living(1, 10, 30);\r
if(hx3695_hrs_enable()== SENSOR_OP_FAILED)\r
{\r
return false;\r
tyhx_spo2_para_barelychange(MEAN_NUM,SOP2_DEGLITCH_THRE,SPO2_REMOVE_JUMP_THRE, \\r
SPO2_LOW_CLIP_END_TIME,SPO2_LOW_CLIP_DN,SPO2_NORMAL_CLIP_DN, \\r
IR_AC_TOUCH_THRE,IR_FFT_POW_THRE,SPO2_CALI,SLOPE_PARA_MAX,SLOPE_PARA_MIN);\r
- tyhx_spo2_set_living(1, 15, 30);\r
+ tyhx_spo2_set_living(1, 7, 20);\r
if(hx3695_spo2_enable()== SENSOR_OP_FAILED)\r
{\r
return false;\r
func(HX3695_MSG_TYPE_LEAKLIGHT_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t));\r
}\r
break;\r
- return true;\r
-\r
- break;\r
\r
case FT_GRAY_CARD_MODE:\r
if (!hx3695_chip_check())\r
break;\r
\r
case FT_SINGLE_CHECK_MODE:\r
+ if (!hx3695_chip_check())\r
+ {\r
+ AGC_LOG("hx3695 check id failed!\r\n");\r
+ return false;\r
+ }\r
hx3695_factroy_test(SINGLE_CHECK_TEST);\r
break;\r
\r
case FT_LED_OFF_MODE:\r
hx3695_factroy_test(LED_OFF_TEST);\r
break;\r
-\r
+ \r
case FT_WEAR_MODE:\r
hx3695_factroy_test(WEAR_MODE_TEST);\r
break;\r
-\r
+ // case NEW_PPG_TEST_MODE:\r
+ // hx3695_factroy_test(NEW_PPG_TEST);\r
+ // break;\r
case LAB_TEST_MODE:\r
#ifdef LAB_TEST\r
if(hx3695_lab_test_enable()== SENSOR_OP_FAILED)\r
\r
void hx3695_agc_Int_handle(void)\r
{\r
+ TYHX_LOG(" hx3695_init mode : HRS_MODE \n");\r
switch (work_mode_flag)\r
{\r
case HRS_MODE:\r
#endif\r
}\r
\r
+static uint32_t ft_ppg_green = 0;\r
+static uint32_t ft_ppg_iir = 0;\r
\r
void hx3695_factory_test_process(uint8_t data[], uint8_t mode, uint8_t* ppg_src)\r
{\r
extern bool factory_test_flag;\r
- extern bool factory_test_aging;\r
extern bool factory_test_sensor_on;\r
- if(factory_test_flag == false || factory_test_aging != false) return;\r
+ extern bool factory_test_aging;\r
+ \r
+ if(factory_test_flag == false) return;\r
if(factory_test_sensor_on == true ) return;\r
\r
static uint8_t ppg_data[15] = {0};\r
+ uint32_t test = 0;\r
+// uint32_t green = 0;\r
+// uint32_t red = 0;\r
+// uint32_t iir = 0;\r
\r
- if(ppg_src == NULL)\r
+ if(data != NULL && ppg_src == NULL)\r
{\r
memcpy(ppg_data, data, 3);\r
return;\r
}\r
- \r
- // switch(mode)\r
- // {\r
- // case APP_FACTORY_TEST_HR_START:\r
- // memcpy((void *)&ppg_data[3], ppg_src, 4);\r
- // factory_test_send_data(ppg_data, 7);\r
- // break;\r
- // case APP_FACTORY_TEST_SPO2_START:\r
- // memcpy((void *)&ppg_data[3], ppg_src, 4);\r
- // factory_test_send_data(ppg_data, 7);\r
- // break;\r
- // case APP_FACTORY_TEST_LEAKING_START:\r
- // memcpy((void *)&ppg_data[3], ppg_src, 12);\r
- // factory_test_send_data(ppg_data, 15);\r
- // break;\r
- // case APP_FACTORY_TEST_GRAY_CARD:\r
- // memcpy((void *)&ppg_data[3], ppg_src, 12);\r
- // factory_test_send_data(ppg_data, 15);\r
- // break;\r
- // default:\r
- // break;\r
- // }\r
+// switch(mode)\r
+// {\r
+// case APP_FACTORY_TEST_HR_START:\r
+// ppg_data[3] = *(ppg_src + 3);\r
+// ppg_data[4] = *(ppg_src + 2);\r
+// ppg_data[5] = *(ppg_src + 1);\r
+// ppg_data[6] = *(ppg_src + 0);\r
+ \r
+// ppg_data[7] = *(ppg_src + 7);\r
+// ppg_data[8] = *(ppg_src + 6);\r
+// ppg_data[9] = *(ppg_src + 5);\r
+// ppg_data[10] = *(ppg_src + 4);\r
+\r
+// ppg_data[11] = *(ppg_src + 11);\r
+// ppg_data[12] = *(ppg_src + 10);\r
+// ppg_data[13] = *(ppg_src + 9);\r
+// ppg_data[14] = *(ppg_src + 8);\r
+ \r
+// factory_test_send_data(ppg_data, 15);\r
+// break;\r
+// case APP_FACTORY_TEST_SPO2_START:\r
+// ppg_data[3] = *(ppg_src + 3);\r
+// ppg_data[4] = *(ppg_src + 2);\r
+// ppg_data[5] = *(ppg_src + 1);\r
+// ppg_data[6] = *(ppg_src + 0);\r
+ \r
+// ppg_data[7] = *(ppg_src + 7);\r
+// ppg_data[8] = *(ppg_src + 6);\r
+// ppg_data[9] = *(ppg_src + 5);\r
+// ppg_data[10] = *(ppg_src + 4);\r
+\r
+// ppg_data[11] = *(ppg_src + 11);\r
+// ppg_data[12] = *(ppg_src + 10);\r
+// ppg_data[13] = *(ppg_src + 9);\r
+// ppg_data[14] = *(ppg_src + 8); \r
+\r
+// factory_test_send_data(ppg_data, 15);\r
+// break;\r
+// case APP_FACTORY_TEST_LEAKING_START:\r
+// // memcpy((void *)&ppg_data[3], ppg_src, 12);\r
+\r
+// ppg_data[3] = *(ppg_src + 3);\r
+// ppg_data[4] = *(ppg_src + 2);\r
+// ppg_data[5] = *(ppg_src + 1);\r
+// ppg_data[6] = *(ppg_src + 0);\r
+ \r
+// ppg_data[7] = *(ppg_src + 7);\r
+// ppg_data[8] = *(ppg_src + 6);\r
+// ppg_data[9] = *(ppg_src + 5);\r
+// ppg_data[10] = *(ppg_src + 4);\r
+\r
+// ppg_data[11] = *(ppg_src + 11);\r
+// ppg_data[12] = *(ppg_src + 10);\r
+// ppg_data[13] = *(ppg_src + 9);\r
+// ppg_data[14] = *(ppg_src + 8);\r
+\r
+\r
+// gui_send_message_by_data(MSG_FACTORY_TEST_UPDATE_HR, ppg_src, 12);\r
+// if(factory_test_aging) break;\r
+// factory_test_send_data(ppg_data, 15);\r
+// break;\r
+// case APP_FACTORY_TEST_GRAY_CARD:\r
+// {\r
+// // memcpy((void *)&ppg_data[3], ppg_src, 12);\r
+// ppg_data[3] = *(ppg_src + 3);\r
+// ppg_data[4] = *(ppg_src + 2);\r
+// ppg_data[5] = *(ppg_src + 1);\r
+// ppg_data[6] = *(ppg_src + 0);\r
+ \r
+// ppg_data[7] = *(ppg_src + 7);\r
+// ppg_data[8] = *(ppg_src + 6);\r
+// ppg_data[9] = *(ppg_src + 5);\r
+// ppg_data[10] = *(ppg_src + 4);\r
+\r
+// ppg_data[11] = *(ppg_src + 11);\r
+// ppg_data[12] = *(ppg_src + 10);\r
+// ppg_data[13] = *(ppg_src + 9);\r
+// ppg_data[14] = *(ppg_src + 8);\r
+ \r
+// gui_send_message_by_data(MSG_FACTORY_TEST_UPDATE_HR, ppg_src, 12);\r
+// if(factory_test_aging) break;\r
+// factory_test_send_data(ppg_data, 15);\r
+// } \r
+// break;\r
+// default:\r
+// break;\r
+// }\r
}\r
\r
+\r
+typedef struct { \r
+ int32_t gr_data_final;\r
+ int32_t red_data_final;\r
+ int32_t ir_data_final;\r
+} ft_test_result_t;\r
+\r
+\r
void heart_rate_meas_timeout_handler(void * p_context)\r
{\r
+ TYHX_LOG(" heart_rate_meas_timeout_handler mode: %d \n", work_mode_flag);\r
+ \r
switch(work_mode_flag)\r
{\r
case HRS_MODE:\r
break;\r
\r
case WEAR_MODE:\r
+// PRINT("@@@@@@@@@ WEAR_MODE $$$$$$$$$\r\n");\r
#ifdef CHECK_TOUCH_LIB\r
hx3695_wear_ppg_Int_handle();\r
#endif\r
#endif\r
\r
case FT_LEAK_LIGHT_MODE:\r
+ {\r
hx3695_factroy_test(LEAK_LIGHT_TEST);\r
break;\r
+ }\r
+ break;\r
\r
case FT_GRAY_CARD_MODE:\r
{\r
/*TYHX 心率模式下 读取PPG， 默认320ms*/\r
hrs_sensor_data_t hrs_s_dat;\r
//hx3695_results_t alg_results_pre;\r
-/***\r
- * typedef struct {\r
- hrs_alg_msg_code_t hrs_alg_status;\r
- living_msg_code_t living_status;\r
- uint32_t data_cnt;\r
- uint8_t hr_result;\r
- uint16_t cal_result;\r
- uint8_t hr_result_qual;\r
- uint32_t hr_result_std;\r
-} hrs_results_t;\r
-*/\r
+\r
void hx3695_hrs_ppg_Int_handle(void)\r
{\r
uint8_t ii=0;\r
int16_t gsen_fifo_y_send[32]= {0};\r
int16_t gsen_fifo_z_send[32]= {0};\r
\r
- HRS_CAL_SET_T cal;\r
- cal = get_hrs_agc_status();\r
+ HRS_CAL_SET_T cal;\r
+ cal = get_hrs_agc_status();\r
\r
#ifdef HR_VECTOR\r
for(ii=0; ii<8; ii++)\r
tyhx_hrs_alg_send_data(PPG_buf_vec,*count, gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send);\r
\r
#else\r
+ \r
if(hx3695_hrs_read(&hrs_s_dat) == 0)\r
{\r
- AGC_LOG("hx3695_hrs_read(&hrs_s_dat) == 0\r\n");\r
return;\r
}\r
\r
#ifndef GSEN_40MS_TIMMER\r
- readFifoByHrsModule();\r
+ //readFifoByHrsModule();\r
#endif\r
// DEBUG_PRINTF("\r\nsend jlink cnt=%d\r\n",*count); \r
- \r
- for(ii=0; ii<*count; ii++)\r
- {\r
- gsen_fifo_x_send[ii] = gsen_fifo_x[32-*count+ii];\r
- gsen_fifo_y_send[ii] = gsen_fifo_y[32-*count+ii];\r
- gsen_fifo_z_send[ii] = gsen_fifo_z[32-*count+ii];\r
-\r
-// DEBUG_PRINTF("gr,ir,gsen:%d/%d %d %d %d %d %d %d\r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x[ii],gsen_fifo_y[ii],gsen_fifo_z[ii],ppg_s_data.green_cur);\r
- }\r
+/* gsensor 屏蔽 */\r
+// for(ii=0; ii<*count; ii++)\r
+// {\r
+// #if 0\r
+// gsen_fifo_x_send[ii] = gsen_fifo_x[32-*count+ii];\r
+// gsen_fifo_y_send[ii] = gsen_fifo_y[32-*count+ii];\r
+// gsen_fifo_z_send[ii] = gsen_fifo_z[32-*count+ii];\r
+\r
+// PRINT("hx3695 gr,ir,gsen:%d/%d %d %d %d %d %d %d\r\n" ,\r
+// 1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x[ii],gsen_fifo_y[ii],gsen_fifo_z[ii],cal.Group1_Cur);\r
+// #else\r
+// accel_data_struct_t accel_raw_data = {0};\r
+// queue_output(&accel_raw_data);\r
+// gsen_fifo_x_send[ii] = accel_raw_data.x;\r
+// gsen_fifo_y_send[ii] = accel_raw_data.y;\r
+// gsen_fifo_z_send[ii] = accel_raw_data.z;\r
+// // PRINT("hx3695 gr,ir,gsen:%d/%d %d %d %d %d %d %d\r\n" ,\r
+// // 1+ii,*count,PPG_buf[ii], ir_buf[0], gsen_fifo_x_send[ii], gsen_fifo_y_send[ii], gsen_fifo_z_send[ii], cal.Group1_Cur);\r
+// printf("FFF==> hr PPG_buf : %d, %d, PPG_buf: %d, ir_buf: %d \n", 1+ii, *count, PPG_buf[ii], ir_buf[0]);\r
+ \r
+// #endif\r
+// }\r
+// ft_ppg_green = hrs_s_dat.green_data[0];\r
+ // ft_test_result_t result = {0};\r
+ // result.gr_data_final = hrs_s_dat.green_data[0];\r
+ // result.ir_data_final = hrs_s_dat.ir_data[0];\r
+ // hx3695_factory_test_process(NULL, APP_FACTORY_TEST_HR_START, &result);\r
\r
hrs_wear_status = hx3695_hrs_get_wear_status();\r
- AGC_LOG("hrs_wear_status: %d !!\r\n", hrs_wear_status);\r
+ PRINT("hrs_wear_status: %d !!\r\n", hrs_wear_status);\r
+ \r
if(hrs_wear_status == MSG_HRS_WEAR)\r
{\r
- tyhx_hrs_alg_send_data(PPG_buf, *count, gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send, cal.Group1_Ledidac);\r
+ tyhx_hrs_alg_send_data(PPG_buf, *count, gsen_fifo_x_send, gsen_fifo_y_send, \r
+ gsen_fifo_z_send, cal.Group1_Ledidac);\r
}\r
#endif\r
\r
- alg_results = tyhx_hrs_alg_get_results();\r
- hrsresult.lastesthrs = alg_results.hr_result;\r
- hrsresult.hr_living = alg_results.living_status;\r
- hrsresult.hr_living_qu = alg_results.hr_result_qual;\r
- hrsresult.hr_living_std = alg_results.hr_result_std;\r
+\r
+/*屏蔽*/\r
+// for(ii=0; ii<*count; ii++)\r
+// {\r
+// #if 0\r
+// gsen_fifo_x_send[ii] = gsen_fifo_x[32-*count+ii];\r
+// gsen_fifo_y_send[ii] = gsen_fifo_y[32-*count+ii];\r
+// gsen_fifo_z_send[ii] = gsen_fifo_z[32-*count+ii];\r
+ \r
+// PRINT("hx3695 gr,ir,gsen:%d/%d %d %d %d %d %d %d\r\n" ,\r
+// 1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x[ii],gsen_fifo_y[ii],gsen_fifo_z[ii],cal.Group1_Cur);\r
+// #else\r
+// // accel_data_struct_t accel_raw_data = {0};\r
+// // queue_output(&accel_raw_data);\r
+// // gsen_fifo_x_send[ii] = accel_raw_data.x;\r
+// // gsen_fifo_y_send[ii] = accel_raw_data.y;\r
+// // gsen_fifo_z_send[ii] = accel_raw_data.z;\r
+// // PRINT("hx3695 gr,ir,gsen:%d/%d %d %d %d %d %d %d hr==%d\r\n" ,\r
+// // 1+ii,*count,PPG_buf[ii], ir_buf[0], gsen_fifo_x_send[ii], gsen_fifo_y_send[ii], gsen_fifo_z_send[ii], cal.Group1_Cur,alg_results.hr_result);\r
+// #endif\r
+// }\r
+ \r
+ uint8_t curr_wear = 1;\r
+ //uint8_t last_wear = cwm_get_wear_status();\r
+\r
+ alg_results = tyhx_hrs_alg_get_results();\r
+ hrsresult.lastesthrs = alg_results.hr_result;\r
+ hrsresult.hr_living = alg_results.living_status;\r
+ hrsresult.hr_living_qu = alg_results.hr_result_qual;\r
+ hrsresult.hr_living_std = alg_results.hr_result_std;\r
\r
- AGC_LOG("hx3695 data_cnt: %d, hr_living: %d, hr_living_qu: %d, hr_living_std: %d, hr_result:%d \r\n",\r
- alg_results.data_cnt, hrsresult.hr_living, hrsresult.hr_living_qu, hrsresult.hr_living_std, hrsresult.lastesthrs);\r
+ PRINT("hx3695 data_cnt: %d, hr_living: %d, hr_living_qu: %d, hr_living_std: %d, hr_result:%d \r\n",\r
+ alg_results.data_cnt, hrsresult.hr_living, hrsresult.hr_living_qu, hrsresult.hr_living_std, hrsresult.lastesthrs);\r
if(hrs_wear_status == MSG_HRS_WEAR && hrsresult.hr_living == MSG_LIVING_TRUE)\r
{\r
// app_hr_reset_stop_timer();\r
if(alg_results.hr_result)\r
{\r
\r
- // app_hr_cal_hr_values(alg_results.hr_result);\r
- // AGC_LOG("app_hr_cal_hr_values tick:%d hr:%d", xTaskGetTickCount(), alg_results.hr_result);\r
- AGC_LOG("app_hr_cal_hr_values hr:%d", alg_results.hr_result);\r
+ //app_hr_cal_hr_values(alg_results.hr_result);\r
+ //PRINT("app_hr_cal_hr_values tick:%d hr:%d", xTaskGetTickCount(), alg_results.hr_result);\r
+ //cwm_hr_input(alg_results.hr_result);\r
//hr_sensor_notify_factory_test();\r
}\r
hr_no_living_dur = 0;\r
+ curr_wear = 1;\r
}\r
else if(hrs_wear_status == MSG_HRS_WEAR && hrsresult.hr_living != MSG_LIVING_TRUE)\r
{\r
- // if (++hr_no_living_dur > 12 * 1000 / tyhx_long_timer_tick)\r
+ if (++hr_no_living_dur > 12 * 1000 / tyhx_long_timer_tick)\r
{\r
- // hr_stop_detect();\r
- // AGC_LOG("tyhx_hrs_module_start(WEAR_MODE) wear:%d liv:%d", hrs_wear_status, hrsresult.hr_living);\r
- // hr_no_living_dur = 0;\r
+ //hr_stop_detect();\r
+ PRINT("MSG_HRS_WEAR:%d liv:%d", hrs_wear_status, hrsresult.hr_living);\r
+ hr_no_living_dur = 0;\r
+ curr_wear = 0;\r
}\r
}\r
else if(hrs_wear_status == MSG_HRS_NO_WEAR || hrsresult.hr_living == MSG_LIVING_FAIL)\r
{\r
- // hr_stop_detect();\r
- AGC_LOG("tyhx_hrs_module_start(WEAR_MODE) wear:%d liv:%d", hrs_wear_status, hrsresult.hr_living);\r
+ //hr_stop_detect();\r
+ PRINT("MSG_HRS_NO_WEAR:%d liv:%d", hrs_wear_status, hrsresult.hr_living);\r
hr_no_living_dur = 0;\r
+ curr_wear = 0;\r
+ }\r
+ \r
+ //cwm_off_body_detect(curr_wear);\r
+\r
+ #if defined(GSENSOR_LOG_NOTIFY) && GSENSOR_LOG_NOTIFY == 1 || defined(HRS_BLE_APP)\r
+ \r
+ if (last_wear!=curr_wear)\r
+ {\r
+ gui_send_message_by_data(MSG_HR_WEAR_STATUS_UPDATE, &curr_wear, 1);\r
}\r
+ #endif\r
+\r
#ifdef BP_CUSTDOWN_ALG_LIB\r
bp_results_t bp_alg_results;\r
bp_alg_results = tyhx_alg_get_bp_results();\r
#endif\r
- \r
+\r
////////////////////////////////////////BLE+DISPLAY/////////////////////////////////\r
\r
\r
rawdata.gsensor_z = gsen_fifo_z_send[ii];\r
rawdata.red_cur = cal.Group1_Cur;\r
rawdata.ir_cur = cal.Group1_Ledidac;\r
- \r
+// PRINT("@@@@@@@@@ HRS_BLE_APP gsen:%d %d %d\r\n", rawdata.gsensor_x, rawdata.gsensor_y, rawdata.gsensor_z);\r
ble_rawdata_vector_push(rawdata);\r
}\r
}\r
}\r
\r
#ifndef GSEN_40MS_TIMMER\r
- readFifoByHrsModule();\r
+// readFifoByHrsModule();\r
#endif\r
DEBUG_PRINTF("\r\nsend jlink cnt=%d\r\n",*count); \r
\r
//#ifdef SPO2_ALG_LIB\r
spo2_sensor_data_t spo2_s_dat;\r
\r
-/****\r
- * \r
-typedef struct {\r
- spo2_alg_msg_code_t spo2_alg_status;\r
- spo2_living_code_t spo2_living_status;\r
- uint32_t data_cnt;\r
- uint8_t spo2_result;\r
- uint8_t hr_result;\r
- uint8_t block_cnt;\r
- uint8_t ir_quality;\r
- uint16_t reliable_score_result;\r
-\r
- uint8_t screen_up;\r
- uint8_t motion;\r
- uint8_t poor_signal;\r
- \r
- uint8_t signal_snr;\r
- uint32_t signal_std;\r
- \r
-} spo2_results_t;\r
-\r
-*/\r
/*TYHX 血氧模式下 读取PPG， 默认320ms*/\r
void hx3695_spo2_ppg_Int_handle(void)\r
{\r
\r
\r
#ifndef GSEN_40MS_TIMMER\r
- readFifoByHrsModule();\r
+// readFifoByHrsModule();\r
#endif\r
DEBUG_PRINTF("\r\n send1 jlink cnt=%d\r\n",*count); \r
+ \r
+ /*屏蔽*/\r
+// for(ii=0; ii<*count; ii++)\r
+// {\r
+// gsen_fifo_x_send[ii] = gsen_fifo_x[32-*count+ii];\r
+// gsen_fifo_y_send[ii] = gsen_fifo_y[32-*count+ii];\r
+// gsen_fifo_z_send[ii] = gsen_fifo_z[32-*count+ii];\r
+// // PRINT("hx3695 data: %d/%d %d %d %d %d %d %d\r\n" ,\r
+// // 1+ii,*count,red_buf[ii],ir_buf[ii],green_buf[ii],gsen_fifo_x[ii],gsen_fifo_y[ii],gsen_fifo_z[ii]);\r
+// // printf("FFF==>spo2 red_buf : %d, %d, %d, %d \n", 1+ii, *count, red_buf[ii], ir_buf[0]);\r
\r
- for(ii=0; ii<*count; ii++)\r
- {\r
- gsen_fifo_x_send[ii] = gsen_fifo_x[32-*count+ii];\r
- gsen_fifo_y_send[ii] = gsen_fifo_y[32-*count+ii];\r
- gsen_fifo_z_send[ii] = gsen_fifo_z[32-*count+ii];\r
- //DEBUG_PRINTF("%d/%d %d %d %d %d %d %d\r\n" ,1+ii,*count,red_buf[ii],ir_buf[ii],green_buf[ii],gsen_fifo_x[ii],gsen_fifo_y[ii],gsen_fifo_z[ii]);\r
- // hx3695_factory_test_process(NULL, APP_FACTORY_TEST_SPO2_START, (uint8_t *)&red_buf[ii]);\r
\r
- }\r
- AGC_LOG("hx3695 current value: %d %d %d %d %d %d\r\n", cal.R_LED, cal.IR_LED1, cal.G_LED, cal.R_LEDDAC, cal.IR_LEDDAC1, cal.G_LEDDAC);\r
+// }\r
+\r
+// ft_ppg_iir = spo2_s_dat.red_data[0];\r
+// hx3695_factory_test_process(NULL, APP_FACTORY_TEST_SPO2_START, &ft_ppg_iir);\r
+\r
+ ft_test_result_t result = {0};\r
+ result.gr_data_final = spo2_s_dat.green_data[0];\r
+ result.red_data_final = spo2_s_dat.red_data[0];\r
+ result.ir_data_final = spo2_s_dat.ir_data1[0];\r
+ //hx3695_factory_test_process(NULL, APP_FACTORY_TEST_SPO2_START, &result);\r
+\r
+ \r
+ PRINT("hx3695 current value: %d %d %d %d %d %d\r\n", cal.R_LED, cal.IR_LED1, cal.G_LED, cal.R_LEDDAC, cal.IR_LEDDAC1, cal.G_LEDDAC);\r
spo2_wear_status = hx3695_spo2_get_wear_status();\r
+ PRINT("spo2_wear_status : %d\r\n",spo2_wear_status);\r
if(spo2_wear_status == MSG_SPO2_WEAR)\r
{\r
- tyhx_spo2_alg_send_data(red_buf, ir_buf, green_buf, cal.R_LEDDAC, cal.IR_LEDDAC1, cal.G_LEDDAC, gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send, *count);\r
+ tyhx_spo2_alg_send_data(red_buf, ir_buf, green_buf, cal.R_LEDDAC, cal.IR_LEDDAC1, cal.G_LEDDAC, \r
+ gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send, *count);\r
}\r
#endif\r
\r
spo2_alg_results = tyhx_spo2_alg_get_results();\r
+//------------------------adjust-------------------\r
+// DEBUG_PRINTF("block_cnt: %d, data_cnt:%d, hr_result:%d,ir_quality:%d,motion:%d,poor_signal:%d,reliable_score_result:%d,screen_up:%d,spo2_result:%d\r\n",spo2_alg_results.block_cnt,spo2_alg_results.data_cnt,spo2_alg_results.hr_result,spo2_alg_results.ir_quality,spo2_alg_results.motion,spo2_alg_results.poor_signal,spo2_alg_results.reliable_score_result,spo2_alg_results.screen_up,spo2_alg_results.spo2_result);\r
+\r
+ hrsresult.lastestspo2 = spo2_alg_results.spo2_result;\r
+ hrsresult.lastesthrs = spo2_alg_results.hr_result;\r
+ uint8_t curr_wear = 1;\r
+ //uint8_t last_wear = cwm_get_wear_status();\r
+ if(spo2_wear_status == MSG_SPO2_WEAR && spo2_alg_results.spo2_living_status == MSG_SPO2_LIVING_TRUE)\r
+ {\r
+ //store_latest_spo2(hrsresult.lastestspo2);\r
+ //app_hr_cal_hr_values(hrsresult.lastesthrs);\r
+ //cwm_hr_input(hrsresult.lastesthrs);\r
+ spo2_no_living_dur = 0;\r
+ curr_wear = 1;\r
+ }\r
+ else if(spo2_wear_status == MSG_SPO2_WEAR && spo2_alg_results.spo2_living_status != MSG_SPO2_LIVING_TRUE)\r
+ {\r
+ if (++spo2_no_living_dur > 12 * 1000 / tyhx_long_timer_tick)\r
+ {\r
+ //gui_send_msg_by_evt(MSG_SPO2_MEASURE_CANCEL);\r
+ PRINT("MSG_SPO2_WEAR:%d liv:%d", spo2_wear_status, spo2_alg_results.spo2_living_status);\r
+ spo2_no_living_dur = 0;\r
+ curr_wear = 0;\r
+ }\r
+ }\r
+ else if(spo2_wear_status == MSG_SPO2_NO_WEAR || spo2_alg_results.spo2_living_status == MSG_SPO2_LIVING_FAIL)\r
+ {\r
+ //gui_send_msg_by_evt(MSG_SPO2_MEASURE_CANCEL);\r
+ PRINT("MSG_SPO2_NO_WEAR:%d liv:%d", spo2_wear_status, spo2_alg_results.spo2_living_status);\r
+ spo2_no_living_dur = 0;\r
+ curr_wear = 0;\r
+ }\r
+ //cwm_off_body_detect(curr_wear);\r
+ #if defined(GSENSOR_LOG_NOTIFY) && GSENSOR_LOG_NOTIFY == 1 || defined(HRS_BLE_APP)\r
+ if (last_wear!=curr_wear)\r
+ {\r
+ gui_send_message_by_data(MSG_HR_WEAR_STATUS_UPDATE, &curr_wear, 1);\r
+ }\r
+ #endif\r
+/////////////////////////////////////////BLE+DISPLAY//////////////////////////////////////////\r
+ spo2_alg_results = tyhx_spo2_alg_get_results();\r
//------------------------adjust-------------------\r
DEBUG_PRINTF("block_cnt: %d, data_cnt:%d, hr_result:%d,ir_quality:%d,motion:%d,poor_signal:%d,reliable_score_result:%d,screen_up:%d,spo2_result:%d\r\n",spo2_alg_results.block_cnt,spo2_alg_results.data_cnt,spo2_alg_results.hr_result,spo2_alg_results.ir_quality,spo2_alg_results.motion,spo2_alg_results.poor_signal,spo2_alg_results.reliable_score_result,spo2_alg_results.screen_up,spo2_alg_results.spo2_result);\r
\r
}\r
\r
\r
-/////////////////////////////////////////BLE+DISPLAY//////////////////////////////////////////\r
\r
\r
#ifdef HRS_BLE_APP\r
rawdata.ir_raw_data = ir_buf[ii];\r
#endif\r
rawdata.vector_flag = SPO2_VECTOR_FLAG;\r
- rawdata.data_cnt = cal.G_LEDDAC;\r
+ rawdata.data_cnt = cal.G_LED;\r
rawdata.hr_result = spo2_alg_results.spo2_result;\r
rawdata.gsensor_x = (int16_t)(green_buf[ii]>>5);\r
rawdata.gsensor_y = cal.R_LEDDAC;\r
}\r
\r
#ifndef GSEN_40MS_TIMMER\r
- readFifoByHrsModule();\r
+//readFifoByHrsModule();\r
#endif\r
DEBUG_PRINTF("\r\nsend jlink cnt=%d\r\n",*count); \r
\r
\r
- for(ii=0; ii<*count; ii++)\r
- {\r
- gsen_fifo_x_send[ii] = gsen_fifo_x[32-*count+ii];\r
- gsen_fifo_y_send[ii] = gsen_fifo_y[32-*count+ii];\r
- gsen_fifo_z_send[ii] = gsen_fifo_z[32-*count+ii];\r
+ // for(ii=0; ii<*count; ii++)\r
+ // {\r
+ // gsen_fifo_x_send[ii] = gsen_fifo_x[32-*count+ii];\r
+ // gsen_fifo_y_send[ii] = gsen_fifo_y[32-*count+ii];\r
+ // gsen_fifo_z_send[ii] = gsen_fifo_z[32-*count+ii];\r
\r
- }\r
+ // }\r
spo2_wear_status = hx3695_spo2_get_wear_status();\r
if(spo2_wear_status == MSG_SPO2_WEAR)\r
{\r
}\r
\r
#ifndef GSEN_40MS_TIMMER\r
- readFifoByHrsModule();\r
+// readFifoByHrsModule();\r
#endif\r
DEBUG_PRINTF("\r\nsend jlink cnt=%d\r\n",*count); \r
\r
#ifdef CHECK_TOUCH_LIB\r
void hx3695_wear_ppg_Int_handle(void)\r
{\r
+// PRINT("hx3695_wear_ppg_Int_handle wearstatus = %d\r\n", hrsresult.wearstatus);\r
+ \r
uint8_t *count = &(ppg_s_data.count);\r
int32_t *ir_buf = &(ppg_s_data.ir_data[0]);\r
hx3695_wear_msg_code_t hx3695_wear_status;\r
\r
hx3695_check_touch_read(&ppg_s_data);\r
+ \r
hx3695_wear_status = hx3695_check_touch_send_data(ir_buf,*count);\r
hrsresult.wearstatus = hx3695_wear_status;\r
+\r
extern uint8_t notouch_cnt;\r
extern uint8_t touch_cnt;\r
+ \r
+// PRINT("===> touch_cnt: %d, notouch_cnt: %d, wear status: %d, \r\n", touch_cnt, notouch_cnt, hx3695_wear_status);\r
\r
- if (hrsresult.wearstatus)\r
- {\r
- cwm_gsensor_enable();\r
- }\r
- else\r
- {\r
- cwm_gsensor_disable();\r
- }\r
-// AGC_LOG("===> touch_cnt: %d, notouch_cnt: %d, wear status: %d, \r\n", touch_cnt, notouch_cnt, hx3695_wear_status);\r
-\r
-// AGC_LOG("hx3695_wear_ppg_Int_handle wearstatus = %d\r\n", hrsresult.wearstatus);\r
+// PRINT("hx3695_wear_ppg_Int_handle wearstatus = %d\r\n", hrsresult.wearstatus);\r
\r
// for(int i=0;i<*count;i++)\r
// {\r
projects / mirrors / FD230.git / commitdiff