新硬件更新配置

diff --git a/2.code/aicos/projects/banyan/ap/gx306l_h3_d_sms_aichat/config/pin_cfg.h b/2.code/aicos/projects/banyan/ap/gx306l_h3_d_sms_aichat/config/pin_cfg.h
index 63d3826..f1e03c6 100644 (file)
--- a/2.code/aicos/projects/banyan/ap/gx306l_h3_d_sms_aichat/config/pin_cfg.h
+++ b/2.code/aicos/projects/banyan/ap/gx306l_h3_d_sms_aichat/config/pin_cfg.h
@@ -9,7 +9,7 @@
 /* @@Platform: GX306 */
 /* @@Author:  */
 /* @@Version:  */
-/* @@Time: 2025/5/13 17:00:19 */
+/* @@Time: 2025/7/22 17:13:54 */
 
 #ifndef __PIN_CFG_H__
 #define __PIN_CFG_H__
@@ -51,8 +51,8 @@ const u32 pin_cfg0[][2] = {
 {REG_IOMUX_RFCTRL7,                   BIT_FUNC_SEL(1)},//RFFE_SDA
 {REG_PG1_PAD_CTRL_RFCTRL7,            BIT_PAD_DRV(1)|BIT_PAD_WPD|BIT_PAD_SLP_CP|BIT_PAD_SLP_WPD|BIT_PAD_SLP_Z},
 /* Group2 */
-{REG_IOMUX_IIS_MCLK,                  BIT_FUNC_SEL(3)},//GPIO20_MOT_EN1
-{REG_PG2_PAD_CTRL_IIS_MCLK,           BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_PX|BIT_PAD_SLP_OE},
+{REG_IOMUX_IIS_MCLK,                  BIT_FUNC_SEL(0)},//IIS_MCLK
+{REG_PG2_PAD_CTRL_IIS_MCLK,           BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPD|BIT_PAD_SLP_Z},
 {REG_IOMUX_IIS_CLK,                   BIT_FUNC_SEL(0)},//IIS_CLK
 {REG_PG2_PAD_CTRL_IIS_CLK,            BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPD|BIT_PAD_SLP_Z},
 {REG_IOMUX_IIS_LRCLK,                 BIT_FUNC_SEL(0)},//IIS_LRCLK
@@ -66,18 +66,18 @@ const u32 pin_cfg0[][2] = {
 {REG_IOMUX_UART1_TXD,                 BIT_FUNC_SEL(0)},//DEBUG_TXD
 {REG_PG2_PAD_CTRL_UART1_TXD,          BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPU|BIT_PAD_SLP_Z},
 /* Group3 */
-{REG_IOMUX_SSP_CS1,                   BIT_FUNC_SEL(3)},//2210_WAKE_6824
-{REG_PG3_PAD_CTRL_SSP_CS1,            BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_PX|BIT_PAD_SLP_OE},
+{REG_IOMUX_SSP_CS1,                   BIT_FUNC_SEL(3)},//MOT_EN_REV_GPO14
+{REG_PG3_PAD_CTRL_SSP_CS1,            BIT_PAD_DRV(1)|BIT_PAD_WPD|BIT_PAD_SLP_TOP|BIT_PAD_SLP_PX|BIT_PAD_SLP_OE},
 {REG_IOMUX_SSP_CLK,                   BIT_FUNC_SEL(3)},//NC
 {REG_PG3_PAD_CTRL_SSP_CLK,            BIT_PAD_DRV(2)|BIT_PAD_WPD|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPD|BIT_PAD_SLP_Z},
 {REG_IOMUX_SSP_CS0,                   BIT_FUNC_SEL(3)},//NC
 {REG_PG3_PAD_CTRL_SSP_CS0,            BIT_PAD_DRV(2)|BIT_PAD_WPD|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPD|BIT_PAD_SLP_Z},
-{REG_IOMUX_SSP_MISO,                  BIT_FUNC_SEL(3)},//NC
-{REG_PG3_PAD_CTRL_SSP_MISO,           BIT_PAD_DRV(1)|BIT_PAD_WPD|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPD|BIT_PAD_SLP_Z},
-{REG_IOMUX_SSP_MOSI,                  BIT_FUNC_SEL(3)},//NC
-{REG_PG3_PAD_CTRL_SSP_MOSI,           BIT_PAD_DRV(1)|BIT_PAD_WPD|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPD|BIT_PAD_SLP_Z},
-{REG_IOMUX_AUX_CLK0,                  BIT_FUNC_SEL(5)},//IIS_MCLK
-{REG_PG3_PAD_CTRL_AUX_CLK0,           BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPD|BIT_PAD_SLP_Z},
+{REG_IOMUX_SSP_MISO,                  BIT_FUNC_SEL(3)},//LED0_GPIO17
+{REG_PG3_PAD_CTRL_SSP_MISO,           BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPD|BIT_PAD_SLP_Z},
+{REG_IOMUX_SSP_MOSI,                  BIT_FUNC_SEL(3)},//LED1_GPIO18
+{REG_PG3_PAD_CTRL_SSP_MOSI,           BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPD|BIT_PAD_SLP_Z},
+{REG_IOMUX_AUX_CLK0,                  BIT_FUNC_SEL(3)},//GPIO19_MOT_EN
+{REG_PG3_PAD_CTRL_AUX_CLK0,           BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_PX|BIT_PAD_SLP_OE},
 /* Group4 */
 {REG_PG4_PAD_CTRL_PSRAM_RWDS,         BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_NONE|BIT_PAD_SLP_WPD|BIT_PAD_SLP_Z},
 {REG_PG4_PAD_CTRL_PSRAM_DQ7,          BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_NONE|BIT_PAD_SLP_WPD|BIT_PAD_SLP_Z},
@@ -96,12 +96,12 @@ const u32 pin_cfg0[][2] = {
 /* Group5 */
 {REG_IOMUX_GPO0,                      BIT_FUNC_SEL(4)},//TP_EN_GPO0
 {REG_PG5_PAD_CTRL_GPO0,               BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_PX|BIT_PAD_SLP_OE},
-{REG_IOMUX_GPO1,                      BIT_FUNC_SEL(4)},//MOT_EN_REV_GPO1
+{REG_IOMUX_GPO1,                      BIT_FUNC_SEL(4)},//2210_WAKE_6824
 {REG_PG5_PAD_CTRL_GPO1,               BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_PX|BIT_PAD_SLP_OE},
-{REG_IOMUX_EIU_INT4,                  BIT_FUNC_SEL(0)},//KEY3_INT4
-{REG_PG5_PAD_CTRL_EIU_INT4,           BIT_PAD_DRV(1)|BIT_PAD_WPU|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPU|BIT_PAD_SLP_IE},
+{REG_IOMUX_EIU_INT4,                  BIT_FUNC_SEL(4)},//MOT_EN_FWD_GPO2
+{REG_PG5_PAD_CTRL_EIU_INT4,           BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_PX|BIT_PAD_SLP_OE},
 {REG_IOMUX_EIU_INT5,                  BIT_FUNC_SEL(4)},//GPO3_INT5_TPQ1
-{REG_PG5_PAD_CTRL_EIU_INT5,           BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_PX|BIT_PAD_SLP_OE},
+{REG_PG5_PAD_CTRL_EIU_INT5,           BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_PX|BIT_PAD_SLP_IE},
 {REG_IOMUX_EIU_INT6,                  BIT_FUNC_SEL(5)},//IIC3_SDA
 {REG_PG5_PAD_CTRL_EIU_INT6,           BIT_PAD_DRV(1)|BIT_PAD_SSPU|BIT_PAD_SLP_MCU|BIT_PAD_SLP_SPU|BIT_PAD_SLP_Z},
 {REG_IOMUX_EIU_INT7,                  BIT_FUNC_SEL(5)},//IIC3_SCL
@@ -124,14 +124,14 @@ const u32 pin_cfg0[][2] = {
 {REG_PG6_PAD_CTRL_PMIC_INT,           BIT_PAD_DRV(1)|BIT_PAD_WPD|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPD|BIT_PAD_SLP_IE},
 {REG_IOMUX_CHIP_SLEEP,                BIT_FUNC_SEL(0)},//CHIP_SLEEP
 {REG_PG6_PAD_CTRL_CHIP_SLEEP,         BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_PX|BIT_PAD_SLP_OE},
-{REG_IOMUX_UART0_TXD,                 BIT_FUNC_SEL(4)},//MOT_EN_FWD_GPO
-{REG_PG6_PAD_CTRL_UART0_TXD,          BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_PX|BIT_PAD_SLP_OE},
+{REG_IOMUX_UART0_TXD,                 BIT_FUNC_SEL(1)},//KEY3_INT4
+{REG_PG6_PAD_CTRL_UART0_TXD,          BIT_PAD_DRV(1)|BIT_PAD_WPU|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPU|BIT_PAD_SLP_IE},
 {REG_IOMUX_UART0_RXD,                 BIT_FUNC_SEL(4)},//STATUS_GPO9
 {REG_PG6_PAD_CTRL_UART0_RXD,          BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_PX|BIT_PAD_SLP_OE},
-{REG_IOMUX_UART0_CTS,                 BIT_FUNC_SEL(1)},//G_EINT_INT6_GPO1
+{REG_IOMUX_UART0_CTS,                 BIT_FUNC_SEL(1)},//G_EINT_INT6_GPO10
 {REG_PG6_PAD_CTRL_UART0_CTS,          BIT_PAD_DRV(1)|BIT_PAD_WPU|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPU|BIT_PAD_SLP_IE},
 {REG_IOMUX_UART0_RTS,                 BIT_FUNC_SEL(4)},//GPO11_INT7_TPQ2
-{REG_PG6_PAD_CTRL_UART0_RTS,          BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_PX|BIT_PAD_SLP_OE},
+{REG_PG6_PAD_CTRL_UART0_RTS,          BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_PX|BIT_PAD_SLP_IE},
 {REG_IOMUX_EIU_INT0,                  BIT_FUNC_SEL(0)},//U_BOOT_KEY_KEYIN
 {REG_PG6_PAD_CTRL_EIU_INT0,           BIT_PAD_DRV(1)|BIT_PAD_WPU|BIT_PAD_SLP_MCU|BIT_PAD_SLP_WPU|BIT_PAD_SLP_IE},
 {REG_IOMUX_EIU_INT3,                  BIT_FUNC_SEL(4)},//CODEC_VDD_EN_GPO13
@@ -176,15 +176,15 @@ const u32 pin_cfg0[][2] = {
 {REG_IOMUX_SIM_DAT,                   BIT_FUNC_SEL(0)},//SIM0_DAT
 {REG_PG9_PAD_CTRL_SIM_DAT,            BIT_PAD_DRV(1)|BIT_PAD_SSPU|BIT_PAD_SLP_CP|BIT_PAD_SLP_SPU|BIT_PAD_SLP_Z},
 /* Group10 */
-{REG_IOMUX_CAN_TXD,                   BIT_FUNC_SEL(6)},//LED1_GPIO30
+{REG_IOMUX_CAN_TXD,                   BIT_FUNC_SEL(6)},//NC
 {REG_PG10_PAD_CTRL_CAN_TXD,           BIT_PAD_DRV(1)|BIT_PAD_WPD|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPD|BIT_PAD_SLP_Z},
-{REG_IOMUX_CAN_RXD,                   BIT_FUNC_SEL(6)},//LED2_GPIO32
+{REG_IOMUX_CAN_RXD,                   BIT_FUNC_SEL(6)},//NC
 {REG_PG10_PAD_CTRL_CAN_RXD,           BIT_PAD_DRV(1)|BIT_PAD_WPD|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPD|BIT_PAD_SLP_Z},
-{REG_IOMUX_CAN_STBY,                  BIT_FUNC_SEL(6)},//LED0_GPIO25
+{REG_IOMUX_CAN_STBY,                  BIT_FUNC_SEL(6)},//NC
 {REG_PG10_PAD_CTRL_CAN_STBY,          BIT_PAD_DRV(1)|BIT_PAD_WPD|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPD|BIT_PAD_SLP_Z},
 /* Group11 */
-{REG_IOMUX_SPI_LCD_SDI,               BIT_FUNC_SEL(6)},//NC
-{REG_PG11_PAD_CTRL_SPI_LCD_SDI,       BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_WPD|BIT_PAD_SLP_Z},
+{REG_IOMUX_SPI_LCD_SDI,               BIT_FUNC_SEL(6)},//LED3_GPIO26
+{REG_PG11_PAD_CTRL_SPI_LCD_SDI,       BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_TOP|BIT_PAD_SLP_PX|BIT_PAD_SLP_OE},
 {REG_IOMUX_SPI_LCD_SDO,               BIT_FUNC_SEL(5)},//SPI_D0
 {REG_PG11_PAD_CTRL_SPI_LCD_SDO,       BIT_PAD_DRV(1)|BIT_PAD_PX|BIT_PAD_SLP_MCU|BIT_PAD_SLP_WPD|BIT_PAD_SLP_Z},
 {REG_IOMUX_SPI_LCD_DCX,               BIT_FUNC_SEL(5)},//SPI_D1