/* VAU Linked List Address NON Cache */
#define PSRAM_DISP_VAU_NODE_ADDR (PSRAM_GUI_MEM_POOL_ADDR + PSRAM_GUI_MEM_POOL_SIZE)
-#define PSRAM_DISP_VAU_NODE_LENGTH psram_align_size(0x80000, POOL_ADDR_ALIGNSIZE)
+#define PSRAM_DISP_VAU_NODE_LENGTH psram_align_size(0x80000+0x380000, POOL_ADDR_ALIGNSIZE)
/* reserve */
#define PSRAM_RESERVE_ADDR (PSRAM_DISP_VAU_NODE_ADDR + PSRAM_DISP_VAU_NODE_LENGTH)
-#define PSRAM_RESERVE_ADDR_LENGTH psram_align_size(0x380000, POOL_ADDR_ALIGNSIZE)
+#define PSRAM_RESERVE_ADDR_LENGTH psram_align_size(0x0, POOL_ADDR_ALIGNSIZE)
#endif // PSRAM_H
LOSCFG_BASE_CORE_TSK_MONITOR=y
LOSCFG_TASK_STACK_STATIC_ALLOCATION=y
LOSCFG_TASK_STACK_DYNAMIC_ALLOCATION=y
-LOSCFG_BASE_CORE_TSK_LIMIT=72
+LOSCFG_BASE_CORE_TSK_LIMIT=100
LOSCFG_BASE_CORE_TSK_MIN_STACK_SIZE=1024
LOSCFG_BASE_CORE_TSK_DEFAULT_STACK_SIZE=2048
LOSCFG_BASE_CORE_TSK_SWTMR_STACK_SIZE=3072