From 2a618bdcbaa7e6ae041cf3092c44dec9253887f0 Mon Sep 17 00:00:00 2001 From: luozheng <1732036298@qq.com> Date: Mon, 20 Apr 2026 11:09:05 +0800 Subject: [PATCH] =?utf8?q?drivers=E6=96=87=E4=BB=B6=E5=A4=B91201patch?= =?utf8?q?=E5=90=88=E5=B9=B6=E6=8F=90=E4=BA=A4?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit --- .../brandy_evb/linker/standard/acore.prelds | 26 ++- .../product/product_evb4_standard.h | 3 + .../brandy_evb/product/product_evb_standard.h | 3 + .../brandy/clocks/drivers/acore/clocks.c | 9 + .../clocks/drivers/acore/clocks_config_priv.c | 16 +- .../brandy/clocks/hal/hal_clocks_app_priv.c | 2 +- .../source/core/osal/liteos/audio_osal_addr.c | 4 +- .../drivers/driver/ipc/ipc_old/shared/ipc.c | 2 +- .../driver/ipc/ipc_old/shared/ipc_actions.h | 2 + .../driver/mmc/host/sdhci/brandy/mmc_sdhci.c | 163 ++++++++++++------ .../drivers/driver/mmc/include/soc_mmc.h | 4 +- .../nand_flash/nand/include/nandflash_inner.h | 2 +- code/sdk/drivers/drivers/driver/spi/spi.c | 54 +----- code/sdk/drivers/drivers/hal/spi/hal_spi.h | 13 +- .../drivers/hal/spi/v100/hal_spi_v100.c | 61 +++++-- 15 files changed, 215 insertions(+), 149 deletions(-) diff --git a/code/sdk/drivers/boards/brandy_evb/linker/standard/acore.prelds b/code/sdk/drivers/boards/brandy_evb/linker/standard/acore.prelds index 7078e96b4..b38c9f536 100644 --- a/code/sdk/drivers/boards/brandy_evb/linker/standard/acore.prelds +++ b/code/sdk/drivers/boards/brandy_evb/linker/standard/acore.prelds @@ -107,16 +107,16 @@ SECTIONS #ifdef SUPPORT_GYRO_SERVICE SORT(*libgyro*.a:*.o*) (.data .data* .sdata .sdata*) #endif -#ifdef BOARD_LEINIAO - SORT(*libthunderbird_toys*.a:*.o*) (.data .data* .sdata .sdata*) -#endif #ifdef CUSTOM_ZHIHUI SORT(*libaiMediaService*.a:*.o*) (.data .data* .sdata .sdata*) SORT(*libzhihui_websocket*.a:*.o*) (.data .data* .sdata .sdata*) SORT(*libcustom_utils*.a:*.o*) (.data .data* .sdata .sdata*) #endif SORT(*libace_adapt.a:*.o*) (.data .data* .sdata .sdata*) + SORT(*libace_ext.a:*.o*) (.data .data* .sdata .sdata*) + SORT(*libace_ble*.a:*.o*) (.data .data* .sdata .sdata*) SORT(*libace_http*.a:*.o*) (.data .data* .sdata .sdata*) + SORT(*libace_websocket*.a:*.o*) (.data .data* .sdata .sdata*) SORT(*libnetstack_http*.a:*.o*) (.data .data* .sdata .sdata*) SORT(*libwebsocket*.a:*.o*) (.data .data* .sdata .sdata*) SORT(*libjerryscript*.a:*.o*) (.data .data* .sdata .sdata*) @@ -158,16 +158,16 @@ SECTIONS #ifdef SUPPORT_GYRO_SERVICE SORT(*libgyro*.a:*.o*) (.bss .bss* .sbss .sbss* COMMON) #endif -#ifdef BOARD_LEINIAO - SORT(*libthunderbird_toys*.a:*.o*) (.bss .bss* .sbss .sbss* COMMON) -#endif #ifdef CUSTOM_ZHIHUI SORT(*libaiMediaService*.a:*.o*) (.bss .bss* .sbss .sbss* COMMON) SORT(*libzhihui_websocket*.a:*.o*) (.bss .bss* .sbss .sbss* COMMON) SORT(*libcustom_utils*.a:*.o*) (.bss .bss* .sbss .sbss* COMMON) #endif SORT(*libace_adapt.a:*.o*) (.bss .bss* .sbss .sbss* COMMON) + SORT(*libace_ext.a:*.o*) (.bss .bss* .sbss .sbss* COMMON) + SORT(*libace_ble*.a:*.o*) (.bss .bss* .sbss .sbss* COMMON) SORT(*libace_http*.a:*.o*) (.bss .bss* .sbss .sbss* COMMON) + SORT(*libace_websocket*.a:*.o*) (.bss .bss* .sbss .sbss* COMMON) SORT(*libnetstack_http*.a:*.o*) (.bss .bss* .sbss .sbss* COMMON) SORT(*libwebsocket*.a:*.o*) (.bss .bss* .sbss .sbss* COMMON) SORT(*libjerryscript*.a:*.o*) (.bss .bss* .sbss .sbss* COMMON) @@ -188,9 +188,6 @@ SECTIONS { __l2m_gpu_text_start = .; __l2m_gpu_text_load = LOADADDR(.l2m_gpu_text); - . = ALIGN(8); - *libdisplay_gfx.a:yuv_to_rgb.c.obj* (.text .text* .rodata .rodata* .srodata .srodata*) - . = ALIGN(8); __l2m_gpu_text_end = .; } > L2M_GPU_PROGRAM AT > FLASH_PROGRAM __l2m_gpu_text_size = __l2m_gpu_text_end - __l2m_gpu_text_start; @@ -198,9 +195,6 @@ SECTIONS .l2m_gpu_bss : { __l2m_gpu_bss_start = .; - . = ALIGN(8); - *libdisplay_gfx.a:yuv_to_rgb.c.obj* (.bss .bss* .sbss .sbss* COMMON) - . = ALIGN(8); __l2m_gpu_bss_end = .; } > L2M_GPU_PROGRAM __l2m_gpu_bss_size = __l2m_gpu_bss_end - __l2m_gpu_bss_start; @@ -209,9 +203,6 @@ SECTIONS { __l2m_gpu_data_start = .; __l2m_gpu_data_load = LOADADDR(.l2m_gpu_data); - . = ALIGN(8); - *libdisplay_gfx.a:yuv_to_rgb.c.obj* (.data .data* .sdata .sdata*) - . = ALIGN(8); __l2m_gpu_data_end = .; } > L2M_GPU_PROGRAM AT > FLASH_PROGRAM __l2m_gpu_data_size = __l2m_gpu_data_end - __l2m_gpu_data_start; @@ -328,6 +319,7 @@ SECTIONS *utils/pm*.a:*.o* (.text .text* .rodata .rodata* .srodata .srodata*) *middleware/chips/brandy/pm*.a:*.o* (.text .text* .rodata .rodata* .srodata .srodata*) KEEP(*(.text.lcd_get_status)); + KEEP(*(.text.uapi_is_lcd_connect)); /* In particular, memcpy_s and memset_s must be placed in itcm. */ SORT(*libsec.a:*.o*) (.text .text* .rodata .rodata* .srodata .srodata*) SORT(*libcsysdeps.a:*.o*) (.text .text* .rodata .rodata* .srodata .srodata*) @@ -357,6 +349,7 @@ SECTIONS SORT(*platform/testsuite/test_dhry*.a:*.o*) (.text .text* .rodata .rodata* .srodata .srodata*) #endif SORT(*systemview.a:*.o*) (.text .text* .rodata .rodata* .srodata .srodata*) + *libdisplay_gfx.a:yuv_to_rgb.c.obj* (.text .text* .rodata .rodata* .srodata .srodata*) . = ALIGN(8); __init_array_start = .; KEEP(*(.ctors .init_array*)) @@ -608,6 +601,7 @@ SECTIONS SORT(*test/platform/testsuite*.a:*.o*) (.data .data*) #endif SORT(*systemview.a:*.o*) (.data .data*) + *libdisplay_gfx.a:yuv_to_rgb.c.obj* (.data .data*) *(.data) *(.data*) *(.got) @@ -635,6 +629,7 @@ SECTIONS SORT(*test/common/testsuite*.a:*.o*) (.sdata .sdata*) SORT(*test/platform/testsuite*.a:*.o*) (.sdata .sdata*) #endif + *libdisplay_gfx.a:yuv_to_rgb.c.obj* (.sdata .sdata*) *(.sdata) *(.sdata*) . = ALIGN(0x4); @@ -682,6 +677,7 @@ SECTIONS SORT(*test/platform/testsuite*.a:*.o*) (.bss .bss* .sbss .sbss* COMMON) #endif SORT(*systemview.a:*.o*) (.bss .bss* .sbss .sbss* COMMON) + *libdisplay_gfx.a:yuv_to_rgb.c.obj* (.bss .bss* .sbss .sbss* COMMON) *(.bss) *(.bss*) *(.sbss) diff --git a/code/sdk/drivers/boards/brandy_evb/product/product_evb4_standard.h b/code/sdk/drivers/boards/brandy_evb/product/product_evb4_standard.h index 9c041e006..9e4a2d4ce 100644 --- a/code/sdk/drivers/boards/brandy_evb/product/product_evb4_standard.h +++ b/code/sdk/drivers/boards/brandy_evb/product/product_evb4_standard.h @@ -297,6 +297,9 @@ #define OPUS_ENC_BIT_RATE 16000 // opus编码码率 #define MP3_ENC_BIT_RATE 16000 // mp3编码码率 + +// volume +#define DEFAULTE_AI_VOL_DB_INTERGER 24 // 默认的AI的音量值整数部分，单位DB /** * @} */ diff --git a/code/sdk/drivers/boards/brandy_evb/product/product_evb_standard.h b/code/sdk/drivers/boards/brandy_evb/product/product_evb_standard.h index d45708c8e..0cd5e7a9c 100644 --- a/code/sdk/drivers/boards/brandy_evb/product/product_evb_standard.h +++ b/code/sdk/drivers/boards/brandy_evb/product/product_evb_standard.h @@ -229,6 +229,9 @@ #define OPUS_ENC_BIT_RATE 16000 // opus编码码率 #define MP3_ENC_BIT_RATE 16000 // mp3编码码率 + +// volume +#define DEFAULTE_AI_VOL_DB_INTERGER 24 // 默认的AI的音量值整数部分，单位DB /** * @} */ diff --git a/code/sdk/drivers/chips/brandy/clocks/drivers/acore/clocks.c b/code/sdk/drivers/chips/brandy/clocks/drivers/acore/clocks.c index f2d445f3b..1c2c7aec2 100644 --- a/code/sdk/drivers/chips/brandy/clocks/drivers/acore/clocks.c +++ b/code/sdk/drivers/chips/brandy/clocks/drivers/acore/clocks.c @@ -14,6 +14,8 @@ #include "hal_xip.h" #endif +void mmc_set_sd_bus_clk_div(uint32_t freq_div); + #if defined(BUILD_APPLICATION_STANDARD) || defined(TEST_SUITE) static system_clocks_config_t g_current_system_clock_config = CLOCKS_CONFIG_MAX; void clocks_system_init(void) @@ -37,6 +39,8 @@ void system_mcu_clocks_config(void) for (i = 0; i < length; i++) { hal_clocks_app_perips_config(mcu_perip_clks[i].perip, mcu_perip_clks[i].on); } + + mmc_set_sd_bus_clk_div(0x1); } #else @@ -85,6 +89,11 @@ uint32_t clocks_get_core_frequency(void) return clocks_get_ccrg_clk_freq(CLOCKS_CCRG_MODULE_MCU_CORE); } +uint32_t clocks_get_spi_frequency(void) +{ + return clocks_get_ccrg_clk_freq(CLOCKS_CCRG_MODULE_MCU_PERP_SPI); +} + uint32_t clocks_get_tcxo_clock(void) { return TCXO_1X_CLK; diff --git a/code/sdk/drivers/chips/brandy/clocks/drivers/acore/clocks_config_priv.c b/code/sdk/drivers/chips/brandy/clocks/drivers/acore/clocks_config_priv.c index 22e32bf99..4f14593e9 100644 --- a/code/sdk/drivers/chips/brandy/clocks/drivers/acore/clocks_config_priv.c +++ b/code/sdk/drivers/chips/brandy/clocks/drivers/acore/clocks_config_priv.c @@ -79,7 +79,7 @@ static const clocks_clk_cfg_t g_system_all_core_clocks[CLOCKS_CONFIG_MAX][CLOCKS {CLOCKS_CLK_SRC_TCXO, CLOCK_DIV_1}, // CLOCKS_CCRG_MODULE_MCU_PERP_UART {CLOCKS_CLK_SRC_TCXO, CLOCK_DIV_1}, // CLOCKS_CCRG_MODULE_MCU_PERP_SPI {CLOCKS_CLK_SRC_TCXO, CLOCK_DIV_1}, // CLOCKS_CCRG_MODULE_COM_BUS - {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_3}, // CLOCKS_CCRG_MODULE_SDIOM + {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_9}, // CLOCKS_CCRG_MODULE_SDIOM {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_8}, // CLOCKS_CCRG_MODULE_MEM_BUS {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_4}, // CLOCKS_CCRG_MODULE_XIP_OPI {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_5}, // CLOCKS_CCRG_MODULE_XIP_QSPI @@ -95,9 +95,9 @@ static const clocks_clk_cfg_t g_system_all_core_clocks[CLOCKS_CONFIG_MAX][CLOCKS {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_4}, // CLOCKS_CCRG_MODULE_MCU_CORE {CLOCKS_CLK_SRC_TCXO, CLOCK_DIV_1}, // CLOCKS_CCRG_MODULE_MCU_PERP_LS {CLOCKS_CLK_SRC_TCXO, CLOCK_DIV_1}, // CLOCKS_CCRG_MODULE_MCU_PERP_UART - {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_10}, // CLOCKS_CCRG_MODULE_MCU_PERP_SPI + {CLOCKS_CLK_SRC_TCXO, CLOCK_DIV_1}, // CLOCKS_CCRG_MODULE_MCU_PERP_SPI {CLOCKS_CLK_SRC_TCXO, CLOCK_DIV_1}, // CLOCKS_CCRG_MODULE_COM_BUS - {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_3}, // CLOCKS_CCRG_MODULE_SDIOM + {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_9}, // CLOCKS_CCRG_MODULE_SDIOM {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_5}, // CLOCKS_CCRG_MODULE_MEM_BUS {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_3}, // CLOCKS_CCRG_MODULE_XIP_OPI {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_5}, // CLOCKS_CCRG_MODULE_XIP_QSPI @@ -325,14 +325,14 @@ static const system_mcu_core_clk_cfg_t g_system_mcu_freq_config[CLOCKS_MCU_FREQ_ {CLOCKS_CLK_SRC_TCXO_2X, CLOCK_DIV_1}, // sdiom: 64M #endif {CLOCKS_CLK_SRC_TCXO_2X, CLOCK_DIV_1}, // gpu: 64M - {CLOCKS_CLK_SRC_TCXO_2X, CLOCK_DIV_1}, // spi: 64M + {CLOCKS_CLK_SRC_TCXO, CLOCK_DIV_1}, // spi: 32M }, { // CLOCKS_M_H0 {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_8}, // mcu_clk:110M {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_4}, // psram_clk:225M {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_8}, // membus:110M {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_5}, // flash: norflash & nandflash: 176M - {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_3}, // sdiom:295M + {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_9}, // sdiom:98M {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_6}, // gpu:147M {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_9}, // spi:98M }, @@ -341,9 +341,9 @@ static const system_mcu_core_clk_cfg_t g_system_mcu_freq_config[CLOCKS_MCU_FREQ_ {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_3}, // psram_clk:295M {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_5}, // membus:177M {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_5}, // flash: norflash & nandflash:177M - {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_3}, // sdiom:295M + {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_9}, // sdiom:98M {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_6}, // gpu:147M - {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_10}, // spi:88M + {CLOCKS_CLK_SRC_TCXO, CLOCK_DIV_1}, // spi:32M }, }; @@ -351,7 +351,7 @@ static const clocks_clk_cfg_t g_system_sdio_freq_config[CLOCKS_SDIO_FREQ_MAX] = {CLOCKS_CLK_SRC_TCXO, CLOCK_DIV_1}, // 32M {CLOCKS_CLK_SRC_RC, CLOCK_DIV_1}, // 50M {CLOCKS_CLK_SRC_TCXO_2X, CLOCK_DIV_1}, // 64M - {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_3}, // 294.912M + {CLOCKS_CLK_SRC_PLL, CLOCK_DIV_9}, // 98M }; /************************** MCU core all perips clock Config *********************/ diff --git a/code/sdk/drivers/chips/brandy/clocks/hal/hal_clocks_app_priv.c b/code/sdk/drivers/chips/brandy/clocks/hal/hal_clocks_app_priv.c index 91aaa6d53..68dec0cc8 100644 --- a/code/sdk/drivers/chips/brandy/clocks/hal/hal_clocks_app_priv.c +++ b/code/sdk/drivers/chips/brandy/clocks/hal/hal_clocks_app_priv.c @@ -175,7 +175,7 @@ uint8_t hal_clocks_ccrg_module_get_div(hal_clocks_ccrg_module_t module) if (div_en == 0) { return CLK_DIV_1; } else { - uint8_t div = reg16_getbits(reg_addr, COMM_CLK_DIV_NUM_POS, COMM_CLK_SRC_LEN); + uint8_t div = reg16_getbits(reg_addr, COMM_CLK_DIV_NUM_POS, COMM_CLK_NUM_LEN); if (div == 0) { div = 1; } diff --git a/code/sdk/drivers/drivers/driver/audio/source/core/osal/liteos/audio_osal_addr.c b/code/sdk/drivers/drivers/driver/audio/source/core/osal/liteos/audio_osal_addr.c index 664af23cd..c5c88671c 100644 --- a/code/sdk/drivers/drivers/driver/audio/source/core/osal/liteos/audio_osal_addr.c +++ b/code/sdk/drivers/drivers/driver/audio/source/core/osal/liteos/audio_osal_addr.c @@ -55,7 +55,7 @@ td_void *audio_osal_malloc(td_ulong size) #ifdef BRANDY_PROT return LOS_MemAlloc(m_aucSysMem0, size); #else - return osal_kmalloc(size, 0); + return malloc(size); #endif } @@ -80,7 +80,7 @@ td_void audio_osal_free(td_void *addr) #ifdef BRANDY_PROT LOS_MemFree(m_aucSysMem0, addr); #else - osal_kfree(addr); + free(addr); #endif } diff --git a/code/sdk/drivers/drivers/driver/ipc/ipc_old/shared/ipc.c b/code/sdk/drivers/drivers/driver/ipc/ipc_old/shared/ipc.c index 42668534f..67cced400 100644 --- a/code/sdk/drivers/drivers/driver/ipc/ipc_old/shared/ipc.c +++ b/code/sdk/drivers/drivers/driver/ipc/ipc_old/shared/ipc.c @@ -726,7 +726,7 @@ static void ipc_spin_send_fail_info_lock(hal_cpu_trace_traced_cpu_t cpu, cores_t oml_pf_log_print4(LOG_ACORE_PLT_BSP_DRIVER_IPC, LOG_NUM_DEBUG, LOG_LEVEL_ERROR, "ipc error, core=%d current pc=0x%x, lr=0x%x, sp=0x%x", dst, pc, lr, sp); #endif - PRINT("%d => %d ipc error, get pc=0x%x, lr=0x%x sp=0x%X", CORE, dst, pc, lr, sp); + PRINT("%d => %d ipc action=%d error, get pc=0x%x, lr=0x%x sp=0x%x\r\n", CORE, dst, action, pc, lr, sp); } #endif diff --git a/code/sdk/drivers/drivers/driver/ipc/ipc_old/shared/ipc_actions.h b/code/sdk/drivers/drivers/driver/ipc/ipc_old/shared/ipc_actions.h index 301f52203..9bb7b28d3 100644 --- a/code/sdk/drivers/drivers/driver/ipc/ipc_old/shared/ipc_actions.h +++ b/code/sdk/drivers/drivers/driver/ipc/ipc_old/shared/ipc_actions.h @@ -75,6 +75,8 @@ typedef enum { IPC_ACTION_DSP_POWER_STATE = 42, // !< Used by DSP core to inform App core POWER state IPC_ACTION_BT_READ_NV_CUSTOMIZE = 43, // !< Used by BT core to inform app core bt needs to load customized nv. IPC_ACTION_APP_LOAD_NV_CUSTOMIZE = 44, // !< Used by APP core to inform bt core customized nv exist or not. + IPC_ACTION_UART_AGENT_TX = 48, // !< Used by APP core to send data to BT core. + IPC_ACTION_UART_AGENT_RX = 49, // !< Used by APP core to rcv data to BT core. IPC_ACTION_GNSS_START = 50, // !< [50:] is used by gnss. IPC_ACTION_GNSS_LOG_INFO = IPC_ACTION_GNSS_START + 0, IPC_ACTION_GNSS_MSG = IPC_ACTION_GNSS_START + 1, diff --git a/code/sdk/drivers/drivers/driver/mmc/host/sdhci/brandy/mmc_sdhci.c b/code/sdk/drivers/drivers/driver/mmc/host/sdhci/brandy/mmc_sdhci.c index 56869e22f..95e58b25b 100644 --- a/code/sdk/drivers/drivers/driver/mmc/host/sdhci/brandy/mmc_sdhci.c +++ b/code/sdk/drivers/drivers/driver/mmc/host/sdhci/brandy/mmc_sdhci.c @@ -25,7 +25,6 @@ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------------------------------------- */ - #include "soc_mmc.h" #include "hci.h" #include "sdhci.h" @@ -61,6 +60,11 @@ #define XO_DLL2_CLK_VALUE 64000000 #define PLL_CLK_VALUE 884736000 +#define PMU2_CMU_CLK_EN_CFG_REG (PMU2_CMU_CTL_RB_BASE + 0x20) +#define PMU2_CMU_PLL_CLK_EN_BIT 0 +#define PMU2_CMU_PLL_LOCK_STS_REG (PMU2_CMU_CTL_RB_BASE + 0x2d8) +#define PMU2_CMU_PLL_LOCK_STS_BIT 0 + #ifndef SDHCI_ERR_INT_STAT_EN #define SDHCI_ERR_INT_STAT_EN 0x36 #endif @@ -100,7 +104,8 @@ uint8_t g_sdiom_sel_mode = SDIOM_SEL_PERF_MODE; uint32_t g_sdiom_cfg_clk[MAX_MMC_NUM] = {0, 0}; system_sdio_freq_t g_sdiom_mmc_sel[MAX_MMC_NUM] = {CLOCKS_SDIO_FREQ_MAX, CLOCKS_SDIO_FREQ_MAX}; system_sdio_freq_t g_sdiom_cur_sel = CLOCKS_SDIO_FREQ_MAX; - +uint32_t g_pll_lock_fail[MAX_MMC_NUM] = {0, 0}; +uint32_t g_mmc_lock_fail[MAX_MMC_NUM] = {0, 0}; static mmc_save_info_t g_mmc_cur_info[MAX_MMC_NUM] = { {0}, {0} }; bool g_mmc_sleep_inited = false; @@ -137,6 +142,47 @@ bool mmc_get_sleep_init_flag(void) return g_mmc_sleep_inited; } +static void mmc_sdhci_reg_save(struct hci_softc *sc) +{ + int i = sc->num; + + reg16_setbit(g_clk_div1_reg[i], 0); // clk en + g_mmc_cur_info[i].timing = regw_getbits(sc->base, SDHCI_HOST_CONTROL2, 0x0, LEN_3BIT); // for speed mode + g_mmc_cur_info[i].at_ctrl = hci_readl(sc, SDHCI_AUTO_TUNING_CTRL); + g_mmc_cur_info[i].at_stat = regw_getbits(sc->base, SDHCI_AUTO_TUNING_STATUS, 0x0, LEN_8BIT); // for phase + if (reg8_getbit(sc->base + SDHCI_HOST_CONTROL, EXT_DAT_XFER_BIT) == 1) { + g_mmc_cur_info[i].bus_width = EMMC_SAVE_BUS_WIDTH_8BIT; + } else { + if (reg8_getbit(sc->base + SDHCI_HOST_CONTROL, 0x1) == 1) { + g_mmc_cur_info[i].bus_width = EMMC_SAVE_BUS_WIDTH_4BIT; + } else { + g_mmc_cur_info[i].bus_width = EMMC_SAVE_BUS_WIDTH_1BIT; + } + } + + g_mmc_cur_info[i].mbiu_ctrl = hci_readw(sc, SDHCI_MBIU_CTRL); + g_mmc_cur_info[i].clk_ctrl = hci_readw(sc, SDHCI_CLOCK_CONTROL); + g_mmc_cur_info[i].power_ctrl = hci_readb(sc, SDHCI_POWER_CONTROL); + g_mmc_cur_info[i].host_ctrl1 = hci_readb(sc, SDHCI_HOST_CONTROL); + g_mmc_cur_info[i].host_ctrl2 = hci_readw(sc, SDHCI_HOST_CONTROL2); + g_mmc_cur_info[i].int_en = hci_readl(sc, SDHCI_INT_ENABLE); + g_mmc_cur_info[i].int_sig_en = hci_readl(sc, SDHCI_SIGNAL_ENABLE); + reg16_clrbit(g_clk_div1_reg[i], 0); // clk disable +} + +static void mmc_sdhci_suspend_debug(struct hci_softc *sc) +{ +#if MMC_BOARD_DEBUG_ON + int i = sc->num; + PRINT("mmc%d save sdiom=0x%x, clk_div1=0x%x, clk_div2=0x%x, timing=%d, phase=%d, bus_width=%d\r\n", + i, g_mmc_cur_info[i].sdiom_clk_reg, g_mmc_cur_info[i].clk_div1_reg, g_mmc_cur_info[i].clk_div2_reg, + g_mmc_cur_info[i].timing, g_mmc_cur_info[i].at_stat, g_mmc_cur_info[i].bus_width); + PRINT("mmc%d save clk_ctrl=0x%x, power_ctrl=0x%x, host_ctrl1=0x%x, host_ctrl2=0x%x\r\n", + i, g_mmc_cur_info[i].clk_ctrl, g_mmc_cur_info[i].power_ctrl, g_mmc_cur_info[i].host_ctrl1, + g_mmc_cur_info[i].host_ctrl2); + PRINT("mmc%d save int_en=0x%x, sig_en=0x%x\r\n", i, g_mmc_cur_info[i].int_en, g_mmc_cur_info[i].int_sig_en); +#endif +} /* * 函 数 名 : mmc_sdhci_suspend * 功能描述 : 低功耗suspend接口, 保存所有mmc slot工作必须的寄存器 @@ -146,46 +192,39 @@ void mmc_sdhci_suspend(void) int32_t i; struct hci_softc *sc = NULL; + // soc reg save for (i = 0; i < MAX_MMC_NUM; i++) { sc = get_mmc_resource(i); if (sc == NULL || sc->slot == NULL || ((struct sdhci_slot*)sc->slot)->dev == NULL) { continue; } - - reg16_setbit(g_clk_div1_reg[i], 0); // clk en - g_mmc_cur_info[i].timing = regw_getbits(sc->base, SDHCI_HOST_CONTROL2, 0x0, LEN_3BIT); // for speed mode - g_mmc_cur_info[i].at_ctrl = hci_readl(sc, SDHCI_AUTO_TUNING_CTRL); - g_mmc_cur_info[i].at_stat = regw_getbits(sc->base, SDHCI_AUTO_TUNING_STATUS, 0x0, LEN_8BIT); // for phase - if (reg8_getbit(sc->base + SDHCI_HOST_CONTROL, EXT_DAT_XFER_BIT) == 1) { - g_mmc_cur_info[i].bus_width = EMMC_SAVE_BUS_WIDTH_8BIT; - } else { - if (reg8_getbit(sc->base + SDHCI_HOST_CONTROL, 0x1) == 1) { - g_mmc_cur_info[i].bus_width = EMMC_SAVE_BUS_WIDTH_4BIT; - } else { - g_mmc_cur_info[i].bus_width = EMMC_SAVE_BUS_WIDTH_1BIT; - } - } g_mmc_cur_info[i].sdiom_clk_reg = readw(SDIOM_CR_REG); g_mmc_cur_info[i].clk_div1_reg = readw(g_clk_div1_reg[i]); g_mmc_cur_info[i].clk_div2_reg = readw(g_clk_div2_reg[i]); g_mmc_cur_info[i].sd_bus_reg = readw(SDIO_BUS_CGDIV_REG); - g_mmc_cur_info[i].mbiu_ctrl = hci_readw(sc, SDHCI_MBIU_CTRL); - g_mmc_cur_info[i].clk_ctrl = hci_readw(sc, SDHCI_CLOCK_CONTROL); - g_mmc_cur_info[i].power_ctrl = hci_readb(sc, SDHCI_POWER_CONTROL); - g_mmc_cur_info[i].host_ctrl1 = hci_readb(sc, SDHCI_HOST_CONTROL); - g_mmc_cur_info[i].host_ctrl2 = hci_readw(sc, SDHCI_HOST_CONTROL2); - g_mmc_cur_info[i].int_en = hci_readl(sc, SDHCI_INT_ENABLE); - g_mmc_cur_info[i].int_sig_en = hci_readl(sc, SDHCI_SIGNAL_ENABLE); -#if MMC_BOARD_DEBUG_ON - PRINT("mmc%d save sdiom=0x%x, clk_div1=0x%x, clk_div2=0x%x, timing=%d, phase=%d, bus_width=%d\r\n", - i, g_mmc_cur_info[i].sdiom_clk_reg, g_mmc_cur_info[i].clk_div1_reg, g_mmc_cur_info[i].clk_div2_reg, - g_mmc_cur_info[i].timing, g_mmc_cur_info[i].at_stat, g_mmc_cur_info[i].bus_width); - PRINT("mmc%d save clk_ctrl=0x%x, power_ctrl=0x%x, host_ctrl1=0x%x, host_ctrl2=0x%x\r\n", - i, g_mmc_cur_info[i].clk_ctrl, g_mmc_cur_info[i].power_ctrl, g_mmc_cur_info[i].host_ctrl1, - g_mmc_cur_info[i].host_ctrl2); - PRINT("mmc%d save int_en=0x%x, sig_en=0x%x\r\n", i, g_mmc_cur_info[i].int_en, g_mmc_cur_info[i].int_sig_en); -#endif - reg16_clrbit(g_clk_div1_reg[i], 0); // clk disable + } + + // sdhci reg save + for (i = 0; i < MAX_MMC_NUM; i++) { + sc = get_mmc_resource(i); + if (sc == NULL || sc->slot == NULL || ((struct sdhci_slot*)sc->slot)->dev == NULL) { + continue; + } + + // 检查pll时钟是否失锁 + if (g_sdiom_cur_sel == CLOCKS_SDIO_FREQ_H) { + if (((readw(PMU2_CMU_CLK_EN_CFG_REG) & 0x1) == 0) || ((readw(PMU2_CMU_PLL_LOCK_STS_REG) & 0x1) == 0)) { + g_pll_lock_fail[i]++; + } + // 切换sdiom时钟到32M XO时钟 + reg16_clrbit(g_clk_div1_reg[i], 0); // clk dis en + writew(SDIOM_CR_REG, SDIOM_CR_CTRL_XO_32M_CLK_EN); + reg16_setbit(g_clk_div1_reg[i], 0); // clk en + } + + mmc_sdhci_reg_save(sc); + + mmc_sdhci_suspend_debug(sc); } mmc_set_sleep_init_flag(false); } @@ -198,6 +237,7 @@ void mmc_sdhci_resume(void) { int32_t i; struct hci_softc *sc; + uint32_t timeout; for (i = 0; i < MAX_MMC_NUM; i++) { sc = get_mmc_resource(i); @@ -209,12 +249,23 @@ void mmc_sdhci_resume(void) #endif writew(SDIOM_CR_REG, g_mmc_cur_info[i].sdiom_clk_reg); writew(g_clk_div1_reg[i], g_mmc_cur_info[i].clk_div1_reg); + reg16_setbit(g_clk_div1_reg[i], 0); // clk en writew(g_clk_div2_reg[i], g_mmc_cur_info[i].clk_div2_reg); writew(SDIO_BUS_CGDIV_REG, g_mmc_cur_info[i].sd_bus_reg); reg16_setbit(sc->base + SDHCI_CLOCK_CONTROL, 0x0); // offset:2c bit0 internal clk en reg16_setbit(sc->base + SDHCI_CLOCK_CONTROL, 0x3); // offset:2c bit3 pll enable reg16_setbit(sc->base + SDHCI_CLOCK_CONTROL, 0x2); // offset:2c bit2 sd clk enable - while (reg16_getbit(sc->base + SDHCI_CLOCK_CONTROL, 0x1) != 1) { ; } // wait clock is stability + /* Wait up to 1000 ms until it stabilize. */ + timeout = 1000; + while (reg16_getbit(sc->base + SDHCI_CLOCK_CONTROL, 0x1) != 1) { + if (timeout == 0) { + PRINT("mmc%d resume wait clk stable timeout\r\n", i); + g_mmc_lock_fail[i]++; + break; + } + timeout--; + osal_udelay(1000); // delay 1000us + } hci_writeb(sc, SDHCI_TIMEOUT_CONTROL, 0xe); hci_writew(sc, SDHCI_CLOCK_CONTROL, g_mmc_cur_info[i].clk_ctrl); @@ -237,6 +288,22 @@ void mmc_sdhci_resume(void) mmc_set_sleep_init_flag(true); } +void mmc_sdhci_clock_info(void) +{ + int32_t i; + struct hci_softc *sc; + + for (i = 0; i < MAX_MMC_NUM; i++) { + sc = get_mmc_resource(i); + if (sc == NULL || sc->slot == NULL || ((struct sdhci_slot*)sc->slot)->dev == NULL) { + continue; + } + PRINT("mmc%d:clk_src=%d,sdiom_div=%d,bus_div=%d,div1=%d,div2=%d,pll_lockfail=%d,sdhci_lockfail=%d\r\n", i, + regw_getbits(SDIOM_CR_REG, 0, 0x1, 0x3), regw_getbits(SDIOM_CR_REG, 0, 0x5, 0x4), + regw_getbits(SDIO_BUS_CGDIV_REG, 0, 0x3, 0x5), regw_getbits(g_clk_div1_reg[i], 0, 0x4, 0x8), + regw_getbits(g_clk_div2_reg[i], 0, 0x1, 0x3), g_pll_lock_fail[i], g_mmc_lock_fail[i]); + } +} #ifdef CFG_DRIVERS_SDIO /* * 函 数 名 : mmc_sdhci_sdio_reset @@ -492,10 +559,10 @@ uint32_t mmc_get_clock_value(uint32_t id) div2 = regw_getbits(g_clk_div1_reg[id], 0, 0x4, 0x8); } if (reg16_getbit(g_clk_div2_reg[id], 0x0) == 1) { - div3 = regw_getbits(g_clk_div2_reg[id], 0, 0x4, 0x3); + div3 = regw_getbits(g_clk_div2_reg[id], 0, 0x1, 0x3); } #if MMC_BOARD_DEBUG_ON - PRINT("clk_flag=%d, value=%lu, div1=%d div2=%d, div3=%d\r\n", clk_flag, source_clk_val, div1, div2, div3); + PRINT("clk_flag=%d,value=%lu,div1=%d,div2=%d,div3=%d\r\n", clk_flag, source_clk_val, div1, div2, div3); #endif return (source_clk_val / div1 / div2 / div3); } @@ -545,37 +612,32 @@ static int mmc_voltage_switch(struct hci_softc *sc, uint32_t vccq) return 0; } -static void mmc_set_sd_bus_clk_div(uint32_t div_reg, uint32_t freq_div) +void mmc_set_sd_bus_clk_div(uint32_t freq_div) { uint16_t value; - value = DPAL_GET_UINT16(div_reg); + value = DPAL_GET_UINT16(SDIO_BUS_CGDIV_REG); value &= ~SD_BUS_LOAD_DIV_EN; - DPAL_WRITE_UINT16(value, div_reg); + DPAL_WRITE_UINT16(value, SDIO_BUS_CGDIV_REG); value &= ~SD_BUS_DIV_NUM_MASK; value |= (uint16_t)(freq_div << SD_BUS_DIV_NUM_POST_SHIFT); - DPAL_WRITE_UINT16(value, div_reg); + DPAL_WRITE_UINT16(value, SDIO_BUS_CGDIV_REG); value |= SD_BUS_LOAD_DIV_EN; - DPAL_WRITE_UINT16(value, div_reg); + DPAL_WRITE_UINT16(value, SDIO_BUS_CGDIV_REG); } static void mmc_calc_sdiom_clk_div(system_sdio_freq_t freq_level, uint32_t cfg_clock, uint32_t *freq_div, uint32_t *second_freq_div) { uint32_t sdiom_freq_val[CLOCKS_SDIO_FREQ_MAX] = { - SDIOM_SRC_CLK_LOW_FREQ_VAL, SDIOM_SRC_CLK_FREQ_LVL_50M_VAL, + SDIOM_SRC_CLK_LOW_FREQ_VAL, SDIOM_SRC_CLK_FREQ_LVL_49M_VAL, SDIOM_SRC_CLK_FREQ_LVL_64M_VAL, SDIOM_SRC_CLK_HIGH_FREQ_LVL_VAL }; - if (freq_level == CLOCKS_SDIO_FREQ_H && cfg_clock <= SDIOM_SRC_CLK_FREQ_LVL_98M_VAL) { - *second_freq_div = 3; // 3：选PLL时钟频率经过3分频到98Mhz，二级分频才能满足低频要求，如400Khz的探卡频率 - } else { - *second_freq_div = 1; - } - + *second_freq_div = 1; if (cfg_clock <= sdiom_freq_val[freq_level]) { *freq_div = sdiom_freq_val[freq_level] / (cfg_clock * (*second_freq_div)); - if (freq_level == CLOCKS_SDIO_FREQ_32M || freq_level == CLOCKS_SDIO_FREQ_H) { - if (sdiom_freq_val[freq_level] % (cfg_clock * (*second_freq_div)) != 0) { *freq_div += 1; } + if (sdiom_freq_val[freq_level] % (cfg_clock * (*second_freq_div)) != 0) { + *freq_div += 1; } } else { *freq_div = 1; @@ -795,7 +857,6 @@ unsigned int mmc_set_clock_with_way2(struct hci_softc *sc, unsigned int cfg_cloc #endif } g_sdiom_cur_sel = sdiom_freq_level; - mmc_set_sd_bus_clk_div(SDIO_BUS_CGDIV_REG, 1); return 0; } diff --git a/code/sdk/drivers/drivers/driver/mmc/include/soc_mmc.h b/code/sdk/drivers/drivers/driver/mmc/include/soc_mmc.h index 9cd6c83ab..2b11da8f6 100644 --- a/code/sdk/drivers/drivers/driver/mmc/include/soc_mmc.h +++ b/code/sdk/drivers/drivers/driver/mmc/include/soc_mmc.h @@ -260,7 +260,7 @@ extern "C" { #define SDIOM_SRC_CLK_FREQ_LVL_64M_VAL 64000000 // 64MHz #define SDIOM_SRC_CLK_FREQ_LVL_49M_VAL 49000000 #define SDIOM_SRC_CLK_FREQ_LVL_98M_VAL 98000000 // 98MHz -#define SDIOM_SRC_CLK_HIGH_FREQ_LVL_VAL 294000000 // 294MHz +#define SDIOM_SRC_CLK_HIGH_FREQ_LVL_VAL SDIOM_SRC_CLK_FREQ_LVL_98M_VAL #define SDHCI_CMD_CONFLIT_CHECK 0x01 @@ -290,7 +290,7 @@ void mmc_set_first_init_flag(bool flag); bool mmc_get_first_init_flag(void); void mmc_set_sleep_init_flag(bool flag); bool mmc_get_sleep_init_flag(void); - +void mmc_sdhci_clock_info(void); #ifdef __cplusplus #if __cplusplus } diff --git a/code/sdk/drivers/drivers/driver/nand_flash/nand/include/nandflash_inner.h b/code/sdk/drivers/drivers/driver/nand_flash/nand/include/nandflash_inner.h index eddf19100..7e09ea27b 100644 --- a/code/sdk/drivers/drivers/driver/nand_flash/nand/include/nandflash_inner.h +++ b/code/sdk/drivers/drivers/driver/nand_flash/nand/include/nandflash_inner.h @@ -56,7 +56,7 @@ typedef enum nandflash_trans_type { } nandflash_trans_type_t; typedef enum nandflash_trans_speed { - SPEED_HIGH = 8, + SPEED_HIGH = 12, SPEED_MID = 12, SPEED_SLOW = 16, } nandflash_speed_type_t; diff --git a/code/sdk/drivers/drivers/driver/spi/spi.c b/code/sdk/drivers/drivers/driver/spi/spi.c index 10fef8aa4..a6ac414b1 100644 --- a/code/sdk/drivers/drivers/driver/spi/spi.c +++ b/code/sdk/drivers/drivers/driver/spi/spi.c @@ -1160,12 +1160,7 @@ static errcode_t spi_master_read_dma(spi_bus_t bus, const spi_xfer_data_t *data, if (spi_get_attr_tmod(bus) == HAL_SPI_TRANS_MODE_RX) { return spi_read_by_writeread(bus, data, timeout); } - - errcode_t ret = spi_read_dma(bus, data, timeout); - if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) { - return ERRCODE_SPI_TIMEOUT; - } - return ret; + return spi_read_dma(bus, data, timeout); } #endif /* NOT CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH */ #endif /* CONFIG_SPI_SUPPORT_DMA */ @@ -1208,11 +1203,6 @@ errcode_t uapi_spi_master_read(spi_bus_t bus, const spi_xfer_data_t *data, uint3 uint32_t irq_sts = spi_porting_lock(bus); ret = g_hal_funcs->read(bus, (hal_spi_xfer_data_t *)data, timeout_tmp); - if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, timeout_tmp) != ERRCODE_SUCC) { - spi_porting_unlock(bus, irq_sts); - spi_mutex_unlock(bus); - return ERRCODE_SPI_TIMEOUT; - } spi_porting_unlock(bus, irq_sts); spi_mutex_unlock(bus); @@ -1234,10 +1224,6 @@ errcode_t uapi_spi_master_writeread(spi_bus_t bus, const spi_xfer_data_t *data, data->tx_bytes > CONFIG_SPI_AUTO_SWITCH_DMA_THRESHOLD) { uapi_spi_set_dma_mode(bus, true, NULL); ret = spi_writeread_dma(bus, data, timeout_tmp); - if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) { - spi_mutex_unlock(bus); - return ERRCODE_SPI_TIMEOUT; - } spi_mutex_unlock(bus); return ret; } @@ -1246,10 +1232,6 @@ errcode_t uapi_spi_master_writeread(spi_bus_t bus, const spi_xfer_data_t *data, #if defined(CONFIG_SPI_SUPPORT_DMA) && (CONFIG_SPI_SUPPORT_DMA == 1) if (g_dma_trans_tx[bus].is_enable && g_dma_trans_rx[bus].is_enable) { ret = spi_writeread_dma(bus, data, timeout_tmp); - if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) { - spi_mutex_unlock(bus); - return ERRCODE_SPI_TIMEOUT; - } spi_mutex_unlock(bus); return ret; } @@ -1258,11 +1240,7 @@ errcode_t uapi_spi_master_writeread(spi_bus_t bus, const spi_xfer_data_t *data, uint32_t irq_sts = spi_porting_lock(bus); ret = g_hal_funcs->writeread(bus, (hal_spi_xfer_data_t *)data, timeout_tmp); - if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, timeout_tmp) != ERRCODE_SUCC) { - spi_porting_unlock(bus, irq_sts); - spi_mutex_unlock(bus); - return ERRCODE_SPI_TIMEOUT; - } + spi_porting_unlock(bus, irq_sts); spi_mutex_unlock(bus); @@ -1289,10 +1267,6 @@ errcode_t uapi_spi_slave_write(spi_bus_t bus, const spi_xfer_data_t *data, uint3 if (data->tx_bytes > CONFIG_SPI_AUTO_SWITCH_DMA_THRESHOLD) { uapi_spi_set_dma_mode(bus, true, NULL); ret = spi_write_dma(bus, data, timeout_tmp); - if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) { - spi_mutex_unlock(bus); - return ERRCODE_SPI_TIMEOUT; - } spi_mutex_unlock(bus); return ret; } @@ -1301,10 +1275,6 @@ errcode_t uapi_spi_slave_write(spi_bus_t bus, const spi_xfer_data_t *data, uint3 #if defined(CONFIG_SPI_SUPPORT_DMA) && (CONFIG_SPI_SUPPORT_DMA == 1) if (g_dma_trans_tx[bus].is_enable) { ret = spi_write_dma(bus, data, timeout_tmp); - if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) { - spi_mutex_unlock(bus); - return ERRCODE_SPI_TIMEOUT; - } spi_mutex_unlock(bus); return ret; } @@ -1320,11 +1290,7 @@ errcode_t uapi_spi_slave_write(spi_bus_t bus, const spi_xfer_data_t *data, uint3 uint32_t irq_sts = spi_porting_lock(bus); ret = g_hal_funcs->write(bus, (hal_spi_xfer_data_t *)data, timeout_tmp); - if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, timeout_tmp) != ERRCODE_SUCC) { - spi_porting_unlock(bus, irq_sts); - spi_mutex_unlock(bus); - return ERRCODE_SPI_TIMEOUT; - } + spi_porting_unlock(bus, irq_sts); spi_mutex_unlock(bus); @@ -1345,10 +1311,6 @@ errcode_t uapi_spi_slave_read(spi_bus_t bus, const spi_xfer_data_t *data, uint32 if (data->rx_bytes > CONFIG_SPI_AUTO_SWITCH_DMA_THRESHOLD) { uapi_spi_set_dma_mode(bus, true, NULL); ret = spi_read_dma(bus, data, timeout_tmp); - if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) { - spi_mutex_unlock(bus); - return ERRCODE_SPI_TIMEOUT; - } spi_mutex_unlock(bus); return ret; } @@ -1357,10 +1319,6 @@ errcode_t uapi_spi_slave_read(spi_bus_t bus, const spi_xfer_data_t *data, uint32 #if defined(CONFIG_SPI_SUPPORT_DMA) && (CONFIG_SPI_SUPPORT_DMA == 1) if (g_dma_trans_rx[bus].is_enable) { ret = spi_read_dma(bus, data, timeout_tmp); - if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) { - spi_mutex_unlock(bus); - return ERRCODE_SPI_TIMEOUT; - } spi_mutex_unlock(bus); return ret; } @@ -1377,11 +1335,7 @@ errcode_t uapi_spi_slave_read(spi_bus_t bus, const spi_xfer_data_t *data, uint32 uint32_t irq_sts = spi_porting_lock(bus); ret = g_hal_funcs->read(bus, (hal_spi_xfer_data_t *)data, timeout_tmp); - if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, timeout_tmp) != ERRCODE_SUCC) { - spi_porting_unlock(bus, irq_sts); - spi_mutex_unlock(bus); - return ERRCODE_SPI_TIMEOUT; - } + spi_porting_unlock(bus, irq_sts); spi_mutex_unlock(bus); diff --git a/code/sdk/drivers/drivers/hal/spi/hal_spi.h b/code/sdk/drivers/drivers/hal/spi/hal_spi.h index 6f31d0d21..fc2ab443b 100644 --- a/code/sdk/drivers/drivers/hal/spi/hal_spi.h +++ b/code/sdk/drivers/drivers/hal/spi/hal_spi.h @@ -405,9 +405,16 @@ typedef struct hal_spi_attr { uint32_t bus_clk; /*!< @if Eng Provide ssi_clk for clock freq division calculation. @else 用于计算SPI的时钟分频系数。 @endif */ - uint32_t freq_mhz; /*!< @if Eng Indicates the frequency of SPI. - @else SPI的工作频率。 @endif */ - + uint32_t freq_mhz; /*!< @if Eng Indicates the frequency of SPI in MHz. + Only one of freq_mhz or freq_hz can be non-zero and effective. + @else SPI的工作频率（MHz）。 + freq_mhz和freq_hz只能有一个非零且有效。 @endif */ +#ifdef CONFIG_SPI_SUPPORT_HZ + uint32_t freq_hz; /*!< @if Eng Indicates the frequency of SPI in Hz. + Only one of freq_mhz or freq_hz can be non-zero and effective. + @else SPI的工作频率（Hz）。 + freq_mhz和freq_hz只能有一个非零且有效。 @endif */ +#endif uint32_t clk_polarity; /*!< @if Eng Indicates the clock polarity of SPI. For details, see @ref hal_spi_cfg_clk_cpol_t @else SPI的时钟极性。参考 @ref hal_spi_cfg_clk_cpol_t @endif */ diff --git a/code/sdk/drivers/drivers/hal/spi/v100/hal_spi_v100.c b/code/sdk/drivers/drivers/hal/spi/v100/hal_spi_v100.c index 3863b7cd4..6567b1f48 100644 --- a/code/sdk/drivers/drivers/hal/spi/v100/hal_spi_v100.c +++ b/code/sdk/drivers/drivers/hal/spi/v100/hal_spi_v100.c @@ -15,6 +15,8 @@ #define SPI_MINUMUM_CLOCK_IN_MHZ 1 #define SPI_MAXIMUM_CLOCK_IN_MHZ 48 +#define SPI_MINUMUM_CLOCK_IN_HZ 10000 +#define SPI_MAXIMUM_CLOCK_IN_HZ 48000000 #define QSPI_MINUMUM_CLOCK_IN_MHZ 1 #define QSPI_MAXIMUM_CLOCK_IN_MHZ 96 @@ -47,18 +49,37 @@ static inline bool hal_spi_check_timeout_by_count(uint32_t *trans_time, uint32_t return ((*trans_time > timeout) ? true : false); } -static bool hal_spi_is_attr_freq_valid(const uint32_t clk_in_mhz, const hal_spi_frame_format_t spi_frame_format) +static bool hal_spi_is_attr_freq_valid(const hal_spi_attr_t *attr, const hal_spi_frame_format_t spi_frame_format) { - if (spi_frame_format == HAL_SPI_FRAME_FORMAT_STANDARD) { - if ((clk_in_mhz < SPI_MINUMUM_CLOCK_IN_MHZ) || (clk_in_mhz > SPI_MAXIMUM_CLOCK_IN_MHZ)) { +#ifdef CONFIG_SPI_SUPPORT_HZ + if ((attr->freq_hz == 0 && attr->freq_mhz == 0) || + (attr->freq_hz != 0 && attr->freq_mhz != 0)) { + return false; + } + if (attr->freq_hz != 0) { + if (spi_frame_format == HAL_SPI_FRAME_FORMAT_STANDARD) { + if ((attr->freq_hz < SPI_MINUMUM_CLOCK_IN_HZ) || (attr->freq_hz > SPI_MAXIMUM_CLOCK_IN_HZ)) { + return false; + } + } else { return false; } - } else { - if ((clk_in_mhz < QSPI_MINUMUM_CLOCK_IN_MHZ) || (clk_in_mhz > QSPI_MAXIMUM_CLOCK_IN_MHZ)) { - return false; + return true; + } +#endif + if (attr->freq_mhz != 0) { + if (spi_frame_format == HAL_SPI_FRAME_FORMAT_STANDARD) { + if ((attr->freq_mhz < SPI_MINUMUM_CLOCK_IN_MHZ) || (attr->freq_mhz > SPI_MAXIMUM_CLOCK_IN_MHZ)) { + return false; + } + } else { + if ((attr->freq_mhz < QSPI_MINUMUM_CLOCK_IN_MHZ) || (attr->freq_mhz > QSPI_MAXIMUM_CLOCK_IN_MHZ)) { + return false; + } } + return true; } - return true; + return false; } static bool hal_spi_is_attr_valid(spi_bus_t bus, const hal_spi_attr_t *attr, const hal_spi_extra_attr_t *extra_attr) @@ -101,7 +122,7 @@ static bool hal_spi_is_attr_valid(spi_bus_t bus, const hal_spi_attr_t *attr, con if (attr->slave_num > spi_porting_max_slave_select_get(bus) + 1) { return false; } - if (hal_spi_is_attr_freq_valid(attr->freq_mhz, spi_frame_format) != true) { + if (hal_spi_is_attr_freq_valid(attr, spi_frame_format) != true) { return false; } } @@ -167,12 +188,22 @@ static void hal_spi_init_config_spi_frame_format(spi_bus_t bus, hal_spi_frame_fo } } -static void hal_spi_init_config_freq(spi_bus_t bus, uint32_t bus_clk, uint32_t clk_in_mhz) +static void hal_spi_init_config_freq(spi_bus_t bus, const hal_spi_attr_t *attr) { - uint32_t clk_div; - clk_div = (uint32_t)(bus_clk / spi_mhz_to_hz(clk_in_mhz)); - if (clk_div < SPI_MINUMUM_CLK_DIV) { - clk_div = SPI_MINUMUM_CLK_DIV; + uint32_t clk_div = SPI_MINUMUM_CLK_DIV; +#ifdef CONFIG_SPI_SUPPORT_HZ + if (attr->freq_hz != 0) { + clk_div = (uint32_t)(attr->bus_clk / attr->freq_hz); + if (clk_div < SPI_MINUMUM_CLK_DIV) { + clk_div = SPI_MINUMUM_CLK_DIV; + } + } +#endif + if (attr->freq_mhz != 0) { + clk_div = (uint32_t)(attr->bus_clk / spi_mhz_to_hz(attr->freq_mhz)); + if (clk_div < SPI_MINUMUM_CLK_DIV) { + clk_div = SPI_MINUMUM_CLK_DIV; + } } hal_spi_v100_baudr_set_sckdv(bus, clk_div); @@ -211,7 +242,7 @@ static bool hal_spi_init_config(spi_bus_t bus, const hal_spi_attr_t *attr, const /* Config slave info and freq in master mode. */ if (attr->is_slave == 0) { hal_spi_v100_ser_set_ser(bus, (attr->slave_num == 0) ? 0 : bit(attr->slave_num - 1)); - hal_spi_init_config_freq(bus, attr->bus_clk, attr->freq_mhz); + hal_spi_init_config_freq(bus, attr); if ((hal_spi_frame_format_t)attr->spi_frame_format == HAL_SPI_FRAME_FORMAT_QUAD) { hal_spi_config_qspi(bus, &extra_attr->qspi_param); } @@ -514,7 +545,7 @@ static errcode_t hal_spi_ctrl_set_attr(spi_bus_t bus, hal_spi_ctrl_id_t id, uint /* Config slave info and freq in master mode. */ if (attr->is_slave == 0) { hal_spi_v100_ser_set_ser(bus, (attr->slave_num == 0) ? 0 : bit(attr->slave_num - 1)); - hal_spi_init_config_freq(bus, attr->bus_clk, attr->freq_mhz); + hal_spi_init_config_freq(bus, attr); } /* Config slave select toggle enable. */ -- 2.17.1