From e4178d342e04fbfb71a5b07e107643c109bb833a Mon Sep 17 00:00:00 2001
From: penglei <1624952103@qq.com>
Date: Mon, 3 Nov 2025 14:32:42 +0800
Subject: [PATCH] =?utf8?q?=E5=BB=B6=E9=95=BF=E9=9B=B7=E9=B8=9FDPU=E8=B6=85?=
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---
 code/sdk/middleware/services/gpu/drv/dpu/isr/dpu_isr.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/code/sdk/middleware/services/gpu/drv/dpu/isr/dpu_isr.c b/code/sdk/middleware/services/gpu/drv/dpu/isr/dpu_isr.c
index 1c4e63918..e8214dae5 100644
--- a/code/sdk/middleware/services/gpu/drv/dpu/isr/dpu_isr.c
+++ b/code/sdk/middleware/services/gpu/drv/dpu/isr/dpu_isr.c
@@ -7,7 +7,7 @@
 #include "drv_gfx_port.h"
 #include "dpu_dfx.h"
 #include "dpu_hal.h"
-#include "pm.h"
+#include "pm.h"
 
 typedef struct {
     osal_spinlock isr_lock;
@@ -204,7 +204,11 @@ td_s32 dpu_wait_all_finish(td_void)
 #ifndef GPU_SUPPORT_VIDEO_MODE
     unsigned long flag = 0;
     dpu_dfx_info *dfx_info = dpu_dfx_get_info();
+#ifdef BOARD_LEINIAO
+    const td_u32 wait_time = 1000;
+#else
     const td_u32 wait_time = 200;
+#endif
     td_u32 cnt = 0;
     static td_u32 dpu_timeout_cnt = 0;
 
-- 
2.17.1