\r
calendar_regs_t *g_calendar_reg = SSB_CALENDAR_BASE_ADDR;\r
\r
-#if 0\r
+#if 1\r
static uint64_t uapi_ulp_systick_get_count(void)\r
{\r
uint64_t count = 0;\r
count |= (uint64_t)readw(ULP_SYSTICK_VAL1) << 16U;\r
count |= (uint64_t)readw(ULP_SYSTICK_VAL0);\r
writew(ULP_LOCK_REG, 0x0);\r
+ PRINT("[ULP_SYSTICK] uapi_ulp_systick_get_count: count=0x%016llx dec=%llu\r\n",\r
+ (unsigned long long)count, (unsigned long long)count);\r
osal_irq_restore(irq_sts);\r
return count;\r
}\r
\r
uint64_t uapi_ulp_systick_get_count(void)\r
{\r
+ #define ULP_SYSTICK_GET_DELAY_US 60UL\r
uint64_t count = 0;\r
- static uint64_t s_last_count = 0;\r
- uint16_t v0 = readw(ULP_SYSTICK_VAL0);\r
- uint16_t v1 = readw(ULP_SYSTICK_VAL1);\r
- uint16_t v2 = readw(ULP_SYSTICK_VAL2);\r
- uint16_t v3 = readw(ULP_SYSTICK_VAL3);\r
-\r
- count = ((uint64_t)v3 << 48U) |\r
- ((uint64_t)v2 << 32U) |\r
- ((uint64_t)v1 << 16U) |\r
- ((uint64_t)v0);\r
-\r
- PRINT("[ULP_CNT][drv ] v3=0x%04x v2=0x%04x v1=0x%04x v0=0x%04x count=0x%016llx (%llu)\r\n",\r
- v3, v2, v1, v0, (unsigned long long)count, (unsigned long long)count);\r
-\r
- if (s_last_count != 0 && count < s_last_count) {\r
- PRINT("[ULP_CNT][WARN][drv ] rollback! last=0x%016llx now=0x%016llx\r\n",\r
- (unsigned long long)s_last_count, (unsigned long long)count);\r
- }\r
- s_last_count = count;\r
-\r
+ unsigned int irq_sts = osal_irq_lock();\r
+ \r
+ uint64_t before = readw(0x5702c510);\r
+ before = before | 0x01;\r
+ writew(0x5702c510,before); \r
+ // writew(ULP_LOCK_REG, 0x1);\r
+\r
+ uapi_tcxo_delay_us(ULP_SYSTICK_GET_DELAY_US);\r
+\r
+ count = (uint64_t)readw(ULP_SYSTICK_VAL3) << 48U;\r
+ count |= (uint64_t)readw(ULP_SYSTICK_VAL2) << 32U;\r
+ count |= (uint64_t)readw(ULP_SYSTICK_VAL1) << 16U;\r
+ count |= (uint64_t)readw(ULP_SYSTICK_VAL0);\r
+ writew(0x5702c510, 0x0);\r
+ PRINT("[ULP_SYSTICK] uapi_ulp_systick_get_count: count=0x%016llx dec=%llu\r\n",\r
+ (unsigned long long)count, (unsigned long long)count);\r
+ osal_irq_restore(irq_sts);\r
return count;\r
}\r
\r