middleware文件夹下services文件夹下gpu文件夹合并提交

diff --git a/code/sdk/middleware/services/gpu/api/rm/brandy-auto-ota-cli/libgfx_rm.a b/code/sdk/middleware/services/gpu/api/rm/brandy-auto-ota-cli/libgfx_rm.a
index 8ba42a5..cf2f437 100644 (file)
Binary files a/code/sdk/middleware/services/gpu/api/rm/brandy-auto-ota-cli/libgfx_rm.a and b/code/sdk/middleware/services/gpu/api/rm/brandy-auto-ota-cli/libgfx_rm.a differ

diff --git a/code/sdk/middleware/services/gpu/api/rm/brandy-auto-ota-ser/libgfx_rm.a b/code/sdk/middleware/services/gpu/api/rm/brandy-auto-ota-ser/libgfx_rm.a
index bfc3f2c..c384ab0 100644 (file)
Binary files a/code/sdk/middleware/services/gpu/api/rm/brandy-auto-ota-ser/libgfx_rm.a and b/code/sdk/middleware/services/gpu/api/rm/brandy-auto-ota-ser/libgfx_rm.a differ

diff --git a/code/sdk/middleware/services/gpu/api/rm/brandy-native-js-r/libgfx_rm.a b/code/sdk/middleware/services/gpu/api/rm/brandy-native-js-r/libgfx_rm.a
index fbc8006..a731301 100644 (file)
Binary files a/code/sdk/middleware/services/gpu/api/rm/brandy-native-js-r/libgfx_rm.a and b/code/sdk/middleware/services/gpu/api/rm/brandy-native-js-r/libgfx_rm.a differ

diff --git a/code/sdk/middleware/services/gpu/api/rm/brandy-native-js/libgfx_rm.a b/code/sdk/middleware/services/gpu/api/rm/brandy-native-js/libgfx_rm.a
index 441cef8..7337ef0 100644 (file)
Binary files a/code/sdk/middleware/services/gpu/api/rm/brandy-native-js/libgfx_rm.a and b/code/sdk/middleware/services/gpu/api/rm/brandy-native-js/libgfx_rm.a differ

diff --git a/code/sdk/middleware/services/gpu/api/rm/brandy-target1-r/libgfx_rm.a b/code/sdk/middleware/services/gpu/api/rm/brandy-target1-r/libgfx_rm.a
index c98fc14..a24f28a 100644 (file)
Binary files a/code/sdk/middleware/services/gpu/api/rm/brandy-target1-r/libgfx_rm.a and b/code/sdk/middleware/services/gpu/api/rm/brandy-target1-r/libgfx_rm.a differ

diff --git a/code/sdk/middleware/services/gpu/api/rm/brandy-target1/libgfx_rm.a b/code/sdk/middleware/services/gpu/api/rm/brandy-target1/libgfx_rm.a
index 3e905a2..57524a6 100644 (file)
Binary files a/code/sdk/middleware/services/gpu/api/rm/brandy-target1/libgfx_rm.a and b/code/sdk/middleware/services/gpu/api/rm/brandy-target1/libgfx_rm.a differ

diff --git a/code/sdk/middleware/services/gpu/api/rm/brandy-target3-r/libgfx_rm.a b/code/sdk/middleware/services/gpu/api/rm/brandy-target3-r/libgfx_rm.a
index 941acdb..0058fbb 100644 (file)
Binary files a/code/sdk/middleware/services/gpu/api/rm/brandy-target3-r/libgfx_rm.a and b/code/sdk/middleware/services/gpu/api/rm/brandy-target3-r/libgfx_rm.a differ

diff --git a/code/sdk/middleware/services/gpu/api/rm/brandy-target3/libgfx_rm.a b/code/sdk/middleware/services/gpu/api/rm/brandy-target3/libgfx_rm.a
index c0b0c1a..3e1cbf2 100644 (file)
Binary files a/code/sdk/middleware/services/gpu/api/rm/brandy-target3/libgfx_rm.a and b/code/sdk/middleware/services/gpu/api/rm/brandy-target3/libgfx_rm.a differ

diff --git a/code/sdk/middleware/services/gpu/api/rm/brandy-target4-r/libgfx_rm.a b/code/sdk/middleware/services/gpu/api/rm/brandy-target4-r/libgfx_rm.a
index 788bded..1a7ac64 100644 (file)
Binary files a/code/sdk/middleware/services/gpu/api/rm/brandy-target4-r/libgfx_rm.a and b/code/sdk/middleware/services/gpu/api/rm/brandy-target4-r/libgfx_rm.a differ

diff --git a/code/sdk/middleware/services/gpu/api/rm/brandy-target4/libgfx_rm.a b/code/sdk/middleware/services/gpu/api/rm/brandy-target4/libgfx_rm.a
index e2b31fd..071b1c1 100644 (file)
Binary files a/code/sdk/middleware/services/gpu/api/rm/brandy-target4/libgfx_rm.a and b/code/sdk/middleware/services/gpu/api/rm/brandy-target4/libgfx_rm.a differ

diff --git a/code/sdk/middleware/services/gpu/api/rm/brandy-target5-r/libgfx_rm.a b/code/sdk/middleware/services/gpu/api/rm/brandy-target5-r/libgfx_rm.a
index 082b3da..01b0f58 100644 (file)
Binary files a/code/sdk/middleware/services/gpu/api/rm/brandy-target5-r/libgfx_rm.a and b/code/sdk/middleware/services/gpu/api/rm/brandy-target5-r/libgfx_rm.a differ

diff --git a/code/sdk/middleware/services/gpu/api/rm/brandy-target5/libgfx_rm.a b/code/sdk/middleware/services/gpu/api/rm/brandy-target5/libgfx_rm.a
index aef687e..d55faab 100644 (file)
Binary files a/code/sdk/middleware/services/gpu/api/rm/brandy-target5/libgfx_rm.a and b/code/sdk/middleware/services/gpu/api/rm/brandy-target5/libgfx_rm.a differ

diff --git a/code/sdk/middleware/services/gpu/api/rm/brandy-xts/libgfx_rm.a b/code/sdk/middleware/services/gpu/api/rm/brandy-xts/libgfx_rm.a
index 73a22fc..a1b8c43 100644 (file)
Binary files a/code/sdk/middleware/services/gpu/api/rm/brandy-xts/libgfx_rm.a and b/code/sdk/middleware/services/gpu/api/rm/brandy-xts/libgfx_rm.a differ

diff --git a/code/sdk/middleware/services/gpu/api/rm/testsuite-brandy-sdk/libgfx_rm.a b/code/sdk/middleware/services/gpu/api/rm/testsuite-brandy-sdk/libgfx_rm.a
index 9e1b022..f845fbe 100644 (file)
Binary files a/code/sdk/middleware/services/gpu/api/rm/testsuite-brandy-sdk/libgfx_rm.a and b/code/sdk/middleware/services/gpu/api/rm/testsuite-brandy-sdk/libgfx_rm.a differ

diff --git a/code/sdk/middleware/services/gpu/drv/comm/CMakeLists.txt b/code/sdk/middleware/services/gpu/drv/comm/CMakeLists.txt
index f15ddbc..200abab 100644 (file)
--- a/code/sdk/middleware/services/gpu/drv/comm/CMakeLists.txt
+++ b/code/sdk/middleware/services/gpu/drv/comm/CMakeLists.txt
@@ -2,6 +2,12 @@
 # @brief    cmake file
 # Copyright (c) @CompanyNameMagicTag 2022-2022. All rights reserved.
 #===============================================================================
+set(
+    gpu_mem_drv_list
+        ${CMAKE_CURRENT_SOURCE_DIR}/gpu_mem_config.c
+)
+set(GPU_SRC_LIST "${GPU_SRC_LIST}" "${gpu_mem_drv_list}" CACHE INTERNAL "platform src obj list" FORCE)
+
 set(
     drv_comm_header_list
         ${CMAKE_CURRENT_SOURCE_DIR}

diff --git a/code/sdk/middleware/services/gpu/drv/comm/gpu_mem_config.c b/code/sdk/middleware/services/gpu/drv/comm/gpu_mem_config.c
new file mode 100644 (file)
index 0000000..5afce42
--- /dev/null
+++ b/code/sdk/middleware/services/gpu/drv/comm/gpu_mem_config.c
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) @CompanyNameMagicTag 2024-2024. All rights reserved.
+ * Description : gpu sram config file
+ */
+
+#include "gpu_mem_config.h"
+
+td_u32 gpu_mem_get_cmd_size(td_void)
+{
+    return GPU_SRAM_CMD_SIZE;
+}

diff --git a/code/sdk/middleware/services/gpu/drv/comm/gpu_mem_config.h b/code/sdk/middleware/services/gpu/drv/comm/gpu_mem_config.h
index 7022494..1147a0f 100644 (file)
--- a/code/sdk/middleware/services/gpu/drv/comm/gpu_mem_config.h
+++ b/code/sdk/middleware/services/gpu/drv/comm/gpu_mem_config.h
@@ -6,6 +6,7 @@
 #ifndef COMM_GPU_MEM_CONFIG_H
 #define COMM_GPU_MEM_CONFIG_H
 
+#include "td_base.h"
 #include "psram.h"
 
 #ifdef __cplusplus
@@ -27,6 +28,7 @@ extern "C" {
 #define GPU_REG_LUT_ADDR    0x603E0000
 #define GPU_REG_LUT_SIZE    0x3FFF
 
+#ifdef SUPPORT_GPU_GMMU
 #define GPU_SRAM_PRE_SIZE   (1 * 1024) /* 1K for vau ip tmp dcmp */
 #define GPU_SRAM_PRE_ADDR   (GPU_SRAM_END + 1 - GPU_SRAM_PRE_SIZE) /* 0x6039FC00 ~ 0x6039FFFF */
 
@@ -40,6 +42,23 @@ extern "C" {
 
 #define GPU_PSRAM_SIZE      (PSRAM_DISP_VAU_NODE_LENGTH)
 #define GPU_PSRAM_ADDR      (PSRAM_DISP_VAU_NODE_ADDR)
+#else
+#define GPU_SRAM_PRE_SIZE   (1 * 1024) /* 1K for vau ip tmp dcmp */
+#define GPU_SRAM_PRE_ADDR   (GPU_SRAM_END + 1 - GPU_SRAM_PRE_SIZE)   /* 0x6039FC00 ~ 0x6039FFFF */
+
+#define GPU_SRAM_NODE_SIZE  (57 * 1024) /* 57K for node/handle */
+#define GPU_SRAM_NODE_ADDR  (GPU_SRAM_PRE_ADDR - GPU_SRAM_NODE_SIZE) /* 0x60391800 ~ 0x6039FC00 */
+
+#define GPU_SRAM_CMD_SIZE   (GPU_SRAM_PRE_SIZE + GPU_SRAM_NODE_SIZE)
+
+#define GPU_SRAM_DRAW_SIZE  (256 * 1024) /* 256K for cmd/data */
+#define GPU_SRAM_DRAW_ADDR  (PSRAM_DISP_VAU_NODE_ADDR) /* PSRAM */
+
+#define GPU_PSRAM_SIZE      (PSRAM_DISP_VAU_NODE_LENGTH - GPU_SRAM_DRAW_SIZE)
+#define GPU_PSRAM_ADDR      (GPU_SRAM_DRAW_ADDR + GPU_SRAM_DRAW_SIZE)
+#endif
+
+td_u32 gpu_mem_get_cmd_size(td_void);
 
 #ifdef __cplusplus
 #if __cplusplus

diff --git a/code/sdk/middleware/services/gpu/drv/dpu/disp/dpu_disp.c b/code/sdk/middleware/services/gpu/drv/dpu/disp/dpu_disp.c
index 5f487bc..e573bd6 100644 (file)
--- a/code/sdk/middleware/services/gpu/drv/dpu/disp/dpu_disp.c
+++ b/code/sdk/middleware/services/gpu/drv/dpu/disp/dpu_disp.c
@@ -8,8 +8,8 @@
 #include "dpu_clock.h"\r
 #include "lcd_bus.h"\r
 \r
-#define DPU_VTHD_POS_SETTING 10\r
-#define DPU_VTHD_POS_FINISH  90\r
+#define DPU_VTHD_PERCENT_10  10\r
+#define DPU_VTHD_PERCENT_90  90\r
 #define DPU_VTHD_PERCENT_100 100\r
 \r
 static dpu_disp_info g_dpu_disp_info = { 0 };\r
@@ -70,18 +70,25 @@ static td_s32 disp_get_panel_timing(const ext_rect *update_rect, dpu_disp_timing
 \r
 static td_void disp_set_interrupt_thd(dpu_disp_timing *timing)\r
 {\r
+#ifdef GPU_SUPPORT_VIDEO_MODE\r
+    td_u32 vtotal = timing->vact + timing->vbb + timing->vfb;\r
+    td_u32 vthd_percent_90 = vtotal * DPU_VTHD_PERCENT_90 / DPU_VTHD_PERCENT_100;\r
+\r
+    dpu_hal_disp_set_int_thd(DPU_DISP_INT_TYPE_SETTING, vthd_percent_90);\r
+#else\r
     td_u32 setting_thd;\r
     td_u32 finish_thd;\r
     td_u32 reserved_thd;\r
     td_u32 vtotal = timing->vact + timing->vbb + timing->vfb;\r
 \r
-    setting_thd  = vtotal * DPU_VTHD_POS_SETTING / DPU_VTHD_PERCENT_100;\r
+    setting_thd  = vtotal * DPU_VTHD_PERCENT_10 / DPU_VTHD_PERCENT_100;\r
     finish_thd   = vtotal - 2; /* 2:line */\r
     reserved_thd = timing->vbb + timing->vfb + 2; /* 2:line */\r
 \r
     dpu_hal_disp_set_int_thd(DPU_DISP_INT_TYPE_SETTING, setting_thd);\r
     dpu_hal_disp_set_int_thd(DPU_DISP_INT_TYPE_FINISH, finish_thd);\r
     dpu_hal_disp_set_int_thd(DPU_DISP_INT_TYPE_RESERVE, reserved_thd);\r
+#endif\r
 }\r
 \r
 static td_s32 disp_config_timing(td_void)\r
@@ -122,7 +129,12 @@ static td_void disp_set_cbm_default_priority(td_void)
 \r
 static td_void disp_set_isr_enable(td_bool enable)\r
 {\r
+#ifdef GPU_SUPPORT_VIDEO_MODE\r
+    dpu_hal_disp_set_dhd0_te_mode(0);      /* set dpu work video mode */\r
+    dpu_hal_disp_set_int_enable(DPU_DISP_INT_TYPE_SETTING, enable);\r
+#else\r
     dpu_hal_disp_set_dhd0_te_mode(enable); /* set dpu work te mode */\r
+#endif\r
     dpu_hal_disp_set_int_enable(DPU_DISP_INT_TYPE_LOWBAND, enable);\r
     dpu_hal_disp_set_int_enable(DPU_DISP_INT_TYPE_BUS_ERR, enable);\r
     dpu_hal_disp_set_int_enable(DPU_DISP_INT_TYPE_FRM_DONE, enable);\r

diff --git a/code/sdk/middleware/services/gpu/drv/dpu/hal/dpu_hal_crg.c b/code/sdk/middleware/services/gpu/drv/dpu/hal/dpu_hal_crg.c
index aa1282e..2fc9273 100644 (file)
--- a/code/sdk/middleware/services/gpu/drv/dpu/hal/dpu_hal_crg.c
+++ b/code/sdk/middleware/services/gpu/drv/dpu/hal/dpu_hal_crg.c
@@ -67,7 +67,11 @@ td_void dpu_crg_set_vedio_mclk_div_ctl(td_bool mclk_cken)
     /* bit[26]:enable, bit[25:13]:div_denom,  bit[12:0]:div_num */
     volatile u_vedio_crg_mclk_div_ctl mclk_div_ctl;
     uapi_reg_read(CRG_VEDIO_CRG_MCLK_DIV_CTL, mclk_div_ctl.u32);
+#ifdef GPU_SUPPORT_VIDEO_MODE
+    mclk_div_ctl.bits.dpu_mclk_div  = 0x412600C; /* 147M * 12/147 = 12M */
+#else
     mclk_div_ctl.bits.dpu_mclk_div  = 0x4126014; /* 147M * 20/147 = 20M */
+#endif
     mclk_div_ctl.bits.dpu_mclk_cken = mclk_cken;
     uapi_reg_write(CRG_VEDIO_CRG_MCLK_DIV_CTL, mclk_div_ctl.u32);
 }

diff --git a/code/sdk/middleware/services/gpu/drv/dpu/intf/drv_dpu_intf.c b/code/sdk/middleware/services/gpu/drv/dpu/intf/drv_dpu_intf.c
index 0fd0888..eec012c 100644 (file)
--- a/code/sdk/middleware/services/gpu/drv/dpu/intf/drv_dpu_intf.c
+++ b/code/sdk/middleware/services/gpu/drv/dpu/intf/drv_dpu_intf.c
@@ -233,14 +233,17 @@ td_s32 uapi_dpu_module_init(void)
     if (ret != EXT_SUCCESS) {\r
         dpu_disp_deinit();\r
         dpu_isr_deinit();\r
-        dpu_hal_init();\r
+        dpu_hal_deinit();\r
         dpu_err("dpu_layer_init fail, ret=%#x!", ret);\r
         return ret;\r
     }\r
 \r
     ret = dpu_register_device();\r
     if (ret != EXT_SUCCESS) {\r
-        uapi_dpu_module_exit();\r
+        dpu_layer_deinit();\r
+        dpu_disp_deinit();\r
+        dpu_isr_deinit();\r
+        dpu_hal_deinit();\r
         dpu_err("dpu_register_device failed, ret=%#x!", ret);\r
         return ret;\r
     }\r

diff --git a/code/sdk/middleware/services/gpu/drv/dpu/isr/dpu_isr.c b/code/sdk/middleware/services/gpu/drv/dpu/isr/dpu_isr.c
index 8aaac9b..1c4e639 100644 (file)
--- a/code/sdk/middleware/services/gpu/drv/dpu/isr/dpu_isr.c
+++ b/code/sdk/middleware/services/gpu/drv/dpu/isr/dpu_isr.c
@@ -39,6 +39,11 @@ static td_void isr_disp_main(td_u32 param)
     if ((int_type & DPU_DISP_INT_TYPE_BUS_ERR) == DPU_DISP_INT_TYPE_BUS_ERR) {\r
         dfx_info->bus_err_cnt++;\r
     }\r
+#ifdef GPU_SUPPORT_VIDEO_MODE\r
+    if ((int_type & DPU_DISP_INT_TYPE_SETTING) == DPU_DISP_INT_TYPE_SETTING) {\r
+        g_dpu_isr_info.finish_done = 1;\r
+    }\r
+#endif\r
     if ((int_type & DPU_DISP_INT_TYPE_TE_INT) == DPU_DISP_INT_TYPE_TE_INT) {\r
         dpu_dfx_get_time_us(&cur_time_us);\r
         dfx_info->te_cost_us = (cur_time_us - dfx_info->last_te_time_us);\r
@@ -49,7 +54,11 @@ static td_void isr_disp_main(td_u32 param)
     }\r
 \r
     if ((int_type & DPU_DISP_INT_TYPE_FRM_DONE) == DPU_DISP_INT_TYPE_FRM_DONE) {\r
+#ifdef GPU_SUPPORT_VIDEO_MODE\r
+        g_dpu_isr_info.finish_done = 0;\r
+#else\r
         g_dpu_isr_info.finish_done = 1;\r
+#endif\r
         dfx_info->frm_done_cnt++;\r
         dfx_info->frm_done_total++;\r
         uapi_pm_remove_sleep_veto(PM_ID_DPU);\r
@@ -192,6 +201,7 @@ td_void dpu_isr_clear_finish_flag(void)
 \r
 td_s32 dpu_wait_all_finish(td_void)\r
 {\r
+#ifndef GPU_SUPPORT_VIDEO_MODE\r
     unsigned long flag = 0;\r
     dpu_dfx_info *dfx_info = dpu_dfx_get_info();\r
     const td_u32 wait_time = 200;\r
@@ -216,5 +226,6 @@ td_s32 dpu_wait_all_finish(td_void)
         dpu_timeout_cnt++;\r
         return EXT_FAILURE;\r
     }\r
+#endif\r
     return EXT_SUCCESS;\r
 }\r

diff --git a/code/sdk/middleware/services/gpu/drv/dpu/layer/dpu_layer.c b/code/sdk/middleware/services/gpu/drv/dpu/layer/dpu_layer.c
index d431017..599467c 100644 (file)
--- a/code/sdk/middleware/services/gpu/drv/dpu/layer/dpu_layer.c
+++ b/code/sdk/middleware/services/gpu/drv/dpu/layer/dpu_layer.c
@@ -285,7 +285,14 @@ static td_void dpu_layer_calculate_gp_region(ext_rect *gp_region)
 {\r
     td_u32 screen_width  = dpu_disp_get_srceen_width();\r
     td_u32 screen_height = dpu_disp_get_srceen_height();\r
+#ifdef GPU_SUPPORT_VIDEO_MODE\r
+    gp_region->x = 0;\r
+    gp_region->y = 0;\r
+    gp_region->width  = (td_u32)screen_width;\r
+    gp_region->height = (td_u32)screen_height;\r
 \r
+    return;\r
+#endif\r
     td_s32 end_x = 0;\r
     td_s32 end_y = 0;\r
     td_s32 start_x = (td_s32)screen_width;\r
@@ -380,6 +387,12 @@ static td_void dpu_layer_revise_update_region(dpu_layer_dev *layer_dev, const ex
 \r
 static td_s32 dpu_check_update_rect(dpu_layer_run_info *run_info, const drv_dpu_surface *surface)\r
 {\r
+#ifdef GPU_SUPPORT_VIDEO_MODE\r
+    run_info->update_region.x = 0;\r
+    run_info->update_region.y = 0;\r
+    run_info->update_region.width  = surface->width;\r
+    run_info->update_region.height = surface->height;\r
+#else\r
     if (surface->update_rect == TD_NULL) {\r
         run_info->update_region.x = 0;\r
         run_info->update_region.y = 0;\r
@@ -413,7 +426,7 @@ static td_s32 dpu_check_update_rect(dpu_layer_run_info *run_info, const drv_dpu_
             run_info->update_region.width = run_info->width;\r
         }\r
     }\r
-\r
+#endif\r
     return EXT_SUCCESS;\r
 }\r
 \r
@@ -861,6 +874,43 @@ td_s32 dpu_layer_get_colorkey(drv_dpu_layer_id layer_id, drv_dpu_colorkey *color
 \r
 td_s32 dpu_layer_refresh(void)\r
 {\r
+#ifdef GPU_SUPPORT_VIDEO_MODE\r
+    td_u32 layer_id;\r
+    unsigned long flag = 0;\r
+    ext_rect gp_region = { 0 };\r
+\r
+    td_u32 time_start = 0;\r
+    td_u32 time_end = 0;\r
+    dpu_dfx_info *dfx_info = dpu_dfx_get_info();\r
+\r
+    dfx_info->refresh_cnt++;\r
+    dfx_info->refresh_total++;\r
+    dpu_dfx_get_time_us(&time_start);\r
+\r
+    dpu_disp_wait_frame_done();\r
+    dpu_layer_calculate_gp_region(&gp_region);\r
+\r
+    for (layer_id = (td_u32)DRV_DPU_LAYER_ID1; layer_id <= (td_u32)DRV_DPU_MAX_LAYER_ID; layer_id++) {\r
+        if (g_dpu_layer_dev[layer_id] == TD_NULL) {\r
+            continue;\r
+        }\r
+\r
+        if ((g_dpu_layer_dev[layer_id]->is_create != TD_TRUE) ||\r
+            (g_dpu_layer_dev[layer_id]->update_flag != TD_TRUE)) {\r
+            continue;\r
+        }\r
+\r
+        osal_spin_lock_irqsave(&g_dpu_layer_dev[layer_id]->layer_lock, &flag);\r
+        dpu_layer_revise_update_region(g_dpu_layer_dev[layer_id], &gp_region);\r
+        dpu_layer_config_update(g_dpu_layer_dev[layer_id]);\r
+        g_dpu_layer_dev[layer_id]->update_flag = TD_FALSE;\r
+        osal_spin_unlock_irqrestore(&g_dpu_layer_dev[layer_id]->layer_lock, &flag);\r
+    }\r
+    dpu_disp_set_chnl_reg_up();\r
+\r
+    dpu_dfx_get_time_us(&time_end);\r
+    dfx_info->refresh_intf_cost = (td_float)(time_end - time_start);\r
+#else\r
     td_u32 layer_id;\r
     unsigned long flag = 0;\r
     ext_rect gp_region = { 0 };\r
@@ -919,7 +969,7 @@ td_s32 dpu_layer_refresh(void)
 \r
     dpu_dfx_get_time_us(&time_end);\r
     dfx_info->refresh_intf_cost = (td_float)(time_end - time_start);\r
-\r
+#endif\r
     return EXT_SUCCESS;\r
 }\r
 \r

diff --git a/code/sdk/middleware/services/gpu/drv/vau/dfx/vau_dfx.c b/code/sdk/middleware/services/gpu/drv/vau/dfx/vau_dfx.c
index e1dd983..da73e64 100644 (file)
--- a/code/sdk/middleware/services/gpu/drv/vau/dfx/vau_dfx.c
+++ b/code/sdk/middleware/services/gpu/drv/vau/dfx/vau_dfx.c
@@ -9,6 +9,7 @@
 #include "vau_list.h"\r
 #include "vau_mem.h"\r
 #include "drv_vau.h"\r
+#include "vau_hal_apb.h"\r
 \r
 /*-------------------------------- macro define -------------------------------------------*/\r
 \r
@@ -40,6 +41,17 @@ static td_u32 g_vau_debug_mask = 0x0;
 vau_dfx_info g_vau_dfx_info = {0};\r
 \r
 /*-------------------------------- func release -------------------------------------------*/\r
+td_s32 vau_dfx_print(int argc, const char *argv[])\r
+{\r
+    if (argc < 1) {\r
+        vau_print("usage: vau_print 0/1\n");\r
+        return EXT_FAILURE;\r
+    }\r
+\r
+    g_vau_dfx_info.print_en = (td_bool)strtoul(argv[0], TD_NULL, 10); /* 10: index */\r
+\r
+    return EXT_SUCCESS;\r
+}\r
 \r
 static td_void vau_dfx_print_node_info(void)\r
 {\r
@@ -69,6 +81,13 @@ td_s32 vau_dfx_proc_read(int argc, const char *argv[])
     vau_dfx_print_node_info();\r
     vau_dfx_print_func_info();\r
     vau_osi_list_proc();\r
+\r
+    if (g_vau_dfx_info.print_en != TD_TRUE) {\r
+        return EXT_SUCCESS;\r
+    }\r
+\r
+    vau_hal_apb_print_all_reg();\r
+\r
     return EXT_SUCCESS;\r
 }\r
 \r

diff --git a/code/sdk/middleware/services/gpu/drv/vau/dfx/vau_dfx.h b/code/sdk/middleware/services/gpu/drv/vau/dfx/vau_dfx.h
index 63ca89e..450bcfa 100644 (file)
--- a/code/sdk/middleware/services/gpu/drv/vau/dfx/vau_dfx.h
+++ b/code/sdk/middleware/services/gpu/drv/vau/dfx/vau_dfx.h
@@ -173,6 +173,7 @@ typedef struct {
     dfx_mem_info mem_info;\r
     dfx_func_info func_info;\r
     td_bool is_print_vau_api;\r
+    td_bool print_en;\r
 } vau_dfx_info;\r
 \r
 /*-------------------------------- func declares ------------------------------------------*/\r
@@ -187,6 +188,7 @@ static inline td_void vau_dfx_get_time_us(td_u32 *time_us)
 vau_dfx_info *vau_dfx_get_info(td_void);\r
 td_bool vau_dfx_check_mask(td_u32 mask);\r
 td_void vau_dfx_print_path(const td_u8 *cmds, const td_float *datas, td_u16 cmd_num, td_u16 data_num);\r
+td_s32 vau_dfx_print(int argc, const char *argv[]);\r
 td_s32 vau_dfx_proc_read(int argc, const char *argv[]);\r
 td_s32 vau_dfx_proc_write(int argc, const char *argv[]);\r
 \r

diff --git a/code/sdk/middleware/services/gpu/drv/vau/hal/vau_hal_apb.c b/code/sdk/middleware/services/gpu/drv/vau/hal/vau_hal_apb.c
index 61c63ec..514ea9a 100644 (file)
--- a/code/sdk/middleware/services/gpu/drv/vau/hal/vau_hal_apb.c
+++ b/code/sdk/middleware/services/gpu/drv/vau/hal/vau_hal_apb.c
@@ -286,9 +286,8 @@ td_void vau_hal_apb_sram_ctrl(td_bool lp_en)
     return;\r
 }\r
 \r
-td_void vau_hal_apb_print_reg(td_u32 base, td_u32 start, td_u32 end)\r
+static td_void vau_print_reg(td_u32 base, td_u32 start, td_u32 end)\r
 {\r
-    volatile td_u32 value;\r
     td_u32 size  = end - start;\r
     td_u32 *addr = (td_u32 *)(base + start);\r
 \r
@@ -296,7 +295,13 @@ td_void vau_hal_apb_print_reg(td_u32 base, td_u32 start, td_u32 end)
         vau_print("%04x:  %08x %08x %08x %08x\n", ((td_u32)addr + i * 16),         /* 16:index */\r
                   addr[i * 4], addr[i * 4 + 1], addr[i * 4 + 2], addr[i * 4 + 3]); /* 2,3,4:index */\r
     }\r
+}\r
+\r
+td_void vau_hal_apb_print_reg(td_u32 base, td_u32 start, td_u32 end)\r
+{\r
+    volatile td_u32 value;\r
 \r
+    vau_print_reg(base, start, end);\r
     uapi_reg_read(HAL_VAU_DRAW_PATH_CMD_ADDR, value);\r
     td_u8 *cmds = (td_u8 *)(uintptr_t)value;\r
     uapi_reg_read(HAL_VAU_DRAW_PATH_DATA_ADDR, value);\r
@@ -311,6 +316,11 @@ td_void vau_hal_apb_print_reg(td_u32 base, td_u32 start, td_u32 end)
 \r
 td_void vau_hal_apb_print_all_reg(td_void)\r
 {\r
-    vau_hal_apb_print_reg(HAL_VAU_REG_BASEADDR, 0, 0x40AC);\r
+    vau_print_reg(HAL_VAU_REG_BASEADDR, 0, 0x164); /* reg:0~0x164 */\r
+    vau_print_reg(HAL_VAU_REG_BASEADDR, 0x200, 0x260); /* reg:0x200~0x260 */\r
+    vau_print_reg(HAL_VAU_REG_BASEADDR, 0x500, 0x534); /* reg:0x500~0x534 */\r
+    vau_print_reg(HAL_VAU_REG_BASEADDR, 0xA00, 0xA60); /* reg:0xA00~0xA60 */\r
+    vau_hal_apb_print_reg(HAL_VAU_REG_BASEADDR, 0x4000, 0x40AC); /* reg:0x4000~0x40AC */\r
+\r
     return;\r
 }\r

diff --git a/code/sdk/middleware/services/gpu/drv/vau/intf/drv_vau_intf.c b/code/sdk/middleware/services/gpu/drv/vau/intf/drv_vau_intf.c
index 15a27a3..c8351f3 100644 (file)
--- a/code/sdk/middleware/services/gpu/drv/vau/intf/drv_vau_intf.c
+++ b/code/sdk/middleware/services/gpu/drv/vau/intf/drv_vau_intf.c
@@ -17,6 +17,7 @@
 #include "vau_handle.h"\r
 #include "drv_vau_struct.h"\r
 #include "drv_gmmu_intf.h"\r
+#include "pmp_config.h"\r
 \r
 #define DRV_VAU_IOCTL_CMD_NUM 20\r
 \r
@@ -71,7 +72,8 @@ td_s32 drv_vau_suspend(td_void *private_data)
     vau_dbg("vau suspend ok");\r
 \r
 #ifdef SUPPORT_GPU_GMMU\r
-        (td_void)drv_gmmu_suspend(NULL);\r
+    pmp_configure_gmmu_region(0);\r
+    (td_void)drv_gmmu_suspend(NULL);\r
 #endif\r
 \r
     return ret;\r
@@ -96,7 +98,8 @@ td_s32 drv_vau_resume(td_void *private_data)
     vau_dbg("vau resume ok");\r
 \r
 #ifdef SUPPORT_GPU_GMMU\r
-        (void)drv_gmmu_resume(NULL);\r
+    (void)drv_gmmu_resume(NULL);\r
+    pmp_configure_gmmu_region(1);\r
 #endif\r
 \r
     return EXT_SUCCESS;\r
@@ -235,6 +238,7 @@ td_s32 uapi_vau_module_init(void)
         vau_err("drv_gmmu_module_init failed, ret=%#x!", ret);\r
         return ret;\r
     }\r
+    pmp_configure_gmmu_region(1);\r
 #endif\r
     vau_ip_dcmp_tmp();\r
 \r
@@ -281,4 +285,7 @@ td_void uapi_vau_module_exit(void)
     vau_unregister_device();\r
     vau_list_deinit();\r
     vau_mem_deinit();\r
+#ifdef SUPPORT_GPU_GMMU\r
+    pmp_configure_gmmu_region(0);\r
+#endif\r
 }\r

diff --git a/code/sdk/middleware/services/gpu/drv/vau/list/vau_list.c b/code/sdk/middleware/services/gpu/drv/vau/list/vau_list.c
index 61e957f..3914df3 100644 (file)
--- a/code/sdk/middleware/services/gpu/drv/vau/list/vau_list.c
+++ b/code/sdk/middleware/services/gpu/drv/vau/list/vau_list.c
@@ -334,7 +334,7 @@ static td_void vau_list_timeout_resume(td_void)
                  (td_void *)DRV_VAU_TIMEOUT_DBG_ADDR, sizeof(g_vau_sw_job_list->dbg.timeout_reg)) != EOK) {
         vau_err("memcpy_s failed");
     }
-    if (g_vau_sw_job_list->dbg.software_timeout < 10) { /* 10:index */
+    if (g_vau_sw_job_list->dbg.software_timeout < 4) { /* 4:index */
         for (td_u32 i = 0; i < DRV_VAU_TIMEOUT_REG_SIZE / 4; i++) {   /* 4:index */
             vau_print("%04x:  %08x %08x %08x %08x\n", (i * 16),       /* 16:index */
                       g_vau_sw_job_list->dbg.timeout_reg[i * 4 + 0],  /* 4:index */
@@ -342,11 +342,10 @@ static td_void vau_list_timeout_resume(td_void)
                       g_vau_sw_job_list->dbg.timeout_reg[i * 4 + 2],  /* 4,2:index */
                       g_vau_sw_job_list->dbg.timeout_reg[i * 4 + 3]); /* 4,3:index */
         }
+        vau_mem_check_psram_addr();
+        vau_dfx_proc_read(0, TD_NULL);
     }
 
-    vau_mem_check_psram_addr();
-    vau_dfx_proc_read(0, TD_NULL);
-    vau_hal_apb_print_all_reg();
     if (!g_vau_sw_job_list->dbg.no_reset) {
         vau_hal_init();
     } else {