add_subdirectory_if_exist(sdio)
add_subdirectory_if_exist(security)
add_subdirectory_if_exist(security_unified)
+add_subdirectory_if_exist(security_unified/drv_hitls)
add_subdirectory_if_exist(spi)
add_subdirectory_if_exist(ssi)
add_subdirectory_if_exist(systick)
if (EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/source/CMakeLists.txt)
set(AUDI_PUBLIC_HEADER ${CMAKE_CURRENT_SOURCE_DIR}/include)
add_subdirectory(source)
-elseif(EXISTS ${BIN_DIR}/${PROJECT_CHIP_DIR}/libs/audio/CMakeLists.txt)
- set(PUBLIC_HEADER ${CMAKE_CURRENT_SOURCE_DIR}/include)
- add_subdirectory(${BIN_DIR}/${PROJECT_CHIP_DIR}/libs/audio audio)
else()
set(PUBLIC_HEADER ${CMAKE_CURRENT_SOURCE_DIR}/include)
set(AUDIO_LIST "audio_api" "audio_core" "audio_drv" "audio_sample" "audio_vendor")
string(APPEND SAP_BOARD "4")
endif()
- set(LIBRARY_OUTPUT_PATH ${BIN_DIR}/${CHIP}/libs/audio/${SAP_BOARD}_${APPLICATION}/${OS})
+ if(DEFINED CONFIG_LOAD_FROM_FS)
+ set(LIBRARY_OUTPUT_PATH ${BIN_DIR}/${CHIP}/libs/audio/${SAP_BOARD}_${APPLICATION}/${OS}/fs)
+ else()
+ set(LIBRARY_OUTPUT_PATH ${BIN_DIR}/${CHIP}/libs/audio/${SAP_BOARD}_${APPLICATION}/${OS})
+ endif()
foreach(COMPONENT ${COMPONENT_LIST})
set(COMPONENT_NAME ${COMPONENT})
if (NOT ${COMPONENT_NAME} IN_LIST TARGET_COMPONENT)
if("${CHIP}" STREQUAL "socmn1")\r
set(LIBRARY_OUTPUT_PATH ${BIN_DIR}/melody/libs/audio/${SAP_BOARD}_${APPLICATION}/${OS})\r
else()\r
- set(LIBRARY_OUTPUT_PATH ${BIN_DIR}/${CHIP}/libs/audio/${SAP_BOARD}_${APPLICATION}/${OS})\r
+ if(DEFINED CONFIG_LOAD_FROM_FS)\r
+ set(LIBRARY_OUTPUT_PATH ${BIN_DIR}/${CHIP}/libs/audio/${SAP_BOARD}_${APPLICATION}/${OS}/fs)\r
+ else()\r
+ set(LIBRARY_OUTPUT_PATH ${BIN_DIR}/${CHIP}/libs/audio/${SAP_BOARD}_${APPLICATION}/${OS})\r
+ endif()\r
endif()\r
\r
build_component()\r
string(APPEND SAP_BOARD "4")\r
if("${DSP_VERSION}" STREQUAL "ultra")\r
# Ultra version:: Switch audio config mak for brandy evb4. Must use 16M FLASH:\r
- if(NOT ("CFG_FLASH_SIZE=16" IN_LIST DEFINES))\r
- message(FATAL_ERROR "Must define CFG_FLASH_SIZE=16 when dsp version is ultra")\r
+ if(NOT ${CONFIG_NORFLASH_SIZE} STREQUAL "16")\r
+ message(FATAL_ERROR "Must define CONFIG_NORFLASH_SIZE=16 when dsp version is ultra")\r
endif()\r
elseif("${DSP_VERSION}" STREQUAL "mini")\r
# Mini version:: Switch audio config mak for brandy evb4 mini:\r
)\r
endif()\r
\r
-if("CFG_LOAD_FROM_FS" IN_LIST DEFINES)\r
+if(DEFINED CONFIG_LOAD_FROM_FS)\r
set(COMPONENT_SRC ${COMPONENT_SRC}\r
${CMAKE_CURRENT_SOURCE_DIR}/common/drv_overlay_load_from_file.c\r
)\r
ao_inst->ao_handle = ao_handle;
param->h_mod = ao_handle;
-#ifdef SAP_VENDOR_DRIVER_SUPPORT
- for (td_u32 i = 0; i < attr->port_num; ++i) {
- ret = drv_audio_vendor_init(attr->port_attr[i].out_port, attr->sample_rate, attr->bit_depth, attr->channels);
- if (ret != AUDIO_SUCCESS) {
- sap_err_log_h32(attr->port_attr[i].out_port);
- sap_err_log_fun(drv_audio_vendor_init, ret);
- }
- }
-#endif
-
audio_unused(cmd);
audio_unused(file);
return AUDIO_SUCCESS;
sap_err_log_h32(attr.port_attr[i].out_port);
sap_err_log_fun(drv_audio_vendor_set_aef_profile, ret);
}
+
+ ret = drv_audio_vendor_init(attr.port_attr[i].out_port, attr.sample_rate, attr.bit_depth, attr.channels);
+ if (ret != AUDIO_SUCCESS) {
+ sap_err_log_h32(attr.port_attr[i].out_port);
+ sap_err_log_fun(drv_audio_vendor_init, ret);
+ }
}
#endif
return ret;
}
+static td_s32 drv_overlay_clear_section(audio_lib_id type)
+{
+ td_s32 ret;
+
+ if (type == AUDIO_LIB_DSP0_APP || type == AUDIO_LIB_DSP1_APP) {
+ return AUDIO_SUCCESS;
+ }
+
+ ret = drv_msg_sys_clear_overlay_section(type);
+ if (ret != AUDIO_SUCCESS) {
+ sap_err_log_fun(drv_msg_sys_clear_overlay_section, ret);
+ return ret;
+ }
+
+ return AUDIO_SUCCESS;
+}
+
td_s32 drv_overlay_load_main_program(audio_core_id core_id)
{
td_s32 ret;
return ret;
}
+ ret = drv_overlay_clear_section(type);
+ if (ret != AUDIO_SUCCESS) {
+ sap_err_log_fun(drv_overlay_clear_section, ret);
+ return ret;
+ }
+
ret = overlay_load_elf(core_id, flip);
if (ret != AUDIO_SUCCESS) {
sap_err_log_fun(overlay_load_elf, ret);
#define LCD_BOE_454X454_SCREEN_ID 0x500\r
#define LCD_SH_240X296_SCREEN_ID 0x101\r
#define LCD_BOE_194X368_SCREEN_ID 0x4a00\r
+/* manufacturer id - driver version id - driver id (don't care for the moment) */\r
+#define LCD_ST7367_360X480_SCREEN_ID 0xFFFFFF\r
+\r
+const combo_dev_cfg_t g_panel_st7367_360x480_60_config = {\r
+ .devno = 0,\r
+ .lane_id = {0, -1},\r
+ .out_mode = OUT_MODE_DSI_VIDEO,\r
+ .out_format = OUT_FORMAT_RGB_24BIT,\r
+ .sync_info = {\r
+ .hsa_pixels = 2, // hsa 2 pixels\r
+ .hbp_pixels = 20, // hbp 20 pixels\r
+ .hact_pixels = 360, // hact 360 pixels\r
+ .hfp_pixels = 20, // hfp 20 pixels\r
+ .vsa_lines = 1, // vsa 1 lines\r
+ .vbp_lines = 6, // vbp 6 lines\r
+ .vact_lines = 480, // vact 480 lines\r
+ .vfp_lines = 6, // vfp 6 lines\r
+ },\r
+ .phy_data_rate = 288, // 288Mbps\r
+ .pixel_clk = 12000, // 12000KHz\r
+};\r
\r
/*\r
pixel_clk 需要大于 sync_info 中的（hsa+hbp+hact+hfp）* \r
{1, 2, {0xfe, 0x00}, 0},\r
{1, 2, {0x51, 0xff}, 0},\r
};\r
+\r
+/* init sequence for ST7367 360*480 lcd */\r
+const lcd_cmd_sequ g_st7367_360x480_screen_init_on[] = {\r
+ {1, 2, {0xF0, 0xC3}, 0},\r
+ {1, 2, {0xF0, 0x96}, 0},\r
+ {1, 2, {0xF0, 0xA5}, 0},\r
+ {1, 5, {0xC1, 0x11, 0x08, 0xAD, 0x13}, 0},\r
+ {1, 5, {0xC2, 0x11, 0x08, 0xAD, 0x13}, 0},\r
+ {1, 5, {0xC3, 0x22, 0x02, 0x44, 0x04}, 0},\r
+ {1, 5, {0xC4, 0x44, 0x04, 0x44, 0x04}, 0},\r
+ {1, 3, {0xC5, 0x4E, 0x80}, 0}, /* #VCOM 0.975 2025 4 28 */\r
+ {1, 2, {0xD6, 0x00}, 0},\r
+ {1, 2, {0xD7, 0x00}, 0},\r
+ {1, 15, {0xE0, 0xD0, 0x08, 0x0D, 0x0A, 0x08, 0x05, 0x35, 0x33, 0x4C, 0x08, 0x13, 0x14, 0x2D, 0x32}, 0},\r
+ {1, 15, {0xE1, 0xD0, 0x08, 0x0D, 0x0A, 0x08, 0x05, 0x35, 0x33, 0x4C, 0x08, 0x13, 0x14, 0x2D, 0x32}, 0},\r
+ {1, 15, {0xE5, 0x58, 0xF5, 0x66, 0x33, 0x22, 0x25, 0x10, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77}, 0},\r
+ {1, 15, {0xE6, 0x58, 0xF5, 0x66, 0x33, 0x22, 0x25, 0x10, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77}, 0},\r
+ {1, 7, {0xEC, 0x00, 0x55, 0x00, 0x00, 0x00, 0x08}, 0},\r
+ {1, 2, {0x36, 0x0C}, 0},\r
+ {1, 2, {0x3A, 0x07}, 0},\r
+ {1, 2, {0xB2, 0x09}, 0},\r
+ {1, 2, {0xB3, 0x01}, 0},\r
+ {1, 2, {0xB4, 0x01}, 0},\r
+ {1, 5, {0xB5, 0x00, 0x08, 0x00, 0x08}, 0},\r
+ {1, 3, {0xB6, 0xEF, 0x2C}, 0},\r
+ {1, 3, {0xA4, 0xC0, 0x63}, 0},\r
+ {1, 10, {0xA5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x2A, 0xBA, 0x02}, 0},\r
+ {1, 10, {0xA6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x2A, 0xBA, 0x02}, 0},\r
+ {1, 8, {0xBA, 0x58, 0x1A, 0x45, 0x02, 0x22, 0x01, 0x00}, 0}, /* #2025 5 9 Modify STV0 */\r
+ {1, 9, {0xBB, 0x00, 0x20, 0x00, 0x25, 0x83, 0x87, 0x18, 0x00}, 0},\r
+ {1, 9, {0xBC, 0x00, 0x24, 0x00, 0x25, 0x83, 0x87, 0x18, 0x00}, 0},\r
+ {1, 12, {0xBD, 0x21, 0x12, 0x99, 0xFF, 0x45, 0x36, 0x63, 0x54, 0xAB, 0xFF, 0x07}, 0},\r
+ {1, 2, {0xED, 0xC3}, 0},\r
+ {1, 4, {0xE4, 0x40, 0x0F, 0x2F}, 0},\r
+ {1, 2, {0x35, 0x00}, 0},\r
+ {1, 1, {0x21}, 0},\r
+ {1, 1, {0x11}, 120},\r
+ {1, 1, {0x29}, 120},\r
+ {1, 2, {0x35, 0x00}, 100},\r
+};\r
+\r
const lcd_cmd_sequ g_edo_502x410_screen_init_on[] = {\r
{1, 5, {0x2A, 0x00, 0x04, 0x01, 0x9d}, 0}, \r
{1, 5, {0x2B, 0x00, 0x00, 0x01, 0xf5}, 0}, \r
.cmd = g_common_cmd_brightness,\r
.cmd_cnt = array_size(g_common_cmd_brightness),\r
};\r
+\r
+const lcd_cmds_sequ g_st7367_360x480_screen_init_on_cmds = {\r
+ .cmd = g_st7367_360x480_screen_init_on,\r
+ .cmd_cnt = array_size(g_st7367_360x480_screen_init_on),\r
+};\r
+\r
const lcd_cmds_sequ g_edo_502x410_screen_init_on_cmds = {\r
.cmd = g_edo_502x410_screen_init_on,\r
.cmd_cnt = array_size(g_edo_502x410_screen_init_on),\r
\r
\r
const lcd_drv_cfg g_lcd_driver_ops[] = {\r
+ {\r
+ .bus_type = BUS_DISPLAY_MIPI,\r
+ .bus_cfg = &g_panel_st7367_360x480_60_config,\r
+ .x_start = 0,\r
+ .y_start = 0,\r
+ .fps = 60,\r
+ .lcd_id = LCD_ST7367_360X480_SCREEN_ID,\r
+ .display_on_cmds = &g_st7367_360x480_screen_init_on_cmds,\r
+ .display_off_cmds = &g_display_off_cmds,\r
+ .enter_idle_cmds = &g_idle_in_cmds,\r
+ .exit_idle_cmds = &g_idle_out_cmds,\r
+ .te_on_cmds = &g_te_on_cmds,\r
+ .te_off_cmds = &g_te_off_cmds,\r
+ .set_brightnes_cmds = &g_brightness_cmds,\r
+ .sleep_in_cmds = &g_sleep_in_cmds,\r
+ .sleep_out_cmds = &g_sleep_out_cmds,\r
+ .lcd_id_info.reg_addr = 0x04,\r
+ .lcd_id_info.read_len = 3,\r
+ },\r
{\r
.bus_type = BUS_DISPLAY_MIPI,\r
.bus_cfg = &g_panel_502x410_50_config,\r
#include "gpio.h"\r
#include "pinctrl_porting.h"\r
#include "product.h"\r
+#include "debug_print.h"\r
#include "pinctrl.h"\r
static void lcd_drv_power_on(void)\r
{\r
uapi_gpio_set_dir(VCI_LCD_GPIO, GPIO_DIRECTION_OUTPUT);\r
uapi_gpio_set_val(VCI_LCD_GPIO, GPIO_LEVEL_HIGH);\r
#endif\r
+\r
+#ifdef GPU_SUPPORT_VIDEO_MODE\r
+ /* Reset pin signal will turn opposite by the triode amplifier on Midea display board. */\r
+ uapi_gpio_set_dir(RESET_LCD_GPIO, GPIO_DIRECTION_OUTPUT);\r
+ uapi_gpio_set_val(RESET_LCD_GPIO, GPIO_LEVEL_LOW);\r
+ uapi_tcxo_delay_ms(100); /* delay 100 ms */\r
+\r
+ uapi_gpio_set_val(RESET_LCD_GPIO, GPIO_LEVEL_HIGH);\r
+ uapi_tcxo_delay_ms(100); /* delay 100 ms */\r
+\r
+ uapi_gpio_set_val(RESET_LCD_GPIO, GPIO_LEVEL_LOW);\r
+ uapi_tcxo_delay_ms(100); /* delay 100 ms */\r
+#else\r
uapi_gpio_set_dir(RESET_LCD_GPIO, GPIO_DIRECTION_OUTPUT);\r
\r
uapi_gpio_set_val(RESET_LCD_GPIO, GPIO_LEVEL_LOW);\r
\r
uapi_gpio_set_val(RESET_LCD_GPIO, GPIO_LEVEL_HIGH);\r
uapi_tcxo_delay_ms(10); /* delay 10 ms */\r
+#endif\r
}\r
+\r
#define USE_OUTPUT_CTL 1\r
static void lcd_drv_power_off(void)\r
{\r
int resetvalue = uapi_gpio_get_output_val(RESET_LCD_GPIO);\r
int lcd_envalue = uapi_gpio_get_output_val(VCI_LCD_GPIO);\r
printf("Output RESET_LCD_GPIO %d , VCI_LCD_GPIO %d\r\n",resetvalue,lcd_envalue);\r
+#else\r
+#ifdef GPU_SUPPORT_VIDEO_MODE\r
+ /* Reset pin signal will turn opposite by the triode amplifier on Midea display board. */\r
+ uapi_gpio_set_val(RESET_LCD_GPIO, GPIO_LEVEL_HIGH);\r
#else\r
uapi_gpio_set_val(RESET_LCD_GPIO, GPIO_LEVEL_LOW);\r
- uapi_gpio_set_dir(RESET_LCD_GPIO, GPIO_DIRECTION_INPUT); //ÉèÖóÉInput£¬ÊÇΪÁ˽â¾ö©µç £¿£¿\r
+#endif\r
+ uapi_gpio_set_dir(RESET_LCD_GPIO, GPIO_DIRECTION_INPUT); //���ó�Input����Ϊ�˽��©�� ����\r
uapi_pin_set_pull(RESET_LCD_GPIO, PIN_PULL_DOWN);\r
#ifndef QSPI_DISPLAY\r
uapi_gpio_set_val(VCI_LCD_GPIO, GPIO_LEVEL_LOW);\r
extern "C" {\r
#endif\r
\r
-#define MAX_DATA_LENGTH 5\r
+#define MAX_DATA_LENGTH 15\r
\r
typedef enum {\r
LCD_DISPLAY_OFF, /* LCD关闭显示 */\r
free_func:
sdio_delete_func(sc);
return (ret);
+}
+
+int sdio_acquire_bus(struct sdio_func *func)
+{
+ if (func == NULL || func->sc == NULL || func->sc->mmcbus == NULL) {
+ dprintf("sdio_acquire_bus fail!\n");
+ return (-1);
+ }
+ return MMCBR_ACQUIRE_HOST(device_get_parent(func->sc->mmcbus), func->sc->mmcbus);
+}
+
+int sdio_release_bus(struct sdio_func *func)
+{
+ if (func == NULL || func->sc == NULL || func->sc->mmcbus == NULL) {
+ dprintf("sdio_release_bus fail!\n");
+ return (-1);
+ }
+ return MMCBR_RELEASE_HOST(device_get_parent(func->sc->mmcbus), func->sc->mmcbus);
}
\ No newline at end of file
SDIOM_SEL_PERF_MODE, // 性能优先，两路mmc需求不一致选高的
SDIOM_SEL_MODE_MAX,
} sdiom_select_mode_t;
-uint8_t g_sdiom_sel_mode = SDIOM_SEL_LP_MODE;
+uint8_t g_sdiom_sel_mode = SDIOM_SEL_PERF_MODE;
uint32_t g_sdiom_cfg_clk[MAX_MMC_NUM] = {0, 0};
system_sdio_freq_t g_sdiom_mmc_sel[MAX_MMC_NUM] = {CLOCKS_SDIO_FREQ_MAX, CLOCKS_SDIO_FREQ_MAX};
return -ENODEV;
}
// 读CCCR寄存器
- for (addr = 0; addr < 0x10; addr++) {
+ for (addr = 0; addr < 0x16; addr++) {
byte = sdio_func0_read_byte(func, addr, &err);
dprintf("%s func0 address: 0x%x, result: 0x%x, err = %d\r\n", __FUNCTION__, addr, byte, err);
}
SDIOM_SRC_CLK_LOW_FREQ_VAL, SDIOM_SRC_CLK_FREQ_LVL_50M_VAL,
SDIOM_SRC_CLK_FREQ_LVL_64M_VAL, SDIOM_SRC_CLK_HIGH_FREQ_LVL_VAL
};
- *second_freq_div = 1;
+
+ if (freq_level == CLOCKS_SDIO_FREQ_H && cfg_clock <= SDIOM_SRC_CLK_FREQ_LVL_98M_VAL) {
+ *second_freq_div = 3; // 3：选PLL时钟频率经过3分频到98Mhz，二级分频才能满足低频要求，如400Khz的探卡频率
+ } else {
+ *second_freq_div = 1;
+ }
+
if (cfg_clock <= sdiom_freq_val[freq_level]) {
- *freq_div = sdiom_freq_val[freq_level] / cfg_clock;
+ *freq_div = sdiom_freq_val[freq_level] / (cfg_clock * (*second_freq_div));
if (freq_level == CLOCKS_SDIO_FREQ_32M || freq_level == CLOCKS_SDIO_FREQ_H) {
- if (sdiom_freq_val[freq_level] % cfg_clock != 0) { *freq_div += 1; }
+ if (sdiom_freq_val[freq_level] % (cfg_clock * (*second_freq_div)) != 0) { *freq_div += 1; }
}
} else {
*freq_div = 1;
system_sdio_freq_t freq_level;
g_sdiom_cfg_clk[sc->num] = cfg_clock;
+#ifdef CFG_DRIVERS_NANDFLASH // NANDFLASH + SDIO共存场景, 固定选高频
+ freq_level = CLOCKS_SDIO_FREQ_H;
+#else
if (cfg_clock <= SDIOM_SRC_CLK_LOW_FREQ_VAL) {
freq_level = CLOCKS_SDIO_FREQ_32M;
-#ifndef CFG_DRIVERS_NANDFLASH
} else if (cfg_clock <= SDIOM_SRC_CLK_FREQ_LVL_50M_VAL) {
freq_level = CLOCKS_SDIO_FREQ_50M;
} else if (cfg_clock == SDIOM_SRC_CLK_FREQ_LVL_64M_VAL) {
} else {
freq_level = CLOCKS_SDIO_FREQ_H;
}
-#else // NANDFLASH + SDIO共存场景, 固定选高频
- } else {
- freq_level = CLOCKS_SDIO_FREQ_H;
- }
#endif
+
/* 记录下原始的选择 */
g_sdiom_mmc_sel[sc->num] = freq_level;
// data_addr is not 8bit aligned, we need copy to sha_context.buffer, then calculate\r
errno_t ret;\r
uint32_t cal_times = sha_get_no_aligned_cal_times(len, sha_context->hash_type);\r
- for (uint8_t i = 0; i < cal_times; i++) {\r
+ for (uint32_t i = 0; i < cal_times; i++) {\r
ret = memcpy_s(&sha_context->buffer.bytes[0], sha_context->block_len,\r
(uint8_t*)(uintptr_t)(data_addr + (i * sha_context->block_len)),\r
sha_context->block_len);\r
--- /dev/null
+#===============================================================================
+# @brief cmake file
+# Copyright (c) CompanyNameMagicTag 2022-2022. All rights reserved.
+#===============================================================================
+set(COMPONENT_NAME "drv_security_unified")
+
+if("romboot" IN_LIST APPLICATION)
+ set(CRYPTO_BUILD_ENV "boot")
+ set(SOURCES
+ # ROM API
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_rom_cipher.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/crypto_drv_common.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/init/cfbb/crypto_curve_param.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/ecc/drv_pke_ecc_verify.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_ecdsa.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_pke_weak_func.c
+ )
+ if(DEFINED CONFIG_PKE_SUPPORT_ECC_VERIFY)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/ecc/drv_pke_ecc_verify.c")
+ endif()
+
+ set(PUBLIC_DEFINES
+ # need to change to related to kconfig.
+ -DCRYPTO_ERROR_ENV=6 # NOOS
+ -DCRYPTO_ROM_ENABLE
+ )
+elseif ("flashboot" IN_LIST APPLICATION)
+ set(SOURCES
+ # flashboot API
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_flashboot_cipher.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/crypto_drv_common.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_km/drv_keyslot.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_km/drv_klad.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_fapc/drv_fapc.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/init/cfbb/crypto_curve_param.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/sm2/drv_pke_sm2_verify.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_ecdsa.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_pke_weak_func.c
+ )
+ if(DEFINED CONFIG_PKE_SUPPORT_SM2_VERIFY)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/sm2/drv_pke_sm2_verify.c")
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/sm2/drv_pke_sm2_dsa_hash.c")
+ endif()
+ # ROM API
+ if(DEFINED CONFIG_FLASH_BOOT_SUPPORT_ROM_API)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/rom_drv_api/hal_rom_table.c")
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/rom_drv_api/drv_rom_table.c")
+ else()
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_rom_cipher.c")
+ endif()
+
+ set(PUBLIC_DEFINES
+ # need to change to related to kconfig.
+ -DCRYPTO_ERROR_ENV=6 # NOOS
+ -DPKE_SM2_SUPPORT
+ )
+elseif("BUILD_APPLICATION_STANDARD" IN_LIST DEFINES)
+ set(CRYPTO_BUILD_ENV "os")
+ set(SOURCES
+ # SYMC
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/drv_symc.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/drv_symc_mac_hard.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/crypto_drv_common.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/drv_hash.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/drv_pbkdf2_hard.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/drv_trng.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_fapc/drv_fapc.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_km/drv_keyslot.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_km/drv_klad.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/init/cfbb/crypto_curve_param.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_ecdsa.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_pke_weak_func.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_hash.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_init.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_pke.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_symc.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_trng.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_km.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/sl_common.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/trng.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/cipher.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/pke.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/km.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/security_init.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/mbedtls_harden_adapt/mbedtls_harden_adapt.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/init/cfbb/os/crypto_drv_init.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/init/cfbb/os/crypto_drv_irq.c
+ )
+ if(DEFINED CONFIG_PKE_SUPPORT_EDWARD)
+ # ed25519 algorithm function realization.
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_eddsa.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_RSA)
+ # rsa algorithm function realization.
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_rsa.c")
+ endif()
+ # outter API
+ if(DEFINED CONFIG_PKE_SUPPORT_ECC_SIGN)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/ecc/drv_pke_ecc_sign.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_ECC_VERIFY)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/ecc/drv_pke_ecc_verify.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_SM2_SIGN)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/sm2/drv_pke_sm2_sign.c")
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/sm2/drv_pke_sm2_dsa_hash.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_SM2_VERIFY)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/sm2/drv_pke_sm2_verify.c")
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/sm2/drv_pke_sm2_dsa_hash.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_SM2_CRYPTO)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/sm2/drv_pke_sm2_crypto.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_ECC_ECDH)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_ecc_ecdh.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_ECC_GEN_KEY)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_ecc_gen_key.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_ECC_CAL)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_ecc_cal.c")
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_pke_ecc_cal.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_BIG_NUMBER)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_cal.c")
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_pke_cal.c")
+ endif()
+
+ set(PUBLIC_DEFINES
+ -DSM4_CFB_OFB_SUPPORT
+ -DCRYPTO_CTR_NON_ALIGN_SUPPORT
+ -DCRYPTO_SYMC_ADDR_NOT_ALIGN_SUPPORT
+ # -DCRYPTO_CCM_TRACE_ENABLE # Debug for ccm trace
+ # -DCRYPTO_DRV_FUNC_TRACE_ENABLE # Debug for drv func trace
+ # -DCONFIG_CRYPTO_PERF_STATISTICS
+ )
+ if("__LITEOS__" IN_LIST DEFINES)
+ list(APPEND PUBLIC_DEFINES -DCRYPTO_ERROR_ENV=4) # LiteOS
+ elseif("__FREERTOS__" IN_LIST DEFINES)
+ list(APPEND PUBLIC_DEFINES -DCRYPTO_ERROR_ENV=7) # FreeRTOS
+ elseif("__ALIOS__" IN_LIST DEFINES)
+ list(APPEND PUBLIC_DEFINES -DCRYPTO_ERROR_ENV=8) # alios
+ endif()
+
+elseif("UT_TEST" IN_LIST DEFINES)
+ set(SOURCES
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/crypto_drv_common.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/drv_hash.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/drv_pbkdf2_hard.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/drv_symc.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/drv_symc_mac_hard.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/drv_trng.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_fapc/drv_fapc.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_km/drv_keyslot.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_km/drv_klad.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/ecc/drv_pke_ecc_sign.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/ecc/drv_pke_ecc_verify.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/sm2/drv_pke_sm2_sign.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/sm2/drv_pke_sm2_verify.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/sm2/drv_pke_sm2_dsa_hash.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/sm2/drv_pke_sm2_crypto.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_cal.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_ecc_cal.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_ecc_ecdh.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_ecc_gen_key.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_ecdsa.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_eddsa.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_rsa.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_hash.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_init.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_pke.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_pke_cal.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_pke_ecc_cal.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_symc.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_trng.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_km.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/sl_common.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/trng.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/cipher.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/pke.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/km.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/security_init.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/init/cfbb/ut/crypto_drv_init.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/init/cfbb/crypto_curve_param.c
+ )
+
+ set(PUBLIC_DEFINES
+ -DSM4_CFB_OFB_SUPPORT
+ # -DCRYPTO_SYMC_ADDR_NOT_ALIGN_SUPPORT
+ # -DCRYPTO_CCM_TRACE_ENABLE # Debug for ccm trace
+ # -DCRYPTO_DRV_FUNC_TRACE_ENABLE # Debug for drv func trace
+ # -DCONFIG_CRYPTO_PERF_STATISTICS
+ )
+
+ list(APPEND PUBLIC_DEFINES -DCRYPTO_ERROR_ENV=1) # Linux
+elseif("FUZZ_TEST" IN_LIST DEFINES)
+ set(SOURCES
+ # SYMC
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/drv_symc.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/drv_symc_mac_hard.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/crypto_drv_common.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/drv_hash.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/drv_pbkdf2_hard.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/drv_trng.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_fapc/drv_fapc.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_km/drv_keyslot.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_km/drv_klad.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/init/cfbb/crypto_curve_param.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_ecdsa.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_pke_weak_func.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_hash.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_init.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_pke.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_symc.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_trng.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_km.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/sl_common.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/trng.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/cipher.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/pke.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/km.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/security_init.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/mbedtls_harden_adapt/mbedtls_harden_adapt.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/init/cfbb/ut/crypto_drv_init.c
+ )
+ if(DEFINED CONFIG_PKE_SUPPORT_EDWARD)
+ # ed25519 algorithm function realization.
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_eddsa.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_RSA)
+ # rsa algorithm function realization.
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_rsa.c")
+ endif()
+ # outter API
+ if(DEFINED CONFIG_PKE_SUPPORT_ECC_SIGN)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/ecc/drv_pke_ecc_sign.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_ECC_VERIFY)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/ecc/drv_pke_ecc_verify.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_SM2_SIGN)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/sm2/drv_pke_sm2_sign.c")
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/sm2/drv_pke_sm2_dsa_hash.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_SM2_VERIFY)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/sm2/drv_pke_sm2_verify.c")
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/sm2/drv_pke_sm2_dsa_hash.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_SM2_CRYPTO)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/sm2/drv_pke_sm2_crypto.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_ECC_ECDH)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_ecc_ecdh.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_ECC_GEN_KEY)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_ecc_gen_key.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_ECC_CAL)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_ecc_cal.c")
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_pke_ecc_cal.c")
+ endif()
+ if(DEFINED CONFIG_PKE_SUPPORT_BIG_NUMBER)
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/drv_pke_cal.c")
+ list(APPEND SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/kapi/source/kapi_pke_cal.c")
+ endif()
+
+ set(PUBLIC_DEFINES
+ -DSM4_CFB_OFB_SUPPORT
+ -DCRYPTO_CTR_NON_ALIGN_SUPPORT
+ -DCRYPTO_SYMC_ADDR_NOT_ALIGN_SUPPORT
+ )
+
+ list(APPEND PUBLIC_DEFINES -DCRYPTO_ERROR_ENV=1) # Linux
+endif()
+
+set(PRIVATE_HEADER
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_pke_v5/common
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_include
+ ${CMAKE_CURRENT_SOURCE_DIR}/kapi/include
+ ${CMAKE_CURRENT_SOURCE_DIR}/init/cfbb/ut
+ ${CMAKE_CURRENT_SOURCE_DIR}/mbedtls_harden_adapt
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_cipher/drv_code/fmea
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_km/include
+ ${CMAKE_CURRENT_SOURCE_DIR}/init/cfbb
+ ${CMAKE_CURRENT_SOURCE_DIR}/init/cfbb/${CRYPTO_BUILD_ENV}
+ ${CMAKE_CURRENT_SOURCE_DIR}/rom_drv_api
+)
+
+set(PUBLIC_HEADER
+
+)
+
+set(PRIVATE_DEFINES
+)
+
+# use this when you want to add ccflags like -include xxx
+set(COMPONENT_PUBLIC_CCFLAGS
+)
+
+set(COMPONENT_CCFLAGS
+)
+
+set(WHOLE_LINK
+ true
+)
+
+set(MAIN_COMPONENT
+ false
+)
+
+build_component()
--- /dev/null
+#===============================================================================\r
+# @brief cmake make file\r
+# Copyright (c) @CompanyNameMagicTag 2022-2022. All rights reserved.\r
+#===============================================================================\r
+set(COMPONENT_NAME "drv_hitls")\r
+\r
+set(SOURCES\r
+ ${CMAKE_CURRENT_SOURCE_DIR}/common/crypto_drv_common.c\r
+ ${CMAKE_CURRENT_SOURCE_DIR}/crypto_osal/crypto_osal_lib.c\r
+\r
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_code/hash/drv_hkdf_soft.c\r
+ ${CMAKE_CURRENT_SOURCE_DIR}/drv_code/symc/drv_symc_aead_gcm_soft.c\r
+\r
+ # service layer\r
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/cipher_init.c\r
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/cipher_aead.c\r
+ ${CMAKE_CURRENT_SOURCE_DIR}/service_layer/hkdf.c\r
+ ${ROOT_DIR}/drivers/drivers/driver/security_unified/service_layer/sl_common.c\r
+\r
+ # HiTLS\r
+ ${ROOT_DIR}/open_source/HiTLS/bsl/sal/src/sal_mem.c\r
+ ${ROOT_DIR}/open_source/HiTLS/bsl/log/src/log.c\r
+ ${ROOT_DIR}/open_source/HiTLS/bsl/err/src/err.c\r
+ ${ROOT_DIR}/open_source/HiTLS/bsl/sal/src/sal_threadlock.c\r
+ ${ROOT_DIR}/open_source/HiTLS/bsl/err/src/avl.c\r
+\r
+ # HiTLS HKDF\r
+ ${ROOT_DIR}/open_source/HiTLS/crypto/hkdf/src/hkdf.c\r
+ ${ROOT_DIR}/open_source/HiTLS/crypto/hmac/src/hmac.c\r
+ ${ROOT_DIR}/open_source/HiTLS/crypto/sha2/src/noasm_sha256.c\r
+ ${ROOT_DIR}/open_source/HiTLS/crypto/sha2/src/sha2_256.c\r
+\r
+ # HiTLS GCM\r
+ ${ROOT_DIR}/open_source/HiTLS/crypto/modes/src/modes_gcm.c\r
+ ${ROOT_DIR}/open_source/HiTLS/crypto/modes/src/noasm_ghash.c\r
+\r
+ ${ROOT_DIR}/open_source/HiTLS/crypto/aes/src/crypt_aes.c\r
+)\r
+\r
+set(PRIVATE_HEADER\r
+ ${CMAKE_CURRENT_SOURCE_DIR}/include/drv_include\r
+ ${ROOT_DIR}/include/driver/security_unified\r
+\r
+ ${CMAKE_CURRENT_SOURCE_DIR}/crypto_osal\r
+ ${CMAKE_CURRENT_SOURCE_DIR}/common\r
+ ${ROOT_DIR}/drivers/drivers/driver/security_unified/service_layer\r
+ ${CMAKE_CURRENT_SOURCE_DIR}/include/common_include\r
+\r
+ # HiTLS\r
+ ${ROOT_DIR}/open_source/HiTLS/include/bsl\r
+ ${ROOT_DIR}/open_source/HiTLS/include/crypto\r
+ ${ROOT_DIR}/open_source/HiTLS/crypto/include\r
+ ${ROOT_DIR}/open_source/HiTLS/bsl/include\r
+ ${ROOT_DIR}/open_source/HiTLS/bsl/err/include\r
+ ${ROOT_DIR}/open_source/HiTLS/bsl/sal/include\r
+ ${ROOT_DIR}/open_source/HiTLS/bsl/log/include\r
+\r
+ # HiTLS HKDF\r
+ ${ROOT_DIR}/open_source/HiTLS/crypto/hkdf/include\r
+ ${ROOT_DIR}/open_source/HiTLS/crypto/hmac/include\r
+ ${ROOT_DIR}/open_source/HiTLS/crypto/sha2/include\r
+\r
+ # HiTLS GCM\r
+ ${ROOT_DIR}/open_source/HiTLS/crypto/modes/include\r
+ ${ROOT_DIR}/open_source/HiTLS/crypto/aes/include\r
+)\r
+\r
+set(PUBLIC_HEADER\r
+\r
+)\r
+\r
+set(PRIVATE_DEFINES\r
+ __FILENAME__=""\r
+)\r
+\r
+set(PUBLIC_DEFINES\r
+)\r
+\r
+set(COMPONENT_CCFLAGS\r
+)\r
+\r
+set(WHOLE_LINK\r
+ true\r
+)\r
+build_component()\r
--- /dev/null
+/**
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n
+ *
+ * Description: Provides IPC source \n
+ * Author: @CompanyNameTag \n
+ * History: \n
+ * 2025-04-18, Create file. \n
+ */
+#include "crypto_drv_common.h"
+
+/* crypto dump functions. */
+#define MAX_DUMP_LENGHT (256)
+#define BYTES_IN_ONE_LINE (16)
+#ifndef KERN_CONT
+#define KERN_CONT
+#endif
+void crypto_dump_data(const char *name, const td_u8 *data, td_u32 data_len)
+{
+ td_u32 i;
+ td_u32 dump_len = data_len;
+ crypto_unused(name);
+ crypto_unused(data);
+ if (data == TD_NULL) {
+ crypto_log_err("data is NULL\n");
+ return;
+ }
+
+ crypto_print("%s:\n", name);
+ dump_len = data_len > MAX_DUMP_LENGHT ? MAX_DUMP_LENGHT : data_len;
+ for (i = 0; i < dump_len; i++) {
+ crypto_print(KERN_CONT"%02x ", data[i]);
+ if ((i + 1) % BYTES_IN_ONE_LINE == 0) {
+ crypto_print("\n");
+ }
+ }
+ if (dump_len % BYTES_IN_ONE_LINE != 0) {
+ crypto_print("\n");
+ }
+}
+
+void crypto_dump_phys_addr(const char *name, const td_u64 phys_addr, td_u32 data_len)
+{
+ td_u8 *buffer = crypto_ioremap_nocache(phys_addr, data_len);
+ if (buffer == TD_NULL) {
+ crypto_log_err("crypto_ioremap_nocache failed, buffer is NULL\n");
+ return;
+ }
+ crypto_dump_data(name, buffer, data_len);
+ crypto_iounmap(buffer, data_len);
+ crypto_unused(phys_addr);
+}
+
+td_u32 crypto_get_value_by_index(const crypto_table_item *table, td_u32 table_size,
+ td_u32 index, td_u32 *value)
+{
+ const crypto_table_item *item = TD_NULL;
+ td_u32 i;
+
+ crypto_chk_return(table == TD_NULL, TD_FAILURE, "table is NULL\n");
+ crypto_chk_return(value == TD_NULL, TD_FAILURE, "value is NULL\n");
+
+ for (i = 0; i < table_size; i++) {
+ item = &table[i];
+ if (item->index == index) {
+ *value = item->value;
+ return TD_SUCCESS;
+ }
+ }
+ crypto_log_err("Invalid Index!\n");
+ return TD_FAILURE;
+}
+
+td_u32 crypto_get_index_by_value(const crypto_table_item *table, td_u32 table_size,
+ td_u32 value, td_u32 *index)
+{
+ const crypto_table_item *item = TD_NULL;
+ td_u32 i;
+
+ crypto_chk_return(table == TD_NULL, TD_FAILURE, "table is NULL\n");
+ crypto_chk_return(index == TD_NULL, TD_FAILURE, "index is NULL\n");
+
+ for (i = 0; i < table_size; i++) {
+ item = &table[i];
+ if (item->value == value) {
+ *index = item->index;
+ return TD_SUCCESS;
+ }
+ }
+ crypto_log_err("Invalid Value!\n");
+ return TD_FAILURE;
+}
+
+void crypto_reg_item_dump(const td_char *name, const reg_item_t *reg_item_table, td_u32 item_size,
+ reg_read_func read_func)
+{
+ td_u32 i;
+ crypto_unused(name);
+ crypto_unused(reg_item_table);
+ crypto_unused(read_func);
+
+ crypto_print("========== %s reg table:==========\n", name);
+ for (i = 0; i < item_size; i++) {
+ crypto_print("%s is 0x%x\n", reg_item_table[i].name, read_func(reg_item_table[i].offset));
+ }
+}
\ No newline at end of file
--- /dev/null
+/*
+ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2022-2023. All rights reserved.
+ */
+
+#ifndef CRYPTO_DRV_COMMON_H
+#define CRYPTO_DRV_COMMON_H
+
+#include "crypto_type.h"
+#include "crypto_osal_lib.h"
+#include "crypto_log.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+typedef struct {
+ const td_char *name;
+ td_u32 offset;
+} reg_item_t;
+
+typedef td_u32 (*reg_read_func)(td_u32 offset);
+
+void crypto_reg_item_dump(const td_char *name, const reg_item_t *reg_item_table, td_u32 item_size,
+ reg_read_func read_func);
+
+typedef enum {
+ TIMER_ID_0 = 0,
+ TIMER_ID_1,
+ TIMER_ID_2,
+ TIMER_ID_3,
+ TIMER_ID_4,
+ TIMER_ID_5,
+ TIMER_ID_6,
+ TIMER_ID_7,
+ TIMER_ID_8,
+ TIMER_ID_9,
+} crypto_timer_id;
+#if defined(CONFIG_CRYPTO_PERF_STATISTICS)
+td_void crypto_timer_start(td_u32 timer_id, const td_char *name);
+
+td_u64 crypto_timer_end(td_u32 timer_id, const td_char *item_name);
+
+td_void crypto_timer_print(td_u32 timer_id);
+
+td_void crypto_timer_print_all(td_void);
+#else
+#define crypto_timer_start(...)
+#define crypto_timer_end(...)
+#define crypto_timer_print(...)
+#define crypto_timer_print_all(...)
+#endif
+
+typedef struct {
+ td_u32 index;
+ td_u32 value;
+} crypto_table_item;
+
+td_u32 crypto_get_value_by_index(const crypto_table_item *table, td_u32 table_size,
+ td_u32 index, td_u32 *value);
+td_u32 crypto_get_index_by_value(const crypto_table_item *table, td_u32 table_size,
+ td_u32 value, td_u32 *index);
+
+unsigned int crypto_align(unsigned int original_length, unsigned int aligned_length);
+
+void crypto_dump_data(const char *name, const td_u8 *data, td_u32 data_len);
+
+void crypto_dump_phys_addr(const char *name, const td_u64 phys_addr, td_u32 data_len);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif
\ No newline at end of file
--- /dev/null
+/**
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n
+ *
+ * Description: Provides IPC source \n
+ * Author: @CompanyNameTag \n
+ * History: \n
+ * 2025-04-18, Create file. \n
+ */
+#ifndef CRYPTO_LOG_H
+#define CRYPTO_LOG_H
+
+#if !defined(CRYPTO_LOG_DEF)
+
+#ifndef crypto_print
+#error "crypto_print is not set!"
+#endif
+
+#ifndef CRYPTO_LOG_LEVEL
+#define CRYPTO_LOG_LEVEL 0
+#endif
+
+#define crypto_log_fmt(LOG_LEVEL_LABEL, fmt, ...) \
+ crypto_print("[%s:%d]" LOG_LEVEL_LABEL ": " fmt, __func__, __LINE__, ##__VA_ARGS__)
+
+#if defined(CRYPTO_LOG_LEVEL) && (CRYPTO_LOG_LEVEL == 0)
+#define crypto_log_err(fmt, ...) crypto_log_fmt("ERROR", fmt, ##__VA_ARGS__)
+#define crypto_log_warn(fmt, ...)
+#define crypto_log_notice(fmt, ...)
+#define crypto_log_dbg(fmt, ...)
+#define crypto_log_trace(fmt, ...)
+#elif defined(CRYPTO_LOG_LEVEL) && (CRYPTO_LOG_LEVEL == 1)
+#define crypto_log_err(fmt, ...) crypto_log_fmt("ERROR", fmt, ##__VA_ARGS__)
+#define crypto_log_warn(fmt, ...) crypto_log_fmt("WARN:", fmt, ##__VA_ARGS__)
+#define crypto_log_notice(fmt, ...)
+#define crypto_log_dbg(fmt, ...)
+#define crypto_log_trace(fmt, ...)
+#elif defined(CRYPTO_LOG_LEVEL) && (CRYPTO_LOG_LEVEL == 2)
+#define crypto_log_err(fmt, ...) crypto_log_fmt("ERROR", fmt, ##__VA_ARGS__)
+#define crypto_log_warn(fmt, ...) crypto_log_fmt("WARN:", fmt, ##__VA_ARGS__)
+#define crypto_log_notice(fmt, ...) crypto_log_fmt("NOTICE", fmt, ##__VA_ARGS__)
+#define crypto_log_dbg(fmt, ...)
+#define crypto_log_trace(fmt, ...)
+#elif defined(CRYPTO_LOG_LEVEL) && (CRYPTO_LOG_LEVEL == 3)
+#define crypto_log_err(fmt, ...) crypto_log_fmt("ERROR", fmt, ##__VA_ARGS__)
+#define crypto_log_warn(fmt, ...) crypto_log_fmt("WARN:", fmt, ##__VA_ARGS__)
+#define crypto_log_notice(fmt, ...) crypto_log_fmt("NOTICE", fmt, ##__VA_ARGS__)
+#define crypto_log_dbg(fmt, ...) crypto_log_fmt("DBG", fmt, ##__VA_ARGS__)
+#define crypto_log_trace(fmt, ...)
+#elif defined(CRYPTO_LOG_LEVEL) && (CRYPTO_LOG_LEVEL == 4)
+#define crypto_log_err(fmt, ...) crypto_log_fmt("ERROR", fmt, ##__VA_ARGS__)
+#define crypto_log_warn(fmt, ...) crypto_log_fmt("WARN:", fmt, ##__VA_ARGS__)
+#define crypto_log_notice(fmt, ...) crypto_log_fmt("NOTICE", fmt, ##__VA_ARGS__)
+#define crypto_log_dbg(fmt, ...) crypto_log_fmt("DBG", fmt, ##__VA_ARGS__)
+#define crypto_log_trace(fmt, ...) crypto_log_fmt("TRACE", fmt, ##__VA_ARGS__)
+#endif
+
+#endif
+#endif
\ No newline at end of file
--- /dev/null
+/**
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n
+ *
+ * Description: Provides IPC source \n
+ * Author: @CompanyNameTag \n
+ * History: \n
+ * 2025-04-18, Create file. \n
+ */
+#include "crypto_osal_lib.h"
+
+#include "bsl_sal.h"
+#include "drv_symc_aead.h"
+
+static void *inner_malloc(uint32_t size)
+{
+ return malloc(size);
+}
+
+static void inner_free(void *addr)
+{
+ free(addr);
+}
+
+void crypto_drv_init(void)
+{
+ BSL_SAL_MemCallback mem_callback;
+ mem_callback.pfMalloc = inner_malloc;
+ mem_callback.pfFree = inner_free;
+
+ (void)BSL_SAL_RegMemCallback(&mem_callback);
+}
\ No newline at end of file
--- /dev/null
+/**
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n
+ *
+ * Description: Provides IPC source \n
+ * Author: @CompanyNameTag \n
+ * History: \n
+ * 2025-04-18, Create file. \n
+ */
+#ifndef CRYPTO_OSAL_LIB_H
+#define CRYPTO_OSAL_LIB_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "securec.h"
+
+#define crypto_print(...)
+
+#define crypto_ioremap_nocache(phys_addr, size) (void *)(uintptr_t)(phys_addr)
+#define crypto_iounmap(...)
+
+#endif
\ No newline at end of file
--- /dev/null
+/**
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n
+ *
+ * Description: Provides IPC source \n
+ * Author: @CompanyNameTag \n
+ * History: \n
+ * 2025-04-18, Create file. \n
+ */
+#include "drv_hkdf.h"
+
+#include "crypt_hmac.h"
+#include "crypt_hkdf.h"
+#include "crypt_errno.h"
+#include "crypt_sha2.h"
+
+#include "crypto_drv_common.h"
+
+static const EAL_MacMethod g_mac_hmac_method = {
+ .initCtx = (MacInitCtx)CRYPT_HMAC_InitCtx,
+ .init = (MacInit)CRYPT_HMAC_Init,
+ .update = (MacUpdate)CRYPT_HMAC_Update,
+ .final = (MacFinal)CRYPT_HMAC_Final,
+ .deinit = (MacDeinit)CRYPT_HMAC_Deinit,
+ .deinitCtx = (MacDeinitCtx)CRYPT_HMAC_DeinitCtx,
+ .reinit = (MacReinit)CRYPT_HMAC_Reinit,
+ .getLen = (MacGetMacLen)CRYPT_HMAC_GetMacLen,
+ .ctxSize = sizeof(CRYPT_HMAC_Ctx)
+};
+
+static const EAL_MdMethod g_md_sha256_meth = {
+ .blockSize = 64, // 64: block size for sha256
+ .mdSize = 32, // 32: result size for sha256
+ .ctxSize = sizeof(CRYPT_SHA2_256_Ctx),
+ .init = (MdInit)CRYPT_SHA2_256_Init,
+ .update = (MdUpdate)CRYPT_SHA2_256_Update,
+ .final = (MdFinal)CRYPT_SHA2_256_Final,
+ .deinit = (MdDeinit)CRYPT_SHA2_256_Deinit,
+ .copyCtx = (MdCopyCtx)CRYPT_SHA2_256_CopyCtx,
+};
+
+int32_t drv_cipher_hkdf(crypto_hkdf_t *hkdf_param, uint8_t *okm, uint32_t okm_length)
+{
+ int32_t ret;
+
+ ret = CRYPT_HKDF(&g_mac_hmac_method, &g_md_sha256_meth, hkdf_param->ikm, hkdf_param->ikm_length,
+ hkdf_param->salt, hkdf_param->salt_length, hkdf_param->info, hkdf_param->info_length,
+ okm, okm_length);
+ crypto_chk_return(ret != CRYPT_SUCCESS, ret, "CRYPT_HKDF failed\n");
+
+ return CRYPTO_SUCCESS;
+}
\ No newline at end of file
--- /dev/null
+/**
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n
+ *
+ * Description: Provides IPC source \n
+ * Author: @CompanyNameTag \n
+ * History: \n
+ * 2025-04-18, Create file. \n
+ */
+#include "drv_symc_aead.h"
+
+#include "crypt_modes_gcm.h"
+#include "crypt_errno.h"
+#include "crypt_aes.h"
+
+#include "crypto_drv_common.h"
+
+#define MAX_TAG_LEN 16
+
+typedef int32_t (*encType)(void *ctx, const uint8_t *key, uint32_t len);
+typedef int32_t (*updateType)(void *ctx, const uint8_t *in, uint8_t *out, uint32_t len);
+typedef int32_t (*ctrlType)(void *ctx, uint32_t opt, void *val, uint32_t len);
+
+static const EAL_CipherMethod aes128 = {
+ .initCtx = NULL,
+ .deinitCtx = NULL,
+ .clean = NULL,
+ .setEncryptKey = (encType)CRYPT_AES_SetEncryptKey128,
+ .setDecryptKey = (encType)CRYPT_AES_SetDecryptKey128,
+ .encrypt = (updateType)CRYPT_AES_Encrypt,
+ .decrypt = (updateType)CRYPT_AES_Decrypt,
+ .ctrl = (ctrlType)NULL,
+ .blockSize = 1,
+ .ctxSize = sizeof(CRYPT_AES_Key),
+ .algId = CRYPT_SYM_AES128
+};
+
+#define SYMC_CTX_NUM 2
+typedef struct {
+ bool is_open;
+ MODES_GCM_Ctx gcm_ctx;
+ uint8_t tag[16];
+ uint32_t tag_len;
+} drv_symc_hitls_ctx;
+
+static drv_symc_hitls_ctx g_symc_ctx[SYMC_CTX_NUM];
+
+static int32_t inner_alloc_ctx(uint32_t *handle)
+{
+ uint32_t i;
+ for (i = 0; i < SYMC_CTX_NUM; i++) {
+ if (g_symc_ctx[i].is_open == false) {
+ *handle = i;
+ g_symc_ctx[i].is_open = true;
+ return CRYPTO_SUCCESS;
+ }
+ }
+ return CRYPTO_FAILURE;
+}
+
+static void inner_free_ctx(uint32_t handle)
+{
+ drv_symc_hitls_ctx *ctx = NULL;
+ if (handle > SYMC_CTX_NUM) {
+ return;
+ }
+ ctx = &g_symc_ctx[handle];
+ (void)memset_s(ctx, sizeof(drv_symc_hitls_ctx), 0, sizeof(drv_symc_hitls_ctx));
+}
+
+static drv_symc_hitls_ctx *inner_get_ctx(uint32_t handle)
+{
+ drv_symc_hitls_ctx *ctx = NULL;
+
+ if (handle > SYMC_CTX_NUM) {
+ crypto_log_err("invalid handle\n");
+ return NULL;
+ }
+
+ ctx = &g_symc_ctx[handle];
+ if (ctx->is_open == false) {
+ crypto_log_err("handle is closed\n");
+ return NULL;
+ }
+ return ctx;
+}
+
+int32_t drv_cipher_symc_gcm_create(uint32_t *handle,
+ uint8_t *key, uint32_t key_len, uint32_t keyslot_handle,
+ const uint8_t *iv, uint32_t iv_len,
+ const uint8_t *aad, uint32_t aad_len, uint32_t tag_len
+)
+{
+ int32_t ret;
+ drv_symc_hitls_ctx *ctx = NULL;
+ MODES_GCM_Ctx *gcm_ctx = NULL;
+ uint32_t out_tag_len = tag_len;
+ crypto_unused(keyslot_handle);
+
+ ret = inner_alloc_ctx(handle);
+ crypto_chk_return(ret != CRYPT_SUCCESS, ret, "inner_alloc_ctx failed\n");
+
+ ctx = &g_symc_ctx[*handle];
+ gcm_ctx = &ctx->gcm_ctx;
+
+ ret = MODES_GCM_InitCtx(gcm_ctx, &aes128);
+ crypto_chk_goto_with_ret(ret, ret != CRYPT_SUCCESS, error_free_ctx, CRYPTO_FAILURE, "MODES_GCM_InitCtx failed\n");
+
+ ret = MODES_GCM_SetKey(gcm_ctx, key, key_len);
+ crypto_chk_goto_with_ret(ret, ret != CRYPT_SUCCESS, error_clean, CRYPTO_FAILURE, "MODES_GCM_SetKey failed\n");
+
+ ret = MODES_GCM_Ctrl(gcm_ctx, CRYPT_CTRL_SET_TAGLEN, (void *)&out_tag_len, sizeof(out_tag_len));
+ crypto_chk_goto_with_ret(ret, ret != CRYPT_SUCCESS, error_clean, CRYPTO_FAILURE, "MODES_GCM_Ctrl failed\n");
+
+ ret = MODES_GCM_Ctrl(gcm_ctx, CRYPT_CTRL_SET_IV, (void *)iv, iv_len);
+ crypto_chk_goto_with_ret(ret, ret != CRYPT_SUCCESS, error_clean, CRYPTO_FAILURE, "MODES_GCM_Ctrl failed\n");
+
+ ret = MODES_GCM_Ctrl(gcm_ctx, CRYPT_CTRL_SET_AAD, (void *)aad, aad_len);
+ crypto_chk_goto_with_ret(ret, ret != CRYPT_SUCCESS, error_clean, CRYPTO_FAILURE, "MODES_GCM_Ctrl failed\n");
+
+ ctx->tag_len = tag_len;
+ return CRYPTO_SUCCESS;
+
+error_clean:
+ MODES_GCM_DeinitCtx(&ctx->gcm_ctx);
+error_free_ctx:
+ inner_free_ctx(*handle);
+ return ret;
+}
+
+int32_t drv_cipher_symc_gcm_destroy(uint32_t handle)
+{
+ drv_symc_hitls_ctx *ctx = NULL;
+
+ if (handle > SYMC_CTX_NUM) {
+ crypto_log_err("invalid handle\n");
+ return CRYPTO_FAILURE;
+ }
+ ctx = &g_symc_ctx[handle];
+
+ MODES_GCM_DeinitCtx(&ctx->gcm_ctx);
+ inner_free_ctx(handle);
+
+ return CRYPTO_SUCCESS;
+}
+
+int32_t drv_cipher_symc_gcm_encrypt_update(uint32_t handle,
+ const uint8_t *plain_text, uint8_t *cipher_text, uint32_t data_len
+)
+{
+ int32_t ret;
+ drv_symc_hitls_ctx *ctx = NULL;
+
+ ctx = inner_get_ctx(handle);
+ crypto_chk_return(ctx == NULL, CRYPTO_FAILURE, "inner_get_ctx failed\n");
+
+ ret = MODES_GCM_Encrypt(&ctx->gcm_ctx, plain_text, cipher_text, data_len);
+ crypto_chk_return(ret != CRYPT_SUCCESS, CRYPTO_FAILURE, "MODES_GCM_Encrypt failed\n");
+
+ return CRYPTO_SUCCESS;
+}
+
+int32_t drv_cipher_symc_gcm_encrypt_get_tag(uint32_t handle,
+ uint8_t *tag, uint32_t tag_len
+)
+{
+ int32_t ret;
+ drv_symc_hitls_ctx *ctx = NULL;
+
+ ctx = inner_get_ctx(handle);
+ crypto_chk_return(ctx == NULL, CRYPTO_FAILURE, "inner_get_ctx failed\n");
+
+ ret = MODES_GCM_Ctrl(&ctx->gcm_ctx, CRYPT_CTRL_GET_TAG, tag, tag_len);
+ crypto_chk_return(ret != CRYPT_SUCCESS, CRYPTO_FAILURE, "MODES_GCM_Ctrl failed\n");
+
+ return CRYPTO_SUCCESS;
+}
+
+int32_t drv_cipher_symc_gcm_decrypt_set_tag(uint32_t handle,
+ const uint8_t *tag, uint32_t tag_len
+)
+{
+ int32_t ret;
+ drv_symc_hitls_ctx *ctx = NULL;
+
+ ctx = inner_get_ctx(handle);
+ crypto_chk_return(ctx == NULL, CRYPTO_FAILURE, "inner_get_ctx failed\n");
+
+ ret = memcpy_s(ctx->tag, sizeof(ctx->tag), tag, tag_len);
+ crypto_chk_return(ret != EOK, CRYPTO_FAILURE, "memcpy_s failed\n");
+
+ return CRYPTO_SUCCESS;
+}
+
+int32_t drv_cipher_symc_gcm_decrypt_update(uint32_t handle,
+ const uint8_t *cipher_text, uint8_t *plain_text, uint32_t data_len
+)
+{
+ int32_t ret;
+ drv_symc_hitls_ctx *ctx = NULL;
+
+ ctx = inner_get_ctx(handle);
+ crypto_chk_return(ctx == NULL, CRYPTO_FAILURE, "inner_get_ctx failed\n");
+
+ ret = MODES_GCM_Decrypt(&ctx->gcm_ctx, cipher_text, plain_text, data_len);
+ crypto_chk_return(ret != CRYPT_SUCCESS, CRYPTO_FAILURE, "MODES_GCM_Decrypt failed\n");
+
+ return CRYPTO_SUCCESS;
+}
+
+int32_t drv_cipher_symc_gcm_decrypt_verify_tag(uint32_t handle)
+{
+ int32_t ret;
+ uint32_t i;
+ uint8_t tag_check = 0;
+ uint8_t out_tag[MAX_TAG_LEN];
+ drv_symc_hitls_ctx *ctx = NULL;
+
+ ctx = inner_get_ctx(handle);
+ crypto_chk_return(ctx == NULL, CRYPTO_FAILURE, "inner_get_ctx failed\n");
+
+ ret = MODES_GCM_Ctrl(&ctx->gcm_ctx, CRYPT_CTRL_GET_TAG, out_tag, ctx->tag_len);
+ crypto_chk_return(ret != CRYPT_SUCCESS, CRYPTO_FAILURE, "MODES_GCM_Ctrl failed\n");
+
+ /* tag compare. */
+ for (i = 0; i < ctx->tag_len; i++) {
+ tag_check |= ctx->tag[i] ^ out_tag[i];
+ }
+ if (tag_check != 0) {
+ crypto_log_err("gcm tag auth failed\n");
+ return CRYPTO_FAILURE;
+ }
+ return CRYPTO_SUCCESS;
+}
+
+int32_t drv_cipher_symc_gcm_encrypt(
+ uint8_t *key, uint32_t key_len, uint32_t keyslot_handle,
+ const uint8_t *iv, uint32_t iv_len,
+ const uint8_t *aad, uint32_t aad_len,
+ const uint8_t *plain_text, uint8_t *cipher_text, uint32_t data_len,
+ uint8_t *tag, uint32_t tag_len
+)
+{
+ int32_t ret;
+ MODES_GCM_Ctx ctx;
+ uint32_t out_tag_len = tag_len;
+
+ crypto_unused(keyslot_handle);
+
+ ret = MODES_GCM_InitCtx(&ctx, &aes128);
+ crypto_chk_return(ret != CRYPT_SUCCESS, ret, "MODES_GCM_InitCtx failed\n");
+
+ ret = MODES_GCM_SetKey(&ctx, key, key_len);
+ crypto_chk_goto_with_ret(ret, ret != CRYPT_SUCCESS, exit_clean, CRYPTO_FAILURE, "MODES_GCM_SetKey failed\n");
+
+ ret = MODES_GCM_Ctrl(&ctx, CRYPT_CTRL_SET_TAGLEN, (void *)&out_tag_len, sizeof(out_tag_len));
+ crypto_chk_goto_with_ret(ret, ret != CRYPT_SUCCESS, exit_clean, CRYPTO_FAILURE, "MODES_GCM_Ctrl failed\n");
+
+ ret = MODES_GCM_Ctrl(&ctx, CRYPT_CTRL_SET_IV, (void *)iv, iv_len);
+ crypto_chk_goto_with_ret(ret, ret != CRYPT_SUCCESS, exit_clean, CRYPTO_FAILURE, "MODES_GCM_Ctrl failed\n");
+
+ ret = MODES_GCM_Ctrl(&ctx, CRYPT_CTRL_SET_AAD, (void *)aad, aad_len);
+ crypto_chk_goto_with_ret(ret, ret != CRYPT_SUCCESS, exit_clean, CRYPTO_FAILURE, "MODES_GCM_Ctrl failed\n");
+
+ ret = MODES_GCM_Encrypt(&ctx, plain_text, cipher_text, data_len);
+ crypto_chk_goto_with_ret(ret, ret != CRYPT_SUCCESS, exit_clean, CRYPTO_FAILURE, "MODES_GCM_Encrypt failed\n");
+
+ ret = MODES_GCM_Ctrl(&ctx, CRYPT_CTRL_GET_TAG, tag, out_tag_len);
+ crypto_chk_goto_with_ret(ret, ret != CRYPT_SUCCESS, exit_clean, CRYPTO_FAILURE, "MODES_GCM_Ctrl failed\n");
+
+exit_clean:
+ MODES_GCM_DeinitCtx(&ctx);
+ return ret;
+}
+
+int32_t drv_cipher_symc_gcm_decrypt_verify(
+ uint8_t *key, uint32_t key_len, uint32_t keyslot_handle,
+ const uint8_t *iv, uint32_t iv_len,
+ const uint8_t *aad, uint32_t aad_len,
+ const uint8_t *cipher_text, uint8_t *plain_text, uint32_t data_len,
+ const uint8_t *tag, uint32_t tag_len
+)
+{
+ int32_t ret;
+ MODES_GCM_Ctx ctx;
+ uint8_t out_tag[MAX_TAG_LEN];
+ uint32_t out_tag_len = tag_len;
+ uint8_t tag_check = 0;
+ uint32_t i;
+
+ crypto_unused(keyslot_handle);
+
+ crypto_chk_return(tag_len > MAX_TAG_LEN, CRYPTO_FAILURE, "tag_len is too long\n");
+
+ ret = MODES_GCM_InitCtx(&ctx, &aes128);
+ crypto_chk_return(ret != CRYPT_SUCCESS, ret, "MODES_GCM_InitCtx failed\n");
+
+ ret = MODES_GCM_SetKey(&ctx, key, key_len);
+ crypto_chk_goto_with_ret(ret, ret != CRYPT_SUCCESS, exit_clean, CRYPTO_FAILURE, "MODES_GCM_SetKey failed\n");
+
+ ret = MODES_GCM_Ctrl(&ctx, CRYPT_CTRL_SET_TAGLEN, (void *)&out_tag_len, sizeof(out_tag_len));
+ crypto_chk_goto_with_ret(ret, ret != CRYPT_SUCCESS, exit_clean, CRYPTO_FAILURE, "MODES_GCM_Ctrl failed\n");
+
+ ret = MODES_GCM_Ctrl(&ctx, CRYPT_CTRL_SET_IV, (void *)iv, iv_len);
+ crypto_chk_goto_with_ret(ret, ret != CRYPT_SUCCESS, exit_clean, CRYPTO_FAILURE, "MODES_GCM_Ctrl failed\n");
+
+ ret = MODES_GCM_Ctrl(&ctx, CRYPT_CTRL_SET_AAD, (void *)aad, aad_len);
+ crypto_chk_goto_with_ret(ret, ret != CRYPT_SUCCESS, exit_clean, CRYPTO_FAILURE, "MODES_GCM_Ctrl failed\n");
+
+ ret = MODES_GCM_Decrypt(&ctx, cipher_text, plain_text, data_len);
+ crypto_chk_goto_with_ret(ret, ret != CRYPT_SUCCESS, exit_clean, CRYPTO_FAILURE, "MODES_GCM_Decrypt failed\n");
+
+ ret = MODES_GCM_Ctrl(&ctx, CRYPT_CTRL_GET_TAG, out_tag, out_tag_len);
+ if (ret != CRYPT_SUCCESS) {
+ crypto_log_err("MODES_GCM_Ctrl failed\n");
+ ret = CRYPTO_FAILURE;
+ (void)memset_s(plain_text, data_len, 0, data_len);
+ goto exit_clean;
+ }
+
+ /* tag compare. */
+ for (i = 0; i < tag_len; i++) {
+ tag_check |= tag[i] ^ out_tag[i];
+ }
+ if (tag_check != 0) {
+ crypto_log_err("gcm tag auth failed\n");
+ ret = CRYPTO_FAILURE;
+ (void)memset_s(plain_text, data_len, 0, data_len);
+ goto exit_clean;
+ }
+
+ ret = CRYPTO_SUCCESS;
+exit_clean:
+ MODES_GCM_DeinitCtx(&ctx);
+ return ret;
+}
\ No newline at end of file
--- /dev/null
+/**
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n
+ *
+ * Description: crypto common def header. \n
+ * Author: @CompanyNameTag \n
+ * History: \n
+ * 2023-03-22, Create file. \n
+ */
+#ifndef CRYPTO_COMMON_DEF_H
+#define CRYPTO_COMMON_DEF_H
+
+#define MS_TO_US 1000
+
+#define CRYPTO_BITS_IN_BYTE 8
+#define CRYPTO_BYTE_MAX 0xFF
+
+#define CRYPTO_AES_IV_SIZE 16
+#define CRYPTO_AES_IV_SIZE_IN_WORD 4
+#define CRYPTO_WORD_WIDTH 4
+#define CRYPTO_IV_LEN_IN_BYTES 16
+
+#define CRYPTO_128_KEY_LEN 16
+#define CRYPTO_192_KEY_LEN 24
+#define CRYPTO_256_KEY_LEN 32
+
+#define CRYPTO_AES_MAX_TAG_SIZE 16
+#define CRYPTO_AES_CCM_N_LEN_IN_BYTES 16
+
+#define CRYPTO_AES_BLOCK_SIZE_IN_BYTES 16
+
+#define CRYPTO_BIT_3 3
+#define CRYPTO_BIT_6 6
+#define CRYPTO_BIT_8 8
+#define CRYPTO_BIT_16 16
+#define CRYPTO_BIT_24 24
+#define CRYPTO_BYTE_1 1
+#define CRYPTO_BYTE_2 2
+#define CRYPTO_BYTE_3 3
+
+#define CRYPTO_AES_CCM_NQ_LEN 14
+#define CRYPTO_SYMC_CCM_Q_LEN_2B 2
+#define CRYPTO_SYMC_CCM_Q_LEN_3B 3
+#define CRYPTO_SYMC_CCM_Q_LEN_4B 4
+#define CRYPTO_SYMC_CCM_HEADER_LEN 2
+
+#define HASH_SHA1_BLOCK_SIZE 64
+#define HASH_SHA224_BLOCK_SIZE 64
+#define HASH_SHA256_BLOCK_SIZE 64
+#define HASH_SHA384_BLOCK_SIZE 128
+#define HASH_SHA512_BLOCK_SIZE 128
+#define HASH_SM3_BLOCK_SIZE 64
+#define HASH_MAX_BLOCK_SIZE 128
+
+#define HASH_SHA1_RESULT_SIZE 20
+#define HASH_SHA224_RESULT_SIZE 28
+#define HASH_SHA256_RESULT_SIZE 32
+#define HASH_SHA384_RESULT_SIZE 48
+#define HASH_SHA512_RESULT_SIZE 64
+#define HASH_SM3_RESULT_SIZE 32
+#define HASH_MAX_RESULT_SIZE 64
+
+#define HASH_STATE_SIZE_160 20
+#define HASH_STATE_SIZE_256 32
+#define HASH_STATE_SIZE_512 64
+
+#define CRYPTO_GCM_SPECIAL_IV_BYTES 12
+#define CRYPTO_AES_MAX_TAG_LEN 16
+
+#define CRYPTO_CENC_IV_LEN 8
+
+#define CRYPTO_TYPE_ENCRYPT 0x0
+#define CRYPTO_TYPE_DECRYPT 0x1
+#define CRYPTO_TYPE_DMA 0x2
+
+#define CRYPTO_RSA_1024_LEN 128
+#define CRYPTO_RSA_2048_LEN 256
+#define CRYPTO_RSA_3072_LEN 384
+#define CRYPTO_RSA_4096_LEN 512
+
+/* Memory Limit. */
+#define CRYPTO_MAX_AAD_SIZE (4 * 1024)
+#define CRYPTO_MAX_CRYPTO_SIZE (4 * 1024)
+
+/* PBKDF2 Limits. */
+#define CRYPTO_PBKDF2_PASS_MAX_LENGTH 1024
+#define CRYPTO_PBKDF2_SALT_MAX_LENGTH 1024
+#define CRYPTO_PBKDF2_OUT_MAX_LENGTH 1024
+#define CRYPTO_PBKDF2_MAX_COUNT 100000
+
+/* Hash Limits. */
+#define CRYPTO_HASH_KEY_MAX_LENGTH 128
+#define CRYPTO_HASH_MIN_LEN 20
+#define CRYPTO_HASH_MAX_LEN 64
+#define CRYPTO_HASH_UPDATE_MAX_LEN 0xffff0000
+#define CRYPTO_SHA256_BLOCK_SIZE 64
+
+/* CENC Limits. */
+#define CRYPTO_SYMC_CENC_SUBSAMPLE_MAX_SIZE 200
+
+/* SYMC Limits. */
+#define CRYPTO_SYMC_MULTI_PACK_MAX_SIZE 200
+#define CRYPTO_SYMC_AAD_MAX_SIZE (4 * 1024)
+#define CRYPTO_SYMC_MAC_UPDATE_MAX_LEN 0xffff0000
+
+/* PKE Limits. */
+#define CRYPTO_PKE_ECC_KEY_MIN_SIZE 32
+#define CRYPTO_PKE_ECC_KEY_MAX_SIZE 72
+#define CRYPTO_PKE_RSA_KEY_MIN_SIZE 256
+#define CRYPTO_PKE_RSA_KEY_MAX_SIZE 512
+
+/* TRNG Limits. */
+#define CRYPTO_MULTI_RANDOM_MAX_LENGTH 1024
+
+/* HKDF Limits. */
+#define HKDF_EXPAND_INFO_MAX_LENGTH 1024
+
+#define CRYPTO_PKE_MSG_MIN_SIZE 1
+#define CRYPTO_PKE_MSG_MAX_SIZE (2 * 1024 * 1024)
+#define CRYPTO_PKE_SM2_ID_MIN_SIZE 1
+#define CRYPTO_PKE_SM2_ID_MAX_SIZE 1024
+#define CRYPTO_PKE_SM2_PLAIN_TEXT_MIN_SIZE 1
+#define CRYPTO_PKE_SM2_PLAIN_TEXT_MAX_SIZE 1024
+#define CRYPTO_PKE_RSA_LABLE_MAX_SIZE 1024
+
+#define KAPI_SYMC_MODULE_ID 0x01
+#define KAPI_HASH_MODULE_ID 0x02
+#define KAPI_KEYSLOT_MODULE_ID 0x03
+#define KAPI_KLAD_MODULE_ID 0x04
+/*
+ * Handle Process
+ * Kapi Handle consists of the following parts:
+ *|<---- SOC_ID_CIPHER(8-bit) --->|<---- Reserved(7-bit) --->|
+ * <- Soft alg flag(1-bit) ->|<---- Module ID(8-bit) ---->|<---- Context Idx(8-bit)---->|
+ */
+#define crypto_set_soft_alg_flag(handle) ((handle) | 0x10000)
+#define crypto_check_soft_alg_flag(handle) (((handle) >> 16) & 0x1)
+#define crypto_get_soft_channel_id(handle) ((handle) & 0xff)
+
+#define kapi_get_module_id(kapi_handle) (((kapi_handle) >> 8) & 0xff)
+#define kapi_get_ctx_idx(kapi_handle) ((kapi_handle) & 0xff)
+#define synthesize_kapi_handle(module_id, ctx_id) (((0x33) << 24) | ((module_id) << 8) | (ctx_id))
+
+/*
+ *|<---- Reserved(8-bit) --->|<- keyslot_type(8-bit) ->|<---- Module ID(8-bit) ---->|<---- Context Idx(8-bit)---->|
+ * keyslot_type: 0 - MCIPHER, 1 - HMAC
+ */
+#define crypto_keyslot_compat_handle(keyslot_type, idx) \
+ (((keyslot_type) << 16) | ((KAPI_KEYSLOT_MODULE_ID) << 8) | (idx))
+#define crypto_keyslot_compat_hmac_handle(idx) crypto_keyslot_compat_handle(1, idx)
+#define crypto_keyslot_compat_mcipher_handle(idx) crypto_keyslot_compat_handle(0, idx)
+#define crypto_keyslot_is_hmac(handle) ((((handle) >> 16) & 0xff) == 0x1)
+#define crypto_keyslot_is_mcipher(handle) ((((handle) >> 16) & 0xff) == 0)
+#define crypto_keyslot_get_idx(handle) ((handle) & 0xff)
+#define crypto_keyslot_get_module_id(handle) (((handle) >> 8) & 0xff)
+
+#endif
--- /dev/null
+/**
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n
+ *
+ * Description: crypto common macro header. \n
+ * Author: @CompanyNameTag \n
+ * History: \n
+ * 2023-03-22, Create file. \n
+ */
+#ifndef CRYPTO_COMMON_MACRO_H
+#define CRYPTO_COMMON_MACRO_H
+
+#ifndef CRYPTO_STATIC
+#define CRYPTO_STATIC static
+#endif
+
+#define crypto_cpu_to_be32(v) ((((td_u32)(v)) >> 24) | ((((td_u32)(v)) >> 8) & 0xff00) \
+ | ((((td_u32)(v)) << 8) & 0xff0000) | (((td_u32)(v)) << 24))
+
+#define crypto_max(a, b) ((a) > (b)) ? (a) : (b)
+#define crypto_min(a, b) ((a) > (b)) ? (b) : (a)
+
+#ifndef crypto_unused
+#define crypto_unused(x) (td_void)(x)
+#endif
+
+#define crypto_array_size(arr) (sizeof(arr) / sizeof((arr)[0]))
+
+#define crypto_reg_read(reg_addr) (*(volatile td_u32 *)(uintptr_t)(reg_addr))
+#define crypto_reg_write(reg_addr, value) (*(volatile td_u32 *)(uintptr_t)(reg_addr) = (value))
+
+#define crypto_set_bits(src, bit) ((src) |= (1 << (bit)))
+#define crypto_clear_bits(src, bit) ((src) &= ~(1 << (bit)))
+
+/* Assert Check. */
+#if defined(CONFIG_CRYPTO_ASSERT_ENABLE)
+#define crypto_assert_eq(a, b) do { \
+ if ((a) != (b)) { \
+ crypto_log_err("ASSERT_EQ Failure. \nExpected: %s == %s\nReal: %s is 0x%x, %s is 0x%x\n", \
+ #a, #b, #a, a, #b, b); \
+ } \
+} while (0)
+#define crypto_assert_neq(a, b) do { \
+ if ((a) == (b)) { \
+ crypto_log_err("ASSERT_EQ Failure. \nExpected: %s != %s\nReal: %s is 0x%x, %s is 0x%x\n", \
+ #a, #b, #a, a, #b, b); \
+ } \
+} while (0)
+#else
+#define crypto_assert_eq(a, b)
+#define crypto_assert_neq(a, b)
+#endif
+
+/* Error Check. */
+#define crypto_chk_print(cond, ...) do { \
+ if (cond) { \
+ crypto_log_err(__VA_ARGS__); \
+ } \
+} while (0)
+
+#define crypto_chk_return(cond, err_ret, ...) do { \
+ if (cond) { \
+ crypto_log_err(__VA_ARGS__); \
+ return err_ret; \
+ } \
+} while (0)
+
+#define crypto_chk_return_void(cond, ...) do { \
+ if (cond) { \
+ crypto_log_err(__VA_ARGS__); \
+ return; \
+ } \
+} while (0)
+
+#define crypto_chk_goto(cond, label, ...) do { \
+ if (cond) { \
+ crypto_log_err(__VA_ARGS__); \
+ goto label; \
+ } \
+} while (0)
+
+/* Input Params Check. */
+#define crypto_param_require(cond) do { \
+ if (!(cond)) { \
+ crypto_log_err("Param Check %s failed\n", #cond); \
+ return CRYPTO_FAILURE; \
+ } \
+} while (0)
+
+#define crypto_param_check(cond) do { \
+ if (cond) { \
+ crypto_log_err("Param Check %s failed\n", #cond); \
+ return CRYPTO_FAILURE; \
+ } \
+} while (0)
+
+#define crypto_chk_goto_with_ret(ret, cond, label, err_ret, fmt, ...) do { \
+ if (cond) { \
+ crypto_log_err(fmt, ##__VA_ARGS__); \
+ ret = err_ret; \
+ goto label; \
+ } \
+} while (0)
+
+#if defined(CRYPTO_HAL_FUNC_TRACE_ENABLE)
+#define crypto_hal_func_enter() crypto_print("########%s===>Enter\n", __func__)
+#define crypto_hal_func_exit() crypto_print("########%s<===Exit\n", __func__)
+#else
+#define crypto_hal_func_enter()
+#define crypto_hal_func_exit()
+#endif
+
+#if defined(CRYPTO_KAPI_FUNC_TRACE_ENABLE)
+#define crypto_kapi_func_enter() crypto_print("%s===>Enter\n", __func__)
+#define crypto_kapi_func_exit() crypto_print("%s<===Exit\n", __func__)
+#else
+#define crypto_kapi_func_enter()
+#define crypto_kapi_func_exit()
+#endif
+
+#if defined(CRYPTO_DRV_FUNC_TRACE_ENABLE)
+#define crypto_drv_func_enter() crypto_print("####%s===>Enter\n", __func__)
+#define crypto_drv_func_exit() crypto_print("####%s<===Exit\n", __func__)
+#else
+#define crypto_drv_func_enter()
+#define crypto_drv_func_exit()
+#endif
+
+#if defined(CRYPTO_DISPATCH_FUNC_TRACE_ENABLE)
+#define crypto_dispatch_func_enter() crypto_print("%s===>Enter\n", __func__)
+#define crypto_dispatch_func_exit() crypto_print("%s<===Exit\n", __func__)
+#else
+#define crypto_dispatch_func_enter()
+#define crypto_dispatch_func_exit()
+#endif
+
+#if defined(CRYPTO_UAPI_FUNC_TRACE_ENABLE)
+#define crypto_uapi_func_enter() crypto_print("%s ===>Enter\n", __func__)
+#define crypto_uapi_func_exit() crypto_print("%s <===Exit\n", __func__)
+#else
+#define crypto_uapi_func_enter()
+#define crypto_uapi_func_exit()
+#endif
+
+#ifndef crypto_print_func_err
+#define crypto_print_func_err(_func, _err_code) do { \
+ crypto_log_err("%s failed! error code: 0x%x \r\n", #_func, _err_code); \
+} while (0)
+#endif
+
+#ifndef crypto_chk_func_return
+#define crypto_chk_func_return(func, ret) do { \
+ if ((ret) != TD_SUCCESS) { \
+ crypto_print_func_err(func, ret); \
+ return ret; \
+ } \
+} while (0)
+#endif
+
+#ifndef crypto_check_param
+#define crypto_check_param(err_level, module, cond, err_code) do { \
+ if (cond) { \
+ crypto_log_err("invalid parameter: %s \r\n", #cond); \
+ return CRYPTO_COMPAT_ERRNO(CRYPTO_ERROR_ENV, err_level, module, err_code); \
+ } \
+} while (0)
+#endif
+
+#ifndef crypto_check_param_null
+#define crypto_check_param_null(err_level, module, _val) do { \
+ crypto_check_param(err_level, module, ((_val) == TD_NULL), ERROR_PARAM_IS_NULL); \
+} while (0)
+#endif
+
+#ifndef drv_crypto_check_param
+#define drv_crypto_check_param(module, cond) do { \
+ crypto_check_param(ERROR_LAYER_DRV, module, cond, ERROR_INVALID_PARAM); \
+} while (0)
+#endif
+
+#ifndef drv_crypto_check_param_null
+#define drv_crypto_check_param_null(module, _val) do { \
+ crypto_check_param_null(ERROR_LAYER_DRV, module, _val); \
+} while (0)
+#endif
+
+#ifndef drv_crypto_pke_check_param
+#define drv_crypto_pke_check_param(cond) do { \
+ drv_crypto_check_param(ERROR_MODULE_PKE, cond); \
+} while (0)
+#endif
+
+#ifndef drv_crypto_pke_check_param_null
+#define drv_crypto_pke_check_param_null(_val) do { \
+ drv_crypto_check_param_null(ERROR_MODULE_PKE, _val); \
+} while (0)
+#endif
+
+#endif
--- /dev/null
+/**
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n
+ *
+ * Description: crypto common struct header. \n
+ * Author: @CompanyNameTag \n
+ * History: \n
+ * 2023-03-22, Create file. \n
+ */
+#ifndef CRYPTO_COMMON_STRUCT_H
+#define CRYPTO_COMMON_STRUCT_H
+
+#include "crypto_type.h"
+
+/* ! \union of compat addr */
+typedef union {
+ void *p; /* !< virtual address */
+ unsigned long long phy; /* !< physical address */
+ unsigned int word[2]; /* !< 2 word of address */
+} crypto_compat_addr;
+
+typedef enum {
+ CRYPTO_BUF_SECURE,
+ CRYPTO_BUF_NONSECURE,
+} crypto_buffer_secure;
+
+typedef struct {
+ unsigned long long uapi_mem_handle; /* Handle to buffer header address */
+ unsigned long long addr_offset; /* buffer offset, unused. */
+ td_void *kapi_mem_handle;
+
+ unsigned long long phys_addr;
+ void *virt_addr;
+ crypto_buffer_secure buf_sec; /* NONSECURE or SECURE */
+} crypto_buf_attr;
+
+typedef enum {
+ CPU_ID_AIDSP = 0x00000035,
+ CPU_ID_PCPU = 0x0000006a,
+ CPU_ID_SCPU = 0x000000a5,
+ CPU_ID_ACPU = 0x000000aa,
+ CPU_ID_INVALID = 0xffffffff
+} ca_misc_cpu_id;
+
+typedef enum {
+ CRYPTO_MEM_TYPE_MMZ,
+ CRYPTO_MEM_TYPE_SMMU,
+} crypto_mem_type;
+
+typedef enum {
+ CRYPTO_CPU_TYPE_SCPU,
+ CRYPTO_CPU_TYPE_ACPU,
+ CRYPTO_CPU_TYPE_HPPCPU,
+ CRYPTO_CPU_TYPE_PCPU,
+ CRYPTO_CPU_TYPE_AIDSP,
+ CRYPTO_CPU_TYPE_INVALID
+} crypto_cpu_type;
+
+typedef enum {
+ IN_NODE_TYPE_FIRST = 1 << 0,
+ IN_NODE_TYPE_NORMAL = 1 << 1,
+ IN_NODE_TYPE_LAST = 1 << 2,
+ /* CCM. */
+ IN_NODE_TYPE_CCM_N = 1 << 3,
+ IN_NODE_TYPE_CCM_AAD = 1 << 4,
+ IN_NODE_TYPE_CCM_P = 1 << 5,
+ IN_NODE_TYPE_CCM_LAST = 1 << 6,
+ /* GCM. */
+ IN_NODE_TYPE_GCM_FIRST = 1 << 7,
+ IN_NODE_TYPE_GCM_A = 1 << 8,
+ IN_NODE_TYPE_GCM_P = 1 << 9,
+ IN_NODE_TYPE_GCM_LEN = 1 << 10,
+ IN_NODE_TYPE_GCM_GHASH = 1 << 11,
+ IN_NODE_TYPE_GCM_IV = 1 << 12,
+} in_node_type_e;
+
+typedef void *(*func_malloc)(unsigned int size, crypto_mem_type mem_type, const td_char *name);
+typedef void (*func_free)(void *ptr);
+typedef td_u64 (*func_get_phys_addr)(const void *ptr);
+typedef void *(*func_get_virt_addr)(void *ptr);
+typedef td_bool (*func_get_smmu_table_addr)(td_u64 *table, td_u64 *rdaddr, td_u64 *wraddr);
+typedef void *(*func_register_coherent_mem)(void *virt_addr, td_u64 phys_addr, unsigned int size);
+typedef void (*func_unregister_coherent_mem)(void *virt_addr);
+typedef crypto_cpu_type (*func_get_cpu_type)(void);
+
+typedef struct {
+ func_malloc malloc_coherent;
+ func_free free_coherent;
+ func_get_phys_addr get_phys_addr;
+ func_get_virt_addr get_virt_addr;
+ func_get_smmu_table_addr get_smmu_table_addr;
+ func_register_coherent_mem register_coherent_mem;
+ func_unregister_coherent_mem unregister_coherent_mem;
+ func_get_cpu_type get_cpu_type;
+} crypto_drv_func;
+
+typedef td_bool (*drv_wait_condition_func)(const td_void *param);
+typedef td_s32 (*crypto_wait_timeout_interruptible)(const td_void *wait, drv_wait_condition_func func,
+ const td_void *param, const td_u32 timeout_ms);
+
+#endif
\ No newline at end of file
--- /dev/null
+/**
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n
+ *
+ * Description: crypto errno header. \n
+ * Author: @CompanyNameTag \n
+ * History: \n
+ * 2023-03-22, Create file. \n
+ */
+#ifndef CRYPTO_ERRNO_H
+#define CRYPTO_ERRNO_H
+
+/**
+ * The Struction of Error Number is as follows:
+ * Env(4 bits) | Layer(4 bits) | Modules(4 bits) | Reserved(12 bits) | Error Code(8 bits)
+ **/
+
+/* Error for Environments Definition. */
+#define ERROR_ENV_LINUX 0x1
+#define ERROR_ENV_ITRUSTEE 0x2
+#define ERROR_ENV_OPTEE 0x3
+#define ERROR_ENV_LITEOS 0x4
+#define ERROR_ENV_SELITEOS 0x5
+#define ERROR_ENV_NOOS 0x6
+#define ERROR_ENV_FREERTOS 0x7
+#define ERROR_ENV_ALIOS 0x8
+
+/* Error for Layer Enumerations. */
+enum {
+ ERROR_LAYER_UAPI = 0x1,
+ ERROR_LAYER_DISPATCH,
+ ERROR_LAYER_KAPI,
+ ERROR_LAYER_DRV,
+ ERROR_LAYER_HAL,
+};
+
+/* Error for Module Enumerations. */
+enum {
+ ERROR_MODULE_SYMC = 0x1,
+ ERROR_MODULE_HASH,
+ ERROR_MODULE_PKE,
+ ERROR_MODULE_TRNG,
+ ERROR_MODULE_KM,
+ ERROR_MODULE_OTP,
+ ERROR_MODULE_OTHER
+};
+
+/* Error for Error Code Enumerations. */
+enum {
+ /* Common Error Code. 0x01 ~ 0x3F. */
+ ERROR_INVALID_PARAM = 0x1, /* return when the input param's value is not in the valid range. */
+ ERROR_PARAM_IS_NULL, /* return when the input param is NULL and required not NULL. */
+ ERROR_NOT_INIT, /* return when call other functions before call init function. */
+ ERROR_UNSUPPORT, /* return when some configuration is unsupport. */
+ ERROR_UNEXPECTED, /* reture when unexpected error occurs. */
+ ERROR_TRY_TIMES, /* return when the number of try attempts failed. */
+ ERROR_CHN_BUSY, /* return when try to create one channel but all channels are busy. */
+ ERROR_CTX_CLOSED, /* return when using one ctx to do something but has been closed. */
+ ERROR_NOT_SET_CONFIG, /* return when not set_config but need for symc. */
+ ERROR_NOT_ATTACHED, /* return when not attach but need for symc. */
+ ERROR_NOT_SET_SESSION_KEY, /* return when not set_session_key but need for klad. */
+ ERROR_NOT_MAC_START, /* return when not mac_start but need for symc. */
+ ERROR_INVALID_HANDLE, /* return when pass one invalid handle. */
+ ERROR_GET_PHYS_ADDR, /* return when transfer from virt_addr to phys_addr failed. */
+ ERROR_SYMC_LEN_NOT_ALIGNED, /* return when length isn't aligned to 16-Byte except CTR/CCM/GCM. */
+ ERROR_SYMC_ADDR_NOT_ALIGNED, /* return when the phys_addr writing to register is not aligned to 4-Byte. */
+ ERROR_PKE_RSA_SAME_DATA, /* return when rsa exp_mod, the input is equal to output. */
+ ERROR_PKE_RSA_CRYPTO_V15_CHECK, /* return when rsa crypto v15 padding check failed. */
+ ERROR_PKE_RSA_CRYPTO_OAEP_CHECK, /* return when rsa crypto oaep padding check failed. */
+ ERROR_PKE_RSA_VERIFY_V15_CHECK, /* return when rsa verify v15 padding check failed. */
+ ERROR_PKE_RSA_VERIFY_PSS_CHECK, /* return when rsa verify pss padding check failed. */
+ ERROR_PKE_RSA_GEN_KEY, /* return when rsa generate key failed. */
+ ERROR_PKE_SM2_DECRYPT, /* return when sm2 decrypt failed. */
+ ERROR_ECDSA_SIGN_R_IS_ZERO, /* return when ecdsa sign, the sig_r is zero. */
+ ERROR_ECDSA_SIGN_S_IS_ZERO, /* return when ecdsa sign, the sig_s is zero. */
+ ERROR_PKE_ECDSA_VERIFY_CHECK, /* return when ecdsa verify check failed. */
+ ERROR_OTP_ADDR_NOT_ALIGNED, /* return when otp address is not aligned to 4. */
+ ERROR_HASH_ADDR_NOT_ALIGNED, /* return when hash data's address is not aligned */
+ ERROR_HASH_LEN_NOT_ALIGNED, /* return when hash length is not aligned to block size. */
+
+ /* Outer's Error Code. 0x40 ~ 0x5F. */
+ ERROR_MEMCPY_S = 0x40, /* return when call memcpy_s failed. */
+ ERROR_MALLOC, /* return when call xxx_malloc failed. */
+ ERROR_MUTEX_INIT, /* return when call xxx_mutex_init failed. */
+ ERROR_MUTEX_LOCK, /* return when call xxx_lock failed. */
+ /* Specific Error Code for UAPI. 0x60 ~ 0x6F. */
+ ERROR_DEV_OPEN_FAILED, /* return when open dev failed. */
+ ERROR_COUNT_OVERFLOW, /* return when call init too many times. */
+
+ /* Specific Error Code for Dispatch. 0x70 ~ 0x7F. */
+ ERROR_CMD_DISMATCH = 0x70, /* return when cmd is dismatched. */
+ ERROR_COPY_FROM_USER, /* return when call copy_from_user failed. */
+ ERROR_COPY_TO_USER, /* return when call copy_to_user failed. */
+ ERROR_MEM_HANDLE_GET, /* return when parse user's mem handle to kernel's mem handle failed. */
+ ERROR_GET_OWNER, /* return when call crypto_get_owner failed. */
+
+ /* Specific Error Code for KAPI. 0x80 ~ 0x8F. */
+ ERROR_PROCESS_NOT_INIT = 0x80, /* return when one process not call kapi_xxx_init first. */
+ ERROR_MAX_PROCESS, /* return when process's num is over the limit. */
+ ERROR_MEMORY_ACCESS, /* return when access the memory that does not belong to itself. */
+ ERROR_INVALID_PROCESS, /* return when the process accesses resources of other processes. */
+ /* Specific Error Code for DRV. 0x90 ~ 0x9F. */
+
+ /* Specific Error Code for HAL. 0xA0 ~ 0xAF. */
+ ERROR_HASH_LOGIC = 0xA0, /* return when hash logic's error occurs. */
+ ERROR_PKE_LOGIC, /* return when pke logic's error occurs. */
+ ERROR_INVALID_CPU_TYPE, /* return when logic get the invalid cpu type. */
+ ERROR_INVALID_REGISTER_VALUE, /* return when value in register is invalid. */
+ ERROR_INVALID_PHYS_ADDR, /* return when phys_addr is invalid. */
+ ERROR_OTP_PERMISSION, /* return when otp access is forbidden. */
+
+ /* Specific Error Code for Timeout. 0xB0 ~ 0xBF. */
+ ERROR_GET_TRNG_TIMEOUT = 0xB0, /* return when logic get rnd timeout. */
+ ERROR_HASH_CLEAR_CHN_TIMEOUT, /* return when clear hash channel timeout. */
+ ERROR_HASH_CALC_TIMEOUT, /* return when hash calculation timeout. */
+ ERROR_SYMC_CLEAR_CHN_TIMEOUT, /* return when clear symc channel timeout. */
+ ERROR_SYMC_CALC_TIMEOUT, /* return when symc crypto timeout. */
+ ERROR_SYMC_GET_TAG_TIMEOUT, /* return when symc get tag timeout. */
+ ERROR_PKE_LOCK_TIMEOUT, /* return when pke lock timeout. */
+ ERROR_PKE_WAIT_DONE_TIMEOUT, /* return when pke wait done timeout. */
+ ERROR_PKE_ROBUST_WARNING, /* return when pke wait done timeout. */
+ ERROR_RKP_LOCK_TIMEOUT, /* return when rkp lock timeout. */
+ ERROR_RKP_CALC_TIMEOUT, /* return when rkp calculate timeout. */
+ ERROR_OTP_TIMEOUT, /* return when otp wait timeout. */
+};
+
+#define CRYPTO_COMPAT_ERRNO(env, layer, module, err_code) \
+ ((((env) & 0xF) << 28) | (((layer) & 0xF) << 24) | (((module) & 0xF) << 20) | ((err_code) & 0xFF))
+
+/* Notice: you should define CRYPTO_ERROR_ENV as one of ERROR_ENV_XXX before using these macros. */
+#define UAPI_COMPAT_ERRNO(module, err_code) \
+ CRYPTO_COMPAT_ERRNO(CRYPTO_ERROR_ENV, ERROR_LAYER_UAPI, module, err_code)
+
+#define DISPATCH_COMPAT_ERRNO(module, err_code) \
+ CRYPTO_COMPAT_ERRNO(CRYPTO_ERROR_ENV, ERROR_LAYER_DISPATCH, module, err_code)
+
+#define KAPI_COMPAT_ERRNO(module, err_code) \
+ CRYPTO_COMPAT_ERRNO(CRYPTO_ERROR_ENV, ERROR_LAYER_KAPI, module, err_code)
+
+#define DRV_COMPAT_ERRNO(module, err_code) \
+ CRYPTO_COMPAT_ERRNO(CRYPTO_ERROR_ENV, ERROR_LAYER_DRV, module, err_code)
+
+#define HAL_COMPAT_ERRNO(module, err_code) \
+ CRYPTO_COMPAT_ERRNO(CRYPTO_ERROR_ENV, ERROR_LAYER_HAL, module, err_code)
+
+enum {
+ CRYPTO_SUCCESS = 0,
+ CRYPTO_FAILURE = 0xffffffff,
+};
+
+#endif
\ No newline at end of file
--- /dev/null
+/**
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n
+ *
+ * Description: crypto hash struct header. \n
+ * Author: @CompanyNameTag \n
+ * History: \n
+ * 2023-03-22, Create file. \n
+ */
+#ifndef CRYPTO_HASH_STRUCT_H
+#define CRYPTO_HASH_STRUCT_H
+
+#include "crypto_common_struct.h"
+
+/*
+ * Component of crypto_hash_type.
+ * is_hmac(4 bits) | alg(4 bits) | mode(4 bits) | max_message_length(4 bits) | block_size(4 bits) | result_size(12 bits)
+ * is_hmac: h'0 - hash
+ * h'1 - hmac
+ * alg: h'0 - sha1
+ * h'1 - sha2
+ * h'2 - sm3
+ * mode: h'0 - 224
+ * h'1 - 256
+ * h'2 - 384
+ * h'3 - 512
+ * max_message_length:
+ * h'6 - 2**6 -> 64, 最大消息 2**64 Bits. For SHA256.
+ * h'7 - 2**7 -> 128, 最大消息 2**128 Bits. For SHA384/SHA512.
+ * block_size:
+ * h'9 - 2**9 -> 512, Block Size 为 512 Bits. For SHA256.
+ * h'a - 2**10 -> 1024, Block Size 为 1024 Bits. For SHA384/SHA512.
+ * result_size:
+ * h'100 - 256, Result Size 为 256 Bits. For SHA256.
+ * h'180 - 384, Result Size 为 384 Bits. For SHA384.
+ * h'200 - 512, Result Size 为 512 Bits. For SHA512.
+ */
+#define compat_hash_type(is_hmac, alg, mode, max_message_length, block_size, result_size) \
+ ((((is_hmac) & 0xF) << 28) | (((alg) & 0xF) << 24) | (((mode) & 0xF) << 20) | \
+ (((max_message_length) & 0xF) << 16) | (((block_size) & 0xF) << 12) | ((result_size) & 0xFFF))
+
+#define CRYPTO_HASH_TYPE 0
+#define CRYPTO_HMAC_TYPE 1
+#define CRYPTO_IS_HMAC_MASK 0xF0000000
+#define CRYPTO_IS_HMAC_SHIFT 28
+
+#define CRYPTO_HASH_ALG_SHA1 0
+#define CRYPTO_HASH_ALG_SHA2 1
+#define CRYPTO_HASH_ALG_SM3 2
+#define CRYPTO_HASH_ALG_MASK 0x0F000000
+#define CRYPTO_HASH_ALG_SHIFT 24
+
+#define CRYPTO_HASH_MODE_224 0
+#define CRYPTO_HASH_MODE_256 1
+#define CRYPTO_HASH_MODE_384 2
+#define CRYPTO_HASH_MODE_512 3
+#define CRYPTO_HASH_MODE_UNDEF 0xf
+#define CRYPTO_HASH_MODE_MASK 0x00F00000
+#define CRYPTO_HASH_MODE_SHIFT 20
+
+#define CRYPTO_HASH_MAX_MESSAGE_LEN_64BIT 0x6
+#define CRYPTO_HASH_MAX_MESSAGE_LEN_128BIT 0x7
+#define CRYPTO_HASH_MAX_MESSAGE_LEN_MASK 0x000F0000
+#define CRYPTO_HASH_MAX_MESSAGE_LEN_SHIFT 16
+
+#define CRYPTO_HASH_BLOCK_SIZE_512BIT 0x9
+#define CRYPTO_HASH_BLOCK_SIZE_1024BIT 0xa
+#define CRYPTO_HASH_BLOCK_SIZE_MASK 0x0000F000
+#define CRYPTO_HASH_BLOCK_SIZE_SHIFT 12
+
+#define CRYPTO_HASH_RESULT_SIZE_160BIT 0xa0
+#define CRYPTO_HASH_RESULT_SIZE_224BIT 0xe0
+#define CRYPTO_HASH_RESULT_SIZE_256BIT 0x100
+#define CRYPTO_HASH_RESULT_SIZE_384BIT 0x180
+#define CRYPTO_HASH_RESULT_SIZE_512BIT 0x200
+#define CRYPTO_HASH_RESULT_SIZE_MASK 0x00000FFF
+#define CRYPTO_HASH_RESULT_SIZE_SHIFT 0
+
+#define crypto_hash_get_attr(value, mask, shift) (((td_u32)(value) & (td_u32)(mask)) >> (shift))
+#define crypto_hash_macth(value, mask, target, shift) (crypto_hash_get_attr(value, mask, shift) == (target))
+
+#define crypto_hash_get_alg(hash_type) \
+ crypto_hash_get_attr(hash_type, CRYPTO_HASH_ALG_MASK, CRYPTO_HASH_ALG_SHIFT)
+#define crypto_hash_get_mode(hash_type) \
+ crypto_hash_get_attr(hash_type, CRYPTO_HASH_MODE_MASK, CRYPTO_HASH_MODE_SHIFT)
+#define crypto_hash_is_hmac(hash_type) \
+ crypto_hash_macth(hash_type, CRYPTO_IS_HMAC_MASK, CRYPTO_HMAC_TYPE, CRYPTO_IS_HMAC_SHIFT)
+#define crypto_hash_get_message_len(hash_type) \
+ (1 << crypto_hash_get_attr(hash_type, CRYPTO_HASH_MAX_MESSAGE_LEN_MASK, CRYPTO_HASH_MAX_MESSAGE_LEN_SHIFT))
+#define crypto_hash_get_block_size(hash_type) \
+ (1 << crypto_hash_get_attr(hash_type, CRYPTO_HASH_BLOCK_SIZE_MASK, CRYPTO_HASH_BLOCK_SIZE_SHIFT))
+#define crypto_hash_get_result_size(hash_type) \
+ crypto_hash_get_attr(hash_type, CRYPTO_HASH_RESULT_SIZE_MASK, CRYPTO_HASH_RESULT_SIZE_SHIFT)
+
+#define crypto_hash_remove_hmac_flag(hash_type) \
+ ((hash_type) & (0x0FFFFFFF))
+
+typedef enum {
+ /* Hash. */
+ CRYPTO_HASH_TYPE_SHA1 = compat_hash_type(
+ CRYPTO_HASH_TYPE, CRYPTO_HASH_ALG_SHA1, CRYPTO_HASH_MODE_UNDEF, CRYPTO_HASH_MAX_MESSAGE_LEN_64BIT,
+ CRYPTO_HASH_BLOCK_SIZE_512BIT, CRYPTO_HASH_RESULT_SIZE_160BIT
+ ),
+ CRYPTO_HASH_TYPE_SHA224 = compat_hash_type(
+ CRYPTO_HASH_TYPE, CRYPTO_HASH_ALG_SHA2, CRYPTO_HASH_MODE_224, CRYPTO_HASH_MAX_MESSAGE_LEN_64BIT,
+ CRYPTO_HASH_BLOCK_SIZE_512BIT, CRYPTO_HASH_RESULT_SIZE_224BIT
+ ),
+ CRYPTO_HASH_TYPE_SHA256 = compat_hash_type(
+ CRYPTO_HASH_TYPE, CRYPTO_HASH_ALG_SHA2, CRYPTO_HASH_MODE_256, CRYPTO_HASH_MAX_MESSAGE_LEN_64BIT,
+ CRYPTO_HASH_BLOCK_SIZE_512BIT, CRYPTO_HASH_RESULT_SIZE_256BIT
+ ),
+ CRYPTO_HASH_TYPE_SHA384 = compat_hash_type(
+ CRYPTO_HASH_TYPE, CRYPTO_HASH_ALG_SHA2, CRYPTO_HASH_MODE_384, CRYPTO_HASH_MAX_MESSAGE_LEN_128BIT,
+ CRYPTO_HASH_BLOCK_SIZE_1024BIT, CRYPTO_HASH_RESULT_SIZE_384BIT
+ ),
+ CRYPTO_HASH_TYPE_SHA512 = compat_hash_type(
+ CRYPTO_HASH_TYPE, CRYPTO_HASH_ALG_SHA2, CRYPTO_HASH_MODE_512, CRYPTO_HASH_MAX_MESSAGE_LEN_128BIT,
+ CRYPTO_HASH_BLOCK_SIZE_1024BIT, CRYPTO_HASH_RESULT_SIZE_512BIT
+ ),
+ CRYPTO_HASH_TYPE_SM3 = compat_hash_type(
+ CRYPTO_HASH_TYPE, CRYPTO_HASH_ALG_SM3, CRYPTO_HASH_MODE_256, CRYPTO_HASH_MAX_MESSAGE_LEN_64BIT,
+ CRYPTO_HASH_BLOCK_SIZE_512BIT, CRYPTO_HASH_RESULT_SIZE_256BIT
+ ),
+
+ /* HMAC. */
+ CRYPTO_HASH_TYPE_HMAC_SHA1 = compat_hash_type(
+ CRYPTO_HMAC_TYPE, CRYPTO_HASH_ALG_SHA1, CRYPTO_HASH_MODE_UNDEF, CRYPTO_HASH_MAX_MESSAGE_LEN_64BIT,
+ CRYPTO_HASH_BLOCK_SIZE_512BIT, CRYPTO_HASH_RESULT_SIZE_160BIT
+ ),
+ CRYPTO_HASH_TYPE_HMAC_SHA224 = compat_hash_type(
+ CRYPTO_HMAC_TYPE, CRYPTO_HASH_ALG_SHA2, CRYPTO_HASH_MODE_224, CRYPTO_HASH_MAX_MESSAGE_LEN_64BIT,
+ CRYPTO_HASH_BLOCK_SIZE_512BIT, CRYPTO_HASH_RESULT_SIZE_224BIT
+ ),
+ CRYPTO_HASH_TYPE_HMAC_SHA256 = compat_hash_type(
+ CRYPTO_HMAC_TYPE, CRYPTO_HASH_ALG_SHA2, CRYPTO_HASH_MODE_256, CRYPTO_HASH_MAX_MESSAGE_LEN_64BIT,
+ CRYPTO_HASH_BLOCK_SIZE_512BIT, CRYPTO_HASH_RESULT_SIZE_256BIT
+ ),
+ CRYPTO_HASH_TYPE_HMAC_SHA384 = compat_hash_type(
+ CRYPTO_HMAC_TYPE, CRYPTO_HASH_ALG_SHA2, CRYPTO_HASH_MODE_384, CRYPTO_HASH_MAX_MESSAGE_LEN_128BIT,
+ CRYPTO_HASH_BLOCK_SIZE_1024BIT, CRYPTO_HASH_RESULT_SIZE_384BIT
+ ),
+ CRYPTO_HASH_TYPE_HMAC_SHA512 = compat_hash_type(
+ CRYPTO_HMAC_TYPE, CRYPTO_HASH_ALG_SHA2, CRYPTO_HASH_MODE_512, CRYPTO_HASH_MAX_MESSAGE_LEN_128BIT,
+ CRYPTO_HASH_BLOCK_SIZE_1024BIT, CRYPTO_HASH_RESULT_SIZE_512BIT
+ ),
+ CRYPTO_HASH_TYPE_HMAC_SM3 = compat_hash_type(
+ CRYPTO_HMAC_TYPE, CRYPTO_HASH_ALG_SM3, CRYPTO_HASH_MODE_256, CRYPTO_HASH_MAX_MESSAGE_LEN_64BIT,
+ CRYPTO_HASH_BLOCK_SIZE_512BIT, CRYPTO_HASH_RESULT_SIZE_256BIT
+ ),
+
+ CRYPTO_HASH_TYPE_INVALID = 0xffffffff,
+} crypto_hash_type;
+
+typedef struct {
+ td_u8 *key;
+ td_u32 key_len;
+ td_handle drv_keyslot_handle;
+ crypto_hash_type hash_type;
+ td_bool is_keyslot;
+ td_bool is_long_term;
+} crypto_hash_attr;
+
+/* Structure for HASH. */
+#define CRYPTO_HASH_RESULT_SIZE_MAX 64 // for SHA-512
+#define CRYPTO_HASH_RESULT_SIZE_MAX_IN_WORD 16 // for SHA-512
+#define CRYPTO_HASH_BLOCK_SIZE_MAX 128 // for SHA-512
+
+typedef struct {
+ td_u32 length[2];
+ td_u32 state[CRYPTO_HASH_RESULT_SIZE_MAX_IN_WORD];
+ td_u32 tail_len;
+ crypto_hash_type hash_type;
+ td_u8 o_key_pad[CRYPTO_HASH_BLOCK_SIZE_MAX];
+ td_u8 i_key_pad[CRYPTO_HASH_BLOCK_SIZE_MAX];
+ td_u8 tail[CRYPTO_HASH_BLOCK_SIZE_MAX];
+} crypto_hash_clone_ctx;
+
+typedef struct {
+ crypto_hash_type hmac_type;
+ td_u8 *salt;
+ td_u32 salt_length;
+ td_u8 *ikm;
+ td_u32 ikm_length;
+} crypto_hkdf_extract_t;
+
+typedef struct {
+ crypto_hash_type hmac_type;
+ td_u8 *prk;
+ td_u32 prk_length;
+ td_u8 *info;
+ td_u32 info_length;
+} crypto_hkdf_expand_t;
+
+typedef struct {
+ crypto_hash_type hmac_type;
+ td_u8 *salt;
+ td_u32 salt_length;
+ td_u8 *ikm;
+ td_u32 ikm_length;
+ td_u8 *info;
+ td_u32 info_length;
+} crypto_hkdf_t;
+
+#endif
--- /dev/null
+/**
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n
+ *
+ * Description: crypto type header. \n
+ * Author: @CompanyNameTag \n
+ * History: \n
+ * 2023-03-22, Create file. \n
+ */
+#ifndef CRYPTO_TYPE_H
+#define CRYPTO_TYPE_H
+
+#include "td_type.h"
+
+#include "crypto_common_def.h"
+#include "crypto_common_macro.h"
+#include "crypto_errno.h"
+
+#endif
\ No newline at end of file
--- /dev/null
+/**\r
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n\r
+ *\r
+ * Description: Provides IPC source \n\r
+ * Author: @CompanyNameTag \n\r
+ * History: \n\r
+ * 2025-04-18, Create file. \n\r
+ */\r
+#ifndef TD_TYPE_H\r
+#define TD_TYPE_H\r
+\r
+#include <stdint.h>\r
+\r
+typedef unsigned char td_uchar;\r
+typedef unsigned char td_u8;\r
+typedef unsigned short td_u16;\r
+typedef unsigned int td_u32;\r
+typedef unsigned long long td_u64;\r
+typedef unsigned long td_ulong;\r
+typedef char td_char;\r
+typedef signed char td_s8;\r
+typedef short td_s16;\r
+typedef int td_s32;\r
+typedef long long td_s64;\r
+typedef long td_slong;\r
+typedef float td_float;\r
+typedef double td_double;\r
+typedef void td_void;\r
+typedef td_u32 td_handle;\r
+typedef td_u8 td_byte;\r
+typedef td_byte* td_pbyte;\r
+typedef void* td_pvoid;\r
+typedef volatile td_u32 td_u32_reg;\r
+typedef unsigned long td_size_t;\r
+typedef signed long td_ssize_t;\r
+typedef unsigned long td_length_t;\r
+\r
+#define EOK 0\r
+\r
+typedef enum {\r
+ TD_FALSE = 0,\r
+ TD_TRUE = 1,\r
+} td_bool;\r
+\r
+#define TD_SUCCESS 0\r
+#define TD_FAILURE (0xFFFFFFFF)\r
+\r
+#define TD_NULL (void *)0\r
+#ifndef NULL\r
+#define NULL (void *)0\r
+#endif\r
+\r
+#endif
\ No newline at end of file
--- /dev/null
+/**
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n
+ *
+ * Description: Provides IPC source \n
+ * Author: @CompanyNameTag \n
+ * History: \n
+ * 2025-04-18, Create file. \n
+ */
+#ifndef DRV_HASH_H
+#define DRV_HASH_H
+
+#include "crypto_type.h"
+#include "crypto_hash_struct.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+int32_t drv_cipher_hkdf(crypto_hkdf_t *hkdf_param, uint8_t *okm, uint32_t okm_length);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif
\ No newline at end of file
--- /dev/null
+/**
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n
+ *
+ * Description: Provides IPC source \n
+ * Author: @CompanyNameTag \n
+ * History: \n
+ * 2025-04-18, Create file. \n
+ */
+#ifndef DRV_SYMC_AEAD_H
+#define DRV_SYMC_AEAD_H
+
+#include "crypto_type.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+/* old. */
+
+int32_t drv_cipher_symc_gcm_encrypt(
+ uint8_t *key, uint32_t key_len, uint32_t keyslot_handle,
+ const uint8_t *iv, uint32_t iv_len,
+ const uint8_t *aad, uint32_t aad_len,
+ const uint8_t *plain_text, uint8_t *cipher_text, uint32_t data_len,
+ uint8_t *tag, uint32_t tag_len
+);
+
+int32_t drv_cipher_symc_gcm_decrypt_verify(
+ uint8_t *key, uint32_t key_len, uint32_t keyslot_handle,
+ const uint8_t *iv, uint32_t iv_len,
+ const uint8_t *aad, uint32_t aad_len,
+ const uint8_t *cipher_text, uint8_t *plain_text, uint32_t data_len,
+ const uint8_t *tag, uint32_t tag_len
+);
+
+/* new. */
+int32_t drv_cipher_symc_gcm_create(uint32_t *handle,
+ uint8_t *key, uint32_t key_len, uint32_t keyslot_handle,
+ const uint8_t *iv, uint32_t iv_len,
+ const uint8_t *aad, uint32_t aad_len,
+ uint32_t tag_len
+);
+
+int32_t drv_cipher_symc_gcm_destroy(uint32_t handle);
+
+int32_t drv_cipher_symc_gcm_encrypt_update(uint32_t handle,
+ const uint8_t *plain_text, uint8_t *cipher_text, uint32_t data_len
+);
+
+int32_t drv_cipher_symc_gcm_encrypt_get_tag(uint32_t handle,
+ uint8_t *tag, uint32_t tag_len
+);
+
+int32_t drv_cipher_symc_gcm_decrypt_set_tag(uint32_t handle,
+ const uint8_t *tag, uint32_t tag_len
+);
+
+int32_t drv_cipher_symc_gcm_decrypt_update(uint32_t handle,
+ const uint8_t *cipher_text, uint8_t *plain_text, uint32_t data_len
+);
+
+int32_t drv_cipher_symc_gcm_decrypt_verify_tag(uint32_t handle);
+
+void crypto_drv_init(void);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif
\ No newline at end of file
--- /dev/null
+/**\r
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n\r
+ *\r
+ * Description: Provides IPC source \n\r
+ * Author: @CompanyNameTag \n\r
+ * History: \n\r
+ * 2025-04-18, Create file. \n\r
+ */\r
+#include "cipher_aead.h"\r
+#include "drv_symc_aead.h"\r
+\r
+#include "sl_common.h"\r
+\r
+errcode_t uapi_drv_cipher_symc_gcm_encrypt(\r
+ uint8_t *key, uint32_t key_len, uint32_t keyslot_handle,\r
+ const uint8_t *iv, uint32_t iv_len,\r
+ const uint8_t *aad, uint32_t aad_len,\r
+ const uint8_t *plain_text, uint8_t *cipher_text, uint32_t data_len,\r
+ uint8_t *tag, uint32_t tag_len)\r
+{\r
+ int32_t ret = drv_cipher_symc_gcm_encrypt(\r
+ key, key_len, keyslot_handle,\r
+ iv, iv_len,\r
+ aad, aad_len,\r
+ plain_text, cipher_text, data_len,\r
+ tag, tag_len);\r
+ return crypto_sl_common_get_errcode(ret);\r
+}\r
+\r
+errcode_t uapi_drv_cipher_symc_gcm_decrypt_verify(\r
+ uint8_t *key, uint32_t key_len, uint32_t keyslot_handle,\r
+ const uint8_t *iv, uint32_t iv_len,\r
+ const uint8_t *aad, uint32_t aad_len,\r
+ const uint8_t *cipher_text, uint8_t *plain_text, uint32_t data_len,\r
+ const uint8_t *tag, uint32_t tag_len)\r
+{\r
+ int32_t ret = drv_cipher_symc_gcm_decrypt_verify(\r
+ key, key_len, keyslot_handle,\r
+ iv, iv_len,\r
+ aad, aad_len,\r
+ cipher_text, plain_text, data_len,\r
+ tag, tag_len);\r
+ return crypto_sl_common_get_errcode(ret);\r
+}\r
+\r
+errcode_t uapi_drv_cipher_symc_gcm_create(uint32_t *handle,\r
+ uint8_t *key, uint32_t key_len, uint32_t keyslot_handle,\r
+ const uint8_t *iv, uint32_t iv_len,\r
+ const uint8_t *aad, uint32_t aad_len,\r
+ uint32_t tag_len)\r
+{\r
+ int32_t ret = drv_cipher_symc_gcm_create(\r
+ handle, key, key_len, keyslot_handle,\r
+ iv, iv_len,\r
+ aad, aad_len,\r
+ tag_len);\r
+ return crypto_sl_common_get_errcode(ret);\r
+}\r
+\r
+errcode_t uapi_drv_cipher_symc_gcm_destroy(uint32_t handle)\r
+{\r
+ int32_t ret = drv_cipher_symc_gcm_destroy(handle);\r
+ return crypto_sl_common_get_errcode(ret);\r
+}\r
+\r
+errcode_t uapi_drv_cipher_symc_gcm_encrypt_update(uint32_t handle,\r
+ const uint8_t *plain_text, uint8_t *cipher_text, uint32_t data_len)\r
+{\r
+ int32_t ret = drv_cipher_symc_gcm_encrypt_update(handle, plain_text, cipher_text, data_len);\r
+ return crypto_sl_common_get_errcode(ret);\r
+}\r
+\r
+errcode_t uapi_drv_cipher_symc_gcm_encrypt_get_tag(uint32_t handle,\r
+ uint8_t *tag, uint32_t tag_len)\r
+{\r
+ int32_t ret = drv_cipher_symc_gcm_encrypt_get_tag(handle, tag, tag_len);\r
+ return crypto_sl_common_get_errcode(ret);\r
+}\r
+\r
+errcode_t uapi_drv_cipher_symc_gcm_decrypt_set_tag(uint32_t handle,\r
+ const uint8_t *tag, uint32_t tag_len)\r
+{\r
+ int32_t ret = drv_cipher_symc_gcm_decrypt_set_tag(handle, tag, tag_len);\r
+ return crypto_sl_common_get_errcode(ret);\r
+}\r
+\r
+errcode_t uapi_drv_cipher_symc_gcm_decrypt_update(uint32_t handle,\r
+ const uint8_t *cipher_text, uint8_t *plain_text, uint32_t data_len)\r
+{\r
+ int32_t ret = drv_cipher_symc_gcm_decrypt_update(handle, cipher_text, plain_text, data_len);\r
+ return crypto_sl_common_get_errcode(ret);\r
+}\r
+\r
+errcode_t uapi_drv_cipher_symc_gcm_decrypt_verify_tag(uint32_t handle)\r
+{\r
+ int32_t ret = drv_cipher_symc_gcm_decrypt_verify_tag(handle);\r
+ return crypto_sl_common_get_errcode(ret);\r
+}
\ No newline at end of file
--- /dev/null
+/**\r
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n\r
+ *\r
+ * Description: Provides IPC source \n\r
+ * Author: @CompanyNameTag \n\r
+ * History: \n\r
+ * 2025-04-18, Create file. \n\r
+ */\r
+#include "security_init.h"\r
+\r
+#include "bsl_sal.h"\r
+#include "drv_symc_aead.h"\r
+\r
+#include "crypto_osal_lib.h"\r
+\r
+static void *inner_malloc(uint32_t size)\r
+{\r
+ return malloc(size);\r
+}\r
+\r
+static void inner_free(void *addr)\r
+{\r
+ free(addr);\r
+}\r
+\r
+void uapi_drv_cipher_env_init(void)\r
+{\r
+ BSL_SAL_MemCallback mem_callback;\r
+ mem_callback.pfMalloc = inner_malloc;\r
+ mem_callback.pfFree = inner_free;\r
+\r
+ (void)BSL_SAL_RegMemCallback(&mem_callback);\r
+}\r
+\r
+void uapi_drv_cipher_env_deinit(void)\r
+{\r
+ BSL_SAL_MemCallback mem_callback;\r
+ mem_callback.pfMalloc = NULL;\r
+ mem_callback.pfFree = NULL;\r
+\r
+ (void)BSL_SAL_RegMemCallback(&mem_callback);\r
+}
\ No newline at end of file
--- /dev/null
+/**\r
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n\r
+ *\r
+ * Description: Provides IPC source \n\r
+ * Author: @CompanyNameTag \n\r
+ * History: \n\r
+ * 2025-04-18, Create file. \n\r
+ */\r
+#include "cipher.h"\r
+#include "drv_hkdf.h"\r
+\r
+#include "sl_common.h"\r
+\r
+errcode_t uapi_drv_cipher_hkdf(uapi_drv_cipher_hkdf_t *hkdf_param, uint8_t *okm, uint32_t okm_length)\r
+{\r
+ int32_t ret = drv_cipher_hkdf((crypto_hkdf_t *)(uintptr_t)hkdf_param, okm, okm_length);\r
+ return crypto_sl_common_get_errcode(ret);\r
+}
\ No newline at end of file
--- /dev/null
+/**
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n
+ *
+ * Description: Provides common utils for security_unified service layer. \n
+ * Author: @CompanyNameTag \n
+ * History: \n
+ * 2023-03-14, Create file. \n
+ */
+#include "sl_common.h"
+#include "crypto_errno.h"
+#include "crypto_common_macro.h"
+
+typedef struct crypto_errcode_item {
+ int32_t from_errcode;
+ errcode_t to_errcode;
+} crypto_errcode_item_t;
+
+#define ERROR_SECURITY_UNIFIED 0x80001500
+errcode_t crypto_sl_common_get_errcode(int32_t from_errcode)
+{
+ errcode_t ret = from_errcode & 0xFF;
+ if ((uint32_t)from_errcode == CRYPTO_SUCCESS) {
+ return ERRCODE_SUCC;
+ } else if ((uint32_t)from_errcode == CRYPTO_FAILURE) {
+ return ERRCODE_FAIL;
+ }
+ return ERROR_SECURITY_UNIFIED + ret;
+}
--- /dev/null
+/**
+ * Copyright (c) @CompanyNameMagicTag 2023-2023. All rights reserved. \n
+ *
+ * Description: Provides common utils for security_unified service layer. \n
+ * Author: @CompanyNameTag \n
+ * History: \n
+ * 2023-03-14, Create file. \n
+ */
+#ifndef SL_COMMON_H
+#define SL_COMMON_H
+
+#include <stdint.h>
+#include "errcode.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+/**
+ * @if Eng
+ * @brief Convert security-driven error codes to standard error codes.
+ * @param [in] from_errcode Error codes returned by the security driver interface.
+ * @retval Converted error code. For details, see @ref errcode_t
+ * @else
+ * @brief 将安全驱动的错误码转换成标准错误码
+ * @param [in] from_errcode 安全驱动接口返回的错误码
+ * @retval 转换后的错误码，参考 @ref errcode_t
+ * @endif
+ */
+errcode_t crypto_sl_common_get_errcode(int32_t from_errcode);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif
\ No newline at end of file
#define DMA_SPI_TRANSFER_WIDTH_WORD 4
#define DMA_SPI_TRANSFER_WIDTH_HALF_WORD 2
-#define DMA_SPI_TRANSFER_TIMEOUT_MS 1000
typedef struct spi_dma_trans_inf {
bool trans_succ;
spi_tx_fragment_t *current_tx_fragment; /*!< Current TX fragment being transmitted. */
spi_tx_fragment_t *free_tx_fragment; /*!< The unused TX fragment admin blocks available
for re-use/freeing. */
- bool is_enable; /*!< TX interrupt transfer enable. */
uint16_t fragments_to_process; /*!< Number of fragments to process including the current one. */
uint32_t current_tx_fragment_pos; /*!< Index of the current position of the next byte to be
transmitted in the current TX fragment
uint32_t new_rx_pos; /*!< Index to the position in the RX buffer that is where new data
should be put if (new_rx_pos == 0) the buffer is empty. */
uint8_t *rx_buffer; /*!< The RX data buffer. */
- bool is_enable; /*!< RX interrupt transfer enable. */
} spi_rx_state_t;
-/**
- * @brief Internal SPI TX configuration pointers.
- */
-static spi_tx_state_t *g_spi_tx_state[SPI_BUS_MAX_NUM];
-/**
- * @brief Internal SPI TX configuration pointers.
- */
-static spi_rx_state_t *g_spi_rx_state[SPI_BUS_MAX_NUM];
+static bool g_spi_tx_int_flag[SPI_BUS_MAX_NUM];
+static bool g_spi_rx_int_flag[SPI_BUS_MAX_NUM];
/**
* @brief Internal SPI TX configuration.
*/
-static spi_tx_state_t g_spi_tx_state_array[SPI_BUS_MAX_NUM];
+static spi_tx_state_t g_spi_tx_state[SPI_BUS_MAX_NUM];
/**
* @brief Internal SPI RX configuration.
*/
-static spi_rx_state_t g_spi_rx_state_array[SPI_BUS_MAX_NUM];
+static spi_rx_state_t g_spi_rx_state[SPI_BUS_MAX_NUM];
+
#endif /* CONFIG_SPI_SUPPORT_INTERRUPT */
#endif /* CONFIG_SPI_SUPPORT_MASTER || CONFIG_SPI_SUPPORT_SLAVE */
static osal_mutex g_spi_mutex[SPI_BUS_MAX_NUM] = { NULL };
#endif /* CONFIG_SPI_SUPPORT_CONCURRENCY */
+#if defined(CONFIG_SPI_SUPPORT_CONCURRENCY) && (CONFIG_SPI_SUPPORT_CONCURRENCY == 1)
+static bool spi_mutex_lock(spi_bus_t bus)
+{
+ if (osal_mutex_lock_timeout(&g_spi_mutex[bus], OSAL_MUTEX_WAIT_FOREVER) != OSAL_SUCCESS) {
+ return false;
+ }
+ return true;
+}
+#endif /* CONFIG_SPI_SUPPORT_CONCURRENCY */
+
+static void spi_mutex_unlock(spi_bus_t bus)
+{
+#if defined(CONFIG_SPI_SUPPORT_CONCURRENCY) && (CONFIG_SPI_SUPPORT_CONCURRENCY == 1)
+ osal_mutex_unlock(&g_spi_mutex[bus]);
+#endif /* CONFIG_SPI_SUPPORT_CONCURRENCY */
+ unused(bus);
+}
+
+#if defined(CONFIG_SPI_SUPPORT_MASTER) || defined(CONFIG_SPI_SUPPORT_SLAVE)
+static uint32_t spi_get_attr_tmod(spi_bus_t bus)
+{
+ spi_attr_t attr; /* uapi_spi_get_attr will copy attr from hal, no need init to 0. */
+
+ if (uapi_spi_get_attr(bus, &attr) != ERRCODE_SUCC) {
+ return 0;
+ }
+ return attr.tmod;
+}
+
+static errcode_t spi_param_check(spi_bus_t bus, spi_mode_t spi_mode, hal_spi_trans_mode_t trans_mode)
+{
+ if (spi_porting_get_device_mode(bus) != spi_mode) {
+ return ERRCODE_SPI_MODE_MISMATCH;
+ }
+
+ if (spi_get_attr_tmod(bus) == trans_mode) {
+ return ERRCODE_SPI_INVALID_TMODE;
+ }
+
+ return ERRCODE_SUCC;
+}
+
+static errcode_t spi_fifo_check(spi_bus_t bus)
+{
+ errcode_t ret = ERRCODE_SUCC;
+#if defined(CONFIG_SPI_SUPPORT_INTERRUPT) && (CONFIG_SPI_SUPPORT_INTERRUPT == 1)
+ if (!g_spi_tx_int_flag[bus]) {
+ if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) {
+ ret = ERRCODE_SPI_TIMEOUT;
+ }
+ }
+#else
+ if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) {
+ ret = ERRCODE_SPI_TIMEOUT;
+ }
+#endif /* CONFIG_SPI_SUPPORT_INTERRUPT */
+ return ret;
+}
+
+static errcode_t spi_param_check_read(spi_bus_t bus, spi_mode_t spi_mode, hal_spi_trans_mode_t trans_mode,
+ const spi_xfer_data_t *data, bool check_fifo)
+{
+ if (bus >= SPI_BUS_MAX_NUM) {
+ return ERRCODE_INVALID_PARAM;
+ }
+
+ if (data == NULL || data->rx_buff == NULL || data->rx_bytes == 0) {
+ return ERRCODE_INVALID_PARAM;
+ }
+
+ errcode_t ret = spi_param_check(bus, spi_mode, trans_mode);
+ if (ret != ERRCODE_SUCC) {
+ return ret;
+ }
+ if (check_fifo) {
+ if (spi_fifo_check(bus) != ERRCODE_SUCC) {
+ return ERRCODE_SPI_TIMEOUT;
+ }
+ }
+#if defined(CONFIG_SPI_SUPPORT_CONCURRENCY) && (CONFIG_SPI_SUPPORT_CONCURRENCY == 1)
+ if (!spi_mutex_lock(bus)) {
+ return ERRCODE_SPI_TIMEOUT;
+ }
+#endif /* CONFIG_SPI_SUPPORT_CONCURRENCY */
+
+ return ERRCODE_SUCC;
+}
+
+static errcode_t spi_param_check_write(spi_bus_t bus, spi_mode_t spi_mode, hal_spi_trans_mode_t trans_mode,
+ const spi_xfer_data_t *data, bool check_fifo)
+{
+ /* data->tx_buff maybe NULL and data->tx_bytes maybe 0, as flash will write cmd only in master mode. */
+ if (bus >= SPI_BUS_MAX_NUM || data == NULL) {
+ return ERRCODE_INVALID_PARAM;
+ }
+
+ errcode_t ret = spi_param_check(bus, spi_mode, trans_mode);
+ if (ret != ERRCODE_SUCC) {
+ return ret;
+ }
+
+ if (check_fifo) {
+ if (spi_fifo_check(bus) != ERRCODE_SUCC) {
+ return ERRCODE_SPI_TIMEOUT;
+ }
+ }
+#if defined(CONFIG_SPI_SUPPORT_CONCURRENCY) && (CONFIG_SPI_SUPPORT_CONCURRENCY == 1)
+ if (!spi_mutex_lock(bus)) {
+ return ERRCODE_SPI_TIMEOUT;
+ }
+#endif /* CONFIG_SPI_SUPPORT_CONCURRENCY */
+
+ return ERRCODE_SUCC;
+}
+
+#endif /* CONFIG_SPI_SUPPORT_MASTER || CONFIG_SPI_SUPPORT_SLAVE */
+
#if defined(CONFIG_SPI_SUPPORT_INTERRUPT) && (CONFIG_SPI_SUPPORT_INTERRUPT == 1)
static bool spi_helper_add_fragment(spi_bus_t bus, const void *buffer, uint32_t length)
{
spi_tx_fragment_t *fragment = NULL;
- if (g_spi_tx_state[bus]->fragments_to_process >= SPI_MAX_NUMBER_OF_FRAGMENTS) {
+ if (g_spi_tx_state[bus].fragments_to_process >= SPI_MAX_NUMBER_OF_FRAGMENTS) {
return false;
} else {
/* If we have fragments left add it.
Put it on the queue and populate the fragment. */
- fragment = g_spi_tx_state[bus]->free_tx_fragment;
+ fragment = g_spi_tx_state[bus].free_tx_fragment;
fragment->data = (uint8_t *)buffer;
fragment->data_length = length;
/* Update the counters */
- g_spi_tx_state[bus]->free_tx_fragment++;
- if (g_spi_tx_state[bus]->free_tx_fragment >=
- g_spi_tx_state[bus]->fragment_buffer + SPI_MAX_NUMBER_OF_FRAGMENTS) {
- g_spi_tx_state[bus]->free_tx_fragment = g_spi_tx_state[bus]->fragment_buffer; /* wrapping */
+ g_spi_tx_state[bus].free_tx_fragment++;
+ if (g_spi_tx_state[bus].free_tx_fragment >=
+ g_spi_tx_state[bus].fragment_buffer + SPI_MAX_NUMBER_OF_FRAGMENTS) {
+ g_spi_tx_state[bus].free_tx_fragment = g_spi_tx_state[bus].fragment_buffer; /* wrapping */
}
- g_spi_tx_state[bus]->fragments_to_process++;
+ g_spi_tx_state[bus].fragments_to_process++;
}
return true;
}
static inline bool spi_helper_is_the_current_fragment_the_last_to_process(spi_bus_t bus)
{
- return (g_spi_tx_state[bus]->fragments_to_process == 1);
+ return (g_spi_tx_state[bus].fragments_to_process == 1);
}
static inline bool spi_helper_are_there_fragments_to_process(spi_bus_t bus)
{
- return (g_spi_tx_state[bus]->fragments_to_process > 0);
+ return (g_spi_tx_state[bus].fragments_to_process > 0);
}
static bool spi_helper_send_next_char(spi_bus_t bus, uint32_t frame_bytes)
uint32_t current_fragment_pos;
spi_xfer_data_t data;
- current_fragment = g_spi_tx_state[bus]->current_tx_fragment;
- current_fragment_pos = g_spi_tx_state[bus]->current_tx_fragment_pos;
+ current_fragment = g_spi_tx_state[bus].current_tx_fragment;
+ current_fragment_pos = g_spi_tx_state[bus].current_tx_fragment_pos;
data.tx_buff = ¤t_fragment->data[current_fragment_pos];
data.tx_bytes = frame_bytes;
g_hal_funcs->write(bus, &data, CONFIG_SPI_MAX_TIMEOUT);
/* update the counters */
- g_spi_tx_state[bus]->current_tx_fragment_pos += frame_bytes;
+ g_spi_tx_state[bus].current_tx_fragment_pos += frame_bytes;
- return (g_spi_tx_state[bus]->current_tx_fragment_pos >= current_fragment->data_length);
+ return (g_spi_tx_state[bus].current_tx_fragment_pos >= current_fragment->data_length);
}
-static inline void spi_helper_invoke_current_fragment_callback(spi_bus_t bus)
+static void spi_helper_invoke_current_fragment_callback(spi_bus_t bus)
{
- spi_tx_fragment_t *current_fragment = g_spi_tx_state[bus]->current_tx_fragment;
+ spi_tx_fragment_t *current_fragment = g_spi_tx_state[bus].current_tx_fragment;
/* Call any TX data release call-back */
- if (g_spi_tx_state[bus]->tx_callback != NULL) {
- g_spi_tx_state[bus]->tx_callback(current_fragment->data, current_fragment->data_length);
+ if (g_spi_tx_state[bus].tx_callback != NULL) {
+ g_spi_tx_state[bus].tx_callback(current_fragment->data, current_fragment->data_length);
}
}
-static inline void spi_helper_move_to_next_fragment(spi_bus_t bus)
+static void spi_helper_move_to_next_fragment(spi_bus_t bus)
{
/* Move onto the next fragment and re-set the position to zero */
- g_spi_tx_state[bus]->current_tx_fragment++;
- if (g_spi_tx_state[bus]->current_tx_fragment >=
- g_spi_tx_state[bus]->fragment_buffer + SPI_MAX_NUMBER_OF_FRAGMENTS) {
- g_spi_tx_state[bus]->current_tx_fragment = g_spi_tx_state[bus]->fragment_buffer; /* wrapping */
+ g_spi_tx_state[bus].current_tx_fragment++;
+ if (g_spi_tx_state[bus].current_tx_fragment >=
+ g_spi_tx_state[bus].fragment_buffer + SPI_MAX_NUMBER_OF_FRAGMENTS) {
+ g_spi_tx_state[bus].current_tx_fragment = g_spi_tx_state[bus].fragment_buffer; /* wrapping */
}
- g_spi_tx_state[bus]->current_tx_fragment_pos = 0; /* reset the current fragment */
- g_spi_tx_state[bus]->fragments_to_process--; /* one fragment less to process */
+ g_spi_tx_state[bus].current_tx_fragment_pos = 0; /* reset the current fragment */
+ g_spi_tx_state[bus].fragments_to_process--; /* one fragment less to process */
}
static void spi_tx_isr(spi_bus_t bus)
{
bool tx_fifo_full = false;
- hal_spi_attr_t attr = { 0 };
+ hal_spi_attr_t attr; /* will copy attr from hal, no need init to 0. */
g_hal_funcs->ctrl(bus, SPI_CTRL_GET_ATTR, (uintptr_t)&attr);
uint32_t frame_bytes = hal_spi_frame_size_trans_to_frame_bytes(attr.frame_size);
return;
}
+ if (g_spi_tx_state[bus].current_tx_fragment_pos == 0) {
+ if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) {
+ return;
+ }
+ }
g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_TX_FIFO_FULL, (uintptr_t)&tx_fifo_full);
/* Populate the SPI TX FIFO if there is data to send */
while (!tx_fifo_full) {
static inline void spi_rx_buffer_release(spi_bus_t bus)
{
- g_spi_rx_state[bus]->new_rx_pos = 0;
+ g_spi_rx_state[bus].new_rx_pos = 0;
}
static inline bool spi_rx_buffer_has_free_space(spi_bus_t bus)
{
- return (g_spi_rx_state[bus]->new_rx_pos < g_spi_rx_state[bus]->rx_buffer_size);
+ return (g_spi_rx_state[bus].new_rx_pos < g_spi_rx_state[bus].rx_buffer_size);
+}
+
+static void spi_rx_finish_clear_ndf(spi_bus_t bus)
+{
+ spi_attr_t attr; /* uapi_spi_get_attr will copy attr from hal, no need init to 0. */
+ if (uapi_spi_get_attr(bus, &attr) != ERRCODE_SUCC) {
+ return;
+ }
+ attr.ndf = 1;
+ if (uapi_spi_set_attr(bus, &attr) != ERRCODE_SUCC) {
+ return;
+ }
}
static void spi_rx_isr(spi_bus_t bus)
{
- bool rx_fifo_empty = false;
+ if (g_spi_rx_state[bus].rx_callback == NULL) {
+ return;
+ }
spi_xfer_data_t data;
- uint32_t rx_buff = 0;
- uint32_t frame_bytes;
- hal_spi_attr_t attr = { 0 };
- g_hal_funcs->ctrl(bus, SPI_CTRL_GET_ATTR, (uintptr_t)&attr);
- frame_bytes = hal_spi_frame_size_trans_to_frame_bytes(attr.frame_size);
-
- data.rx_bytes = frame_bytes;
- data.rx_buff = (uint8_t *)&rx_buff;
- g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_RX_FIFO_EMPTY, (uintptr_t)&rx_fifo_empty);
- /* Check that the SPI is opened */
- while (!rx_fifo_empty) {
- /* Read the data out of the SPI to clear the interrupt */
- /* Using a volatile variable to ensure the read always happens */
- g_hal_funcs->read(bus, &data, CONFIG_SPI_MAX_TIMEOUT);
- /* Only bother to try and record SPI data it there is an RX callback registered */
- if (g_spi_rx_state[bus]->rx_callback == NULL) {
- g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_RX_FIFO_EMPTY, (uintptr_t)&rx_fifo_empty);
- break;
- }
- /* There is some space in the RX buffer so put the data in and move the pointers */
- for (uint32_t i = 0; i < frame_bytes; i++) {
- g_spi_rx_state[bus]->rx_buffer[g_spi_rx_state[bus]->new_rx_pos] = *(data.rx_buff + i);
- g_spi_rx_state[bus]->new_rx_pos++;
- }
- if (spi_rx_buffer_has_free_space(bus) == false) {
- g_hal_funcs->ctrl(bus, SPI_CTRL_EN_RXFI_INT, 0);
- g_spi_rx_state[bus]->rx_callback(g_spi_rx_state[bus]->rx_buffer, g_spi_rx_state[bus]->new_rx_pos, false);
- spi_rx_buffer_release(bus);
- break;
- }
- g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_RX_FIFO_EMPTY, (uintptr_t)&rx_fifo_empty);
+ data.rx_bytes = g_spi_rx_state[bus].rx_buffer_size - g_spi_rx_state[bus].new_rx_pos;
+ data.rx_buff = g_spi_rx_state[bus].rx_buffer + g_spi_rx_state[bus].new_rx_pos;
+
+ if (g_hal_funcs->read(bus, &data, 0) != ERRCODE_SUCC) {
+ return;
+ }
+ g_spi_rx_state[bus].new_rx_pos = g_spi_rx_state[bus].rx_buffer_size - data.rx_bytes;
+
+ if (!spi_rx_buffer_has_free_space(bus)) {
+ g_hal_funcs->ctrl(bus, SPI_CTRL_EN_RXFI_INT, 0);
+ g_spi_rx_state[bus].rx_callback(g_spi_rx_state[bus].rx_buffer, g_spi_rx_state[bus].new_rx_pos, false);
+ spi_rx_buffer_release(bus);
+ spi_rx_finish_clear_ndf(bus);
}
}
static void spi_config_tx_state(spi_bus_t bus)
{
/* Configure TX state structure */
- g_spi_tx_state[bus] = &g_spi_tx_state_array[bus];
- g_spi_tx_state[bus]->current_tx_fragment = g_spi_tx_state[bus]->fragment_buffer; /* the queue is empty */
- g_spi_tx_state[bus]->free_tx_fragment = g_spi_tx_state[bus]->fragment_buffer; /* the queue is empty */
+ g_spi_tx_state[bus].current_tx_fragment = g_spi_tx_state[bus].fragment_buffer; /* the queue is empty */
+ g_spi_tx_state[bus].free_tx_fragment = g_spi_tx_state[bus].fragment_buffer; /* the queue is empty */
}
#endif /* CONFIG_SPI_SUPPORT_INTERRUPT */
unused(bus);
}
-#if defined(CONFIG_SPI_SUPPORT_CONCURRENCY) && (CONFIG_SPI_SUPPORT_CONCURRENCY == 1)
-static bool spi_mutex_lock(spi_bus_t bus)
-{
- if (osal_mutex_lock_timeout(&g_spi_mutex[bus], OSAL_MUTEX_WAIT_FOREVER) != OSAL_SUCCESS) {
- return false;
- }
- return true;
-}
-#endif /* CONFIG_SPI_SUPPORT_CONCURRENCY */
-
-static void spi_mutex_unlock(spi_bus_t bus)
-{
-#if defined(CONFIG_SPI_SUPPORT_CONCURRENCY) && (CONFIG_SPI_SUPPORT_CONCURRENCY == 1)
- osal_mutex_unlock(&g_spi_mutex[bus]);
-#endif /* CONFIG_SPI_SUPPORT_CONCURRENCY */
- unused(bus);
-}
-
static void spi_int_mode_init(spi_bus_t bus)
{
#if defined(CONFIG_SPI_SUPPORT_INTERRUPT) && (CONFIG_SPI_SUPPORT_INTERRUPT == 1)
spi_port_register_irq(bus);
spi_config_tx_state(bus);
- g_spi_rx_state[bus] = &g_spi_rx_state_array[bus];
#else
unused(bus);
#endif /* CONFIG_SPI_SUPPORT_INTERRUPT */
#endif /* CONFIG_SPI_SUPPORT_DMA */
#if defined(CONFIG_SPI_SUPPORT_INTERRUPT) && (CONFIG_SPI_SUPPORT_INTERRUPT == 1)
- g_spi_rx_state[bus] = NULL;
- g_spi_tx_state[bus] = NULL;
-
spi_port_unregister_irq(bus);
#endif /* CONFIG_SPI_SUPPORT_INTERRUPT */
spi_mutex_deinit(bus);
- if (ret == ERRCODE_SUCC) {
- g_spi_is_initialised[bus] = false;
- }
+ g_spi_is_initialised[bus] = false;
return ret;
}
#if defined(CONFIG_SPI_SUPPORT_DMA) && (CONFIG_SPI_SUPPORT_DMA == 1)
errcode_t uapi_spi_set_dma_mode(spi_bus_t bus, bool en, const spi_dma_config_t *dma_cfg)
{
- hal_spi_dma_cfg_param_t data = { 0 };
-
if (bus >= SPI_BUS_MAX_NUM) {
return ERRCODE_INVALID_PARAM;
}
-
+ hal_spi_dma_cfg_param_t data;
#if !defined(CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH)
#if defined(CONFIG_SPI_SUPPORT_INTERRUPT) && (CONFIG_SPI_SUPPORT_INTERRUPT == 1)
- if (g_spi_rx_state[bus]->is_enable || g_spi_tx_state[bus]->is_enable) {
+ if (g_spi_rx_int_flag[bus] || g_spi_tx_int_flag[bus]) {
return ERRCODE_SPI_DMA_IRQ_MODE_MUTEX;
}
#endif /* CONFIG_SPI_SUPPORT_INTERRUPT */
/* channel default value is 0, means not used. channel > 0 means used.
So ch + 1 will not misjudgment with channel value 0. */
if (dma_trans[i].channel == ch + 1) {
+ g_dma_trans_tx[i].channel = 0;
bus = i;
break;
}
static hal_dma_data_width_t spi_dma_get_spi_width(spi_bus_t bus)
{
- hal_spi_attr_t attr = { 0 };
+ hal_spi_attr_t attr; /* will copy attr from hal, no need init to 0. */
g_hal_funcs->ctrl(bus, SPI_CTRL_GET_ATTR, (uintptr_t)&attr);
uint32_t frame_bytes = hal_spi_frame_size_trans_to_frame_bytes(attr.frame_size);
transfer_config->dest = data_addr;
}
-static errcode_t spi_write_dma(spi_bus_t bus, const spi_xfer_data_t *data, uint32_t timeout)
+static errcode_t spi_write_dma_config(spi_bus_t bus, uint8_t *ch, const spi_xfer_data_t *data)
{
dma_ch_user_peripheral_config_t transfer_config = { 0 };
uint8_t channel = DMA_CHANNEL_NONE;
g_dma_trans_tx[bus].channel = channel + 1;
g_dma_trans_tx[bus].trans_succ = false;
+ *ch = channel;
+
+ return ERRCODE_SUCC;
+}
+
+static errcode_t spi_write_dma(spi_bus_t bus, const spi_xfer_data_t *data, uint32_t timeout)
+{
+ uint8_t channel;
+ errcode_t ret;
+ if (data->tx_buff == NULL || data->tx_bytes == 0) {
+ return ERRCODE_INVALID_PARAM;
+ }
+
+ ret = spi_write_dma_config(bus, &channel, data);
+ if (ret != ERRCODE_SUCC) {
+ return ret;
+ }
+ hal_spi_dma_cfg_param_t dcfg = {0};
+ dcfg.is_enable = false;
+ dcfg.dma_tx_level = spi_port_tx_data_level_get(bus);
+ g_hal_funcs->ctrl(bus, SPI_CTRL_SET_DMA_CFG, (uintptr_t)&dcfg);
uapi_pm_add_sleep_veto(PM_ID_SPI_DMA);
if (uapi_dma_start_transfer(channel) != ERRCODE_SUCC) {
uapi_pm_remove_sleep_veto(PM_ID_SPI_DMA);
return ERRCODE_SPI_DMA_CONFIG_ERROR;
}
+ dcfg.is_enable = true;
+ g_hal_funcs->ctrl(bus, SPI_CTRL_SET_DMA_CFG, (uintptr_t)&dcfg);
if (osal_sem_down_timeout(&(g_dma_trans_tx[bus].dma_sem), timeout) != OSAL_SUCCESS) {
uapi_dma_end_transfer(channel);
uapi_pm_remove_sleep_veto(PM_ID_SPI_DMA);
transfer_config->src = data_addr;
}
-static errcode_t spi_read_dma(spi_bus_t bus, const spi_xfer_data_t *data, uint32_t timeout)
+static errcode_t spi_read_dma_config(spi_bus_t bus, uint8_t *ch, const spi_xfer_data_t *data)
{
dma_ch_user_peripheral_config_t transfer_config = { 0 };
uint8_t channel = DMA_CHANNEL_NONE;
spi_dma_rx_config(&transfer_config, bus);
transfer_config.dest = (uint32_t)(uintptr_t)data->rx_buff;
#if defined(CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH) && (CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH == 1)
- transfer_config.dest_width = spi_dma_get_mem_width(transfer_config.dest, DMA_SPI_TRANSFER_WIDTH_WORD);
+ transfer_config.dest_width = spi_dma_get_mem_width(transfer_config.dest, data->rx_bytes);
transfer_config.burst_length = HAL_DMA_BURST_TRANSACTION_LENGTH_1;
transfer_config.priority = HAL_DMA_CH_PRIORITY_0;
transfer_config.transfer_num = (uint16_t)data->rx_bytes >> transfer_config.src_width;
g_dma_trans_rx[bus].channel = channel + 1;
g_dma_trans_rx[bus].trans_succ = false;
+ *ch = channel;
+
+ return ERRCODE_SUCC;
+}
+static errcode_t spi_read_dma(spi_bus_t bus, const spi_xfer_data_t *data, uint32_t timeout)
+{
+ uint8_t channel;
+ errcode_t ret = spi_read_dma_config(bus, &channel, data);
+ if (ret != ERRCODE_SUCC) {
+ return ret;
+ }
+
+ hal_spi_dma_cfg_param_t dcfg = {0};
+ dcfg.is_enable = false;
+ g_hal_funcs->ctrl(bus, SPI_CTRL_SET_DMA_CFG, (uintptr_t)&dcfg);
uapi_pm_add_sleep_veto(PM_ID_SPI_DMA);
if (uapi_dma_start_transfer(channel) != ERRCODE_SUCC) {
uapi_pm_remove_sleep_veto(PM_ID_SPI_DMA);
return ERRCODE_SPI_DMA_CONFIG_ERROR;
}
+ dcfg.is_enable = true;
+ g_hal_funcs->ctrl(bus, SPI_CTRL_SET_DMA_CFG, (uintptr_t)&dcfg);
if (osal_sem_down_timeout(&(g_dma_trans_rx[bus].dma_sem), timeout) != OSAL_SUCCESS) {
uapi_dma_end_transfer(channel);
uapi_pm_remove_sleep_veto(PM_ID_SPI_DMA);
return ERRCODE_SUCC;
}
-static errcode_t spi_read_dma_config(spi_bus_t bus, uint8_t *ch, const spi_xfer_data_t *data)
-{
- dma_ch_user_peripheral_config_t transfer_config = { 0 };
- uint8_t channel = DMA_CHANNEL_NONE;
-
- spi_dma_rx_config(&transfer_config, bus);
- transfer_config.dest = (uint32_t)(uintptr_t)data->rx_buff;
-#if defined(CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH) && (CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH == 1)
- transfer_config.dest_width = spi_dma_get_mem_width(transfer_config.dest, DMA_SPI_TRANSFER_WIDTH_WORD);
- transfer_config.burst_length = HAL_DMA_BURST_TRANSACTION_LENGTH_1;
- transfer_config.priority = HAL_DMA_CH_PRIORITY_0;
- transfer_config.transfer_num = (uint16_t)data->rx_bytes >> transfer_config.src_width;
-#else
- if (data->rx_bytes % bit(g_dma_cfg[bus].src_width) == 0) {
- transfer_config.transfer_num = (uint16_t)data->rx_bytes >> g_dma_cfg[bus].src_width;
- } else {
- return ERRCODE_INVALID_PARAM;
- }
-
- spi_dma_common_config(&transfer_config, &(g_dma_cfg[bus]));
-#endif /* CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH */
-
- transfer_config.src_handshaking = spi_port_get_dma_trans_src_handshaking(bus);
- if (transfer_config.src_handshaking == HAL_DMA_HANDSHAKING_MAX_NUM) {
- return ERRCODE_SPI_DMA_CONFIG_ERROR;
- }
-
- if (uapi_dma_configure_peripheral_transfer_single(&transfer_config, &channel, spi_dma_isr, 1) != ERRCODE_SUCC) {
- return ERRCODE_SPI_DMA_CONFIG_ERROR;
- }
-
- g_dma_trans_rx[bus].channel = channel + 1;
- g_dma_trans_rx[bus].trans_succ = false;
- *ch = channel;
-
- return ERRCODE_SUCC;
-}
-
-static errcode_t spi_write_dma_config(spi_bus_t bus, uint8_t *ch, const spi_xfer_data_t *data)
-{
- dma_ch_user_peripheral_config_t transfer_config = { 0 };
- uint8_t channel = DMA_CHANNEL_NONE;
-
- transfer_config.src = (uint32_t)(uintptr_t)data->tx_buff;
-#if defined(CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH) && (CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH == 1)
- transfer_config.src_width = spi_dma_get_mem_width(transfer_config.src, data->tx_bytes);
- transfer_config.transfer_num = (uint16_t)data->tx_bytes >> transfer_config.src_width;
- transfer_config.burst_length = HAL_DMA_BURST_TRANSACTION_LENGTH_1;
- transfer_config.priority = HAL_DMA_CH_PRIORITY_0;
-#else
- if (data->tx_bytes % bit(g_dma_cfg[bus].src_width) == 0) {
- transfer_config.transfer_num = (uint16_t)data->tx_bytes >> g_dma_cfg[bus].src_width;
- } else {
- return ERRCODE_INVALID_PARAM;
- }
-
- spi_dma_common_config(&transfer_config, &(g_dma_cfg[bus]));
-#endif /* CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH */
- spi_dma_tx_config(&transfer_config, bus);
-
- transfer_config.dest_handshaking = spi_port_get_dma_trans_dest_handshaking(bus);
- if (transfer_config.dest_handshaking == HAL_DMA_HANDSHAKING_MAX_NUM) {
- return ERRCODE_SPI_DMA_CONFIG_ERROR;
- }
-
- if (uapi_dma_configure_peripheral_transfer_single(&transfer_config, &channel, spi_dma_isr, 0) != ERRCODE_SUCC) {
- return ERRCODE_SPI_DMA_CONFIG_ERROR;
- }
-
- g_dma_trans_tx[bus].channel = channel + 1;
- g_dma_trans_tx[bus].trans_succ = false;
- *ch = channel;
-
- return ERRCODE_SUCC;
-}
-
-static inline void spi_writeread_dma_clear_trans(spi_bus_t bus, uint8_t channel_tx, uint8_t channel_rx)
+static void spi_writeread_dma_clear_trans(spi_bus_t bus, uint8_t channel_tx, uint8_t channel_rx)
{
g_dma_trans_tx[bus].channel = 0;
g_dma_trans_rx[bus].channel = 0;
uapi_dma_end_transfer(channel_tx);
}
+static void spi_dma_request_enable(bool enable, spi_bus_t bus)
+{
+ uint32_t irq_sts = spi_porting_lock(bus);
+ hal_spi_dma_cfg_param_t dcfg = {0};
+ dcfg.is_enable = enable;
+ dcfg.dma_tx_level = spi_port_tx_data_level_get(bus);
+ dcfg.dma_rx_level = spi_port_rx_data_level_get(bus);
+ g_hal_funcs->ctrl(bus, SPI_CTRL_SET_DMA_CFG, (uintptr_t)&dcfg);
+ spi_porting_unlock(bus, irq_sts);
+}
+
static errcode_t spi_writeread_dma(spi_bus_t bus, const spi_xfer_data_t *data, uint32_t timeout)
{
- uint8_t channel_rx = 0;
- uint8_t channel_tx = 0;
+ uint8_t channel_rx;
+ uint8_t channel_tx;
+
+ if (data->tx_buff == NULL || data->tx_bytes == 0) {
+ return ERRCODE_INVALID_PARAM;
+ }
if (spi_read_dma_config(bus, &channel_rx, data) != ERRCODE_SUCC) {
return ERRCODE_SPI_DMA_CONFIG_ERROR;
}
+ spi_dma_request_enable(false, bus);
uapi_pm_add_sleep_veto(PM_ID_SPI_DMA);
if (uapi_dma_start_transfer(channel_rx) != ERRCODE_SUCC) {
uapi_pm_remove_sleep_veto(PM_ID_SPI_DMA);
return ERRCODE_SPI_DMA_CONFIG_ERROR;
}
+ spi_dma_request_enable(true, bus);
+
if (osal_sem_down_timeout(&(g_dma_trans_tx[bus].dma_sem), timeout) != OSAL_SUCCESS) {
spi_writeread_dma_clear_trans(bus, channel_tx, channel_rx);
uapi_pm_remove_sleep_veto(PM_ID_SPI_DMA);
return g_hal_funcs->ctrl(bus, SPI_CTRL_GET_EXTRA_ATTR, (uintptr_t)extra_attr);
}
-static uint32_t spi_get_attr_tmod(spi_bus_t bus)
-{
- spi_attr_t attr = { 0 };
-
- if (uapi_spi_get_attr(bus, &attr) != ERRCODE_SUCC) {
- return 0;
- }
- return attr.tmod;
-}
-
#if defined(CONFIG_SPI_SUPPORT_INTERRUPT) && (CONFIG_SPI_SUPPORT_INTERRUPT == 1)
errcode_t uapi_spi_set_irq_mode(spi_bus_t bus, bool irq_en, spi_rx_callback_t rx_callback,
spi_tx_callback_t tx_callback)
#endif /* CONFIG_SPI_SUPPORT_DMA */
uint32_t irq_sts = spi_porting_lock(bus);
if (irq_en) {
- g_spi_rx_state[bus]->rx_callback = rx_callback;
- g_spi_tx_state[bus]->tx_callback = tx_callback;
+ g_spi_rx_state[bus].rx_callback = rx_callback;
+ g_spi_tx_state[bus].tx_callback = tx_callback;
} else {
- g_spi_rx_state[bus]->rx_callback = NULL;
- g_spi_tx_state[bus]->tx_callback = NULL;
+ g_spi_rx_state[bus].rx_callback = NULL;
+ g_spi_tx_state[bus].tx_callback = NULL;
}
- g_spi_rx_state[bus]->is_enable = irq_en;
- g_spi_tx_state[bus]->is_enable = irq_en;
+ g_spi_rx_int_flag[bus] = irq_en;
+ g_spi_tx_int_flag[bus] = irq_en;
spi_porting_unlock(bus, irq_sts);
return ERRCODE_SUCC;
static void spi_data_send(spi_bus_t bus)
{
bool tx_fifo_full = true;
- hal_spi_attr_t attr = { 0 };
+ hal_spi_attr_t attr; /* will copy attr from hal, no need init to 0. */
g_hal_funcs->ctrl(bus, SPI_CTRL_GET_ATTR, (uintptr_t)&attr);
uint32_t frame_bytes = hal_spi_frame_size_trans_to_frame_bytes(attr.frame_size);
+ if (g_spi_tx_state[bus].current_tx_fragment_pos == 0) {
+ if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) {
+ return;
+ }
+ }
g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_TX_FIFO_FULL, (uintptr_t)&tx_fifo_full);
/* Populate the SPI TX FIFO if there is data to send */
while (!tx_fifo_full) {
static errcode_t spi_write_int(spi_bus_t bus, const spi_xfer_data_t *data)
{
+ if (data->tx_buff == NULL || data->tx_bytes == 0) {
+ return ERRCODE_INVALID_PARAM;
+ }
uint32_t irq_sts = spi_porting_lock(bus);
if (!spi_helper_add_fragment(bus, data->tx_buff, data->tx_bytes)) {
static errcode_t spi_register_rx_callback(spi_bus_t bus, const spi_xfer_data_t *data)
{
+ spi_attr_t attr; /* uapi_spi_get_attr will copy attr from hal, no need init to 0. */
+ errcode_t ret = ERRCODE_SUCC;
+ if (uapi_spi_get_attr(bus, &attr) != ERRCODE_SUCC) {
+ return ERRCODE_SPI_CONFIG_FAIL;
+ }
uint32_t irq_sts = spi_porting_lock(bus);
- g_spi_rx_state[bus]->rx_buffer = data->rx_buff;
- g_spi_rx_state[bus]->rx_buffer_size = data->rx_bytes;
- errcode_t ret = g_hal_funcs->ctrl(bus, SPI_CTRL_EN_RXFI_INT, 1);
+ g_spi_rx_state[bus].rx_buffer = data->rx_buff;
+ g_spi_rx_state[bus].rx_buffer_size = data->rx_bytes;
+ g_hal_funcs->ctrl(bus, SPI_CTRL_EN_RXFI_INT, 1);
+
+ if (spi_porting_get_device_mode(bus) == SPI_MODE_MASTER && attr.tmod == HAL_SPI_TRANS_MODE_RX) {
+ uint32_t frame_bytes = hal_spi_frame_size_trans_to_frame_bytes(attr.frame_size);
+ if (frame_bytes == 0) {
+ return ERRCODE_SPI_CONFIG_FAIL;
+ }
+ attr.ndf = g_spi_rx_state[bus].rx_buffer_size / frame_bytes;
+ if (uapi_spi_set_attr(bus, &attr) != ERRCODE_SUCC) {
+ return ERRCODE_SPI_CONFIG_FAIL;
+ }
+ uint32_t data_tx = 0;
+ spi_xfer_data_t data_write = { 0 };
+ data_write.tx_buff = (uint8_t *)(uintptr_t)&data_tx;
+ data_write.tx_bytes = frame_bytes;
+ ret = g_hal_funcs->write(bus, (hal_spi_xfer_data_t *)&data_write, CONFIG_SPI_MAX_TIMEOUT);
+ }
spi_porting_unlock(bus, irq_sts);
return ret;
}
#endif /* CONFIG_SPI_SUPPORT_INTERRUPT */
-#if defined(CONFIG_SPI_SUPPORT_MASTER) || defined(CONFIG_SPI_SUPPORT_SLAVE)
-static errcode_t uapi_spi_param_check(spi_bus_t bus, spi_mode_t spi_mode, hal_spi_trans_mode_t trans_mode)
-{
- if (spi_porting_get_device_mode(bus) != spi_mode) {
- return ERRCODE_SPI_MODE_MISMATCH;
- }
-
- if (spi_get_attr_tmod(bus) == trans_mode) {
- return ERRCODE_SPI_INVALID_TMODE;
- }
-
-#if defined(CONFIG_SPI_SUPPORT_CONCURRENCY) && (CONFIG_SPI_SUPPORT_CONCURRENCY == 1)
- if (!spi_mutex_lock(bus)) {
- return ERRCODE_SPI_TIMEOUT;
- }
-#endif /* CONFIG_SPI_SUPPORT_CONCURRENCY */
-
- return ERRCODE_SUCC;
-}
-#endif /* CONFIG_SPI_SUPPORT_MASTER || CONFIG_SPI_SUPPORT_SLAVE */
-
#if defined(CONFIG_SPI_SUPPORT_MASTER) && (CONFIG_SPI_SUPPORT_MASTER == 1)
errcode_t uapi_spi_select_slave(spi_bus_t bus, spi_slave_t cs)
{
errcode_t ret;
uint32_t timeout_tmp = timeout == 0 ? CONFIG_SPI_MAX_TIMEOUT : timeout;
- if (bus >= SPI_BUS_MAX_NUM || data == NULL) {
- return ERRCODE_INVALID_PARAM;
- }
-
- ret = uapi_spi_param_check(bus, SPI_MODE_MASTER, HAL_SPI_TRANS_MODE_RX);
+ ret = spi_param_check_write(bus, SPI_MODE_MASTER, HAL_SPI_TRANS_MODE_RX, data, true);
if (ret != ERRCODE_SUCC) {
return ret;
}
#if defined(CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH) && (CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH == 1)
if (data->tx_bytes > CONFIG_SPI_AUTO_SWITCH_DMA_THRESHOLD) {
uapi_spi_set_dma_mode(bus, true, NULL);
- ret = spi_write_dma(bus, data, DMA_SPI_TRANSFER_TIMEOUT_MS);
+ ret = spi_write_dma(bus, data, timeout_tmp);
if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) {
spi_mutex_unlock(bus);
return ERRCODE_SPI_TIMEOUT;
#else
#if defined(CONFIG_SPI_SUPPORT_DMA) && (CONFIG_SPI_SUPPORT_DMA == 1)
if (g_dma_trans_tx[bus].is_enable) {
- ret = spi_write_dma(bus, data, DMA_SPI_TRANSFER_TIMEOUT_MS);
+ ret = spi_write_dma(bus, data, timeout_tmp);
+ if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) {
+ spi_mutex_unlock(bus);
+ return ERRCODE_SPI_TIMEOUT;
+ }
spi_mutex_unlock(bus);
return ret;
}
#endif /* CONFIG_SPI_SUPPORT_DMA */
#if defined(CONFIG_SPI_SUPPORT_INTERRUPT) && (CONFIG_SPI_SUPPORT_INTERRUPT == 1)
- if (g_spi_tx_state[bus]->is_enable) {
+ if (g_spi_tx_int_flag[bus]) {
ret = spi_write_int(bus, data);
spi_mutex_unlock(bus);
return ret;
uint32_t irq_sts = spi_porting_lock(bus);
ret = g_hal_funcs->write(bus, (hal_spi_xfer_data_t *)data, timeout_tmp);
- if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) {
+ if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, timeout_tmp) != ERRCODE_SUCC) {
spi_porting_unlock(bus, irq_sts);
spi_mutex_unlock(bus);
return ERRCODE_SPI_TIMEOUT;
#if defined(CONFIG_SPI_SUPPORT_DMA) && (CONFIG_SPI_SUPPORT_DMA == 1)
static errcode_t spi_read_by_writeread(spi_bus_t bus, const spi_xfer_data_t *data, uint32_t timeout)
{
- spi_attr_t attr = { 0 };
+ spi_attr_t attr; /* uapi_spi_get_attr will copy attr from hal, no need init to 0. */
uint32_t data_tx = 0;
spi_xfer_data_t data_writeread = { 0 };
uapi_spi_get_attr(bus, &attr);
-
uint32_t ndf_before = attr.ndf;
uint32_t frame_bytes = hal_spi_frame_size_trans_to_frame_bytes(attr.frame_size);
if (frame_bytes == 0) {
return ret;
}
-#endif /* CONFIG_SPI_SUPPORT_DMA */
#if !defined(CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH)
static errcode_t spi_master_read_dma(spi_bus_t bus, const spi_xfer_data_t *data, uint32_t timeout)
if (spi_get_attr_tmod(bus) == HAL_SPI_TRANS_MODE_RX) {
return spi_read_by_writeread(bus, data, timeout);
}
- return spi_read_dma(bus, data, timeout);
+
+ errcode_t ret = spi_read_dma(bus, data, timeout);
+ if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) {
+ return ERRCODE_SPI_TIMEOUT;
+ }
+ return ret;
}
#endif /* NOT CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH */
+#endif /* CONFIG_SPI_SUPPORT_DMA */
errcode_t uapi_spi_master_read(spi_bus_t bus, const spi_xfer_data_t *data, uint32_t timeout)
{
errcode_t ret;
uint32_t timeout_tmp = timeout == 0 ? CONFIG_SPI_MAX_TIMEOUT : timeout;
- if (bus >= SPI_BUS_MAX_NUM || data == NULL || data->rx_buff == NULL || data->rx_bytes == 0) {
- return ERRCODE_INVALID_PARAM;
- }
-
- ret = uapi_spi_param_check(bus, SPI_MODE_MASTER, HAL_SPI_TRANS_MODE_TX);
+ ret = spi_param_check_read(bus, SPI_MODE_MASTER, HAL_SPI_TRANS_MODE_TX, data, true);
if (ret != ERRCODE_SUCC) {
return ret;
}
#endif /* CONFIG_SPI_SUPPORT_DMA */
#if defined(CONFIG_SPI_SUPPORT_INTERRUPT) && (CONFIG_SPI_SUPPORT_INTERRUPT == 1)
- if (g_spi_rx_state[bus]->is_enable) {
+ if (g_spi_rx_int_flag[bus]) {
ret = spi_register_rx_callback(bus, data);
spi_mutex_unlock(bus);
return ret;
uint32_t irq_sts = spi_porting_lock(bus);
ret = g_hal_funcs->read(bus, (hal_spi_xfer_data_t *)data, timeout_tmp);
+ if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, timeout_tmp) != ERRCODE_SUCC) {
+ spi_porting_unlock(bus, irq_sts);
+ spi_mutex_unlock(bus);
+ return ERRCODE_SPI_TIMEOUT;
+ }
spi_porting_unlock(bus, irq_sts);
spi_mutex_unlock(bus);
errcode_t ret;
uint32_t timeout_tmp = timeout == 0 ? CONFIG_SPI_MAX_TIMEOUT : timeout;
- if (bus >= SPI_BUS_MAX_NUM || data == NULL || data->rx_buff == NULL || data->rx_bytes == 0) {
- return ERRCODE_INVALID_PARAM;
- }
-
- ret = uapi_spi_param_check(bus, SPI_MODE_MASTER, HAL_SPI_TRANS_MODE_TX);
+ ret = spi_param_check_read(bus, SPI_MODE_MASTER, HAL_SPI_TRANS_MODE_TX, data, true);
if (ret != ERRCODE_SUCC) {
return ret;
}
data->tx_bytes > CONFIG_SPI_AUTO_SWITCH_DMA_THRESHOLD) {
uapi_spi_set_dma_mode(bus, true, NULL);
ret = spi_writeread_dma(bus, data, timeout_tmp);
+ if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) {
+ spi_mutex_unlock(bus);
+ return ERRCODE_SPI_TIMEOUT;
+ }
spi_mutex_unlock(bus);
return ret;
}
#if defined(CONFIG_SPI_SUPPORT_DMA) && (CONFIG_SPI_SUPPORT_DMA == 1)
if (g_dma_trans_tx[bus].is_enable && g_dma_trans_rx[bus].is_enable) {
ret = spi_writeread_dma(bus, data, timeout_tmp);
+ if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) {
+ spi_mutex_unlock(bus);
+ return ERRCODE_SPI_TIMEOUT;
+ }
spi_mutex_unlock(bus);
return ret;
}
uint32_t irq_sts = spi_porting_lock(bus);
ret = g_hal_funcs->writeread(bus, (hal_spi_xfer_data_t *)data, timeout_tmp);
+ if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, timeout_tmp) != ERRCODE_SUCC) {
+ spi_porting_unlock(bus, irq_sts);
+ spi_mutex_unlock(bus);
+ return ERRCODE_SPI_TIMEOUT;
+ }
spi_porting_unlock(bus, irq_sts);
spi_mutex_unlock(bus);
errcode_t ret;
uint32_t timeout_tmp = timeout == 0 ? CONFIG_SPI_MAX_TIMEOUT : timeout;
- if (bus >= SPI_BUS_MAX_NUM || data == NULL || data->tx_buff == NULL || data->tx_bytes == 0) {
+ if (data == NULL || data->tx_buff == NULL || data->tx_bytes == 0) {
return ERRCODE_INVALID_PARAM;
}
- ret = uapi_spi_param_check(bus, SPI_MODE_SLAVE, HAL_SPI_TRANS_MODE_RX);
+ ret = spi_param_check_write(bus, SPI_MODE_SLAVE, HAL_SPI_TRANS_MODE_RX, data, true);
if (ret != ERRCODE_SUCC) {
return ret;
}
#if defined(CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH) && (CONFIG_SPI_SUPPORT_POLL_AND_DMA_AUTO_SWITCH == 1)
if (data->tx_bytes > CONFIG_SPI_AUTO_SWITCH_DMA_THRESHOLD) {
uapi_spi_set_dma_mode(bus, true, NULL);
- ret = spi_write_dma(bus, data, CONFIG_SPI_MAX_TIMEOUT);
+ ret = spi_write_dma(bus, data, timeout_tmp);
+ if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) {
+ spi_mutex_unlock(bus);
+ return ERRCODE_SPI_TIMEOUT;
+ }
spi_mutex_unlock(bus);
return ret;
}
#else
#if defined(CONFIG_SPI_SUPPORT_DMA) && (CONFIG_SPI_SUPPORT_DMA == 1)
if (g_dma_trans_tx[bus].is_enable) {
- ret = spi_write_dma(bus, data, CONFIG_SPI_MAX_TIMEOUT);
+ ret = spi_write_dma(bus, data, timeout_tmp);
+ if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) {
+ spi_mutex_unlock(bus);
+ return ERRCODE_SPI_TIMEOUT;
+ }
spi_mutex_unlock(bus);
return ret;
}
#endif /* CONFIG_SPI_SUPPORT_DMA */
#if defined(CONFIG_SPI_SUPPORT_INTERRUPT) && (CONFIG_SPI_SUPPORT_INTERRUPT == 1)
- if (g_spi_tx_state[bus]->is_enable) {
+ if (g_spi_tx_int_flag[bus]) {
ret = spi_write_int(bus, data);
spi_mutex_unlock(bus);
return ret;
uint32_t irq_sts = spi_porting_lock(bus);
ret = g_hal_funcs->write(bus, (hal_spi_xfer_data_t *)data, timeout_tmp);
+ if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, timeout_tmp) != ERRCODE_SUCC) {
+ spi_porting_unlock(bus, irq_sts);
+ spi_mutex_unlock(bus);
+ return ERRCODE_SPI_TIMEOUT;
+ }
spi_porting_unlock(bus, irq_sts);
spi_mutex_unlock(bus);
errcode_t ret;
uint32_t timeout_tmp = timeout == 0 ? CONFIG_SPI_MAX_TIMEOUT : timeout;
- if (bus >= SPI_BUS_MAX_NUM || data == NULL || data->rx_buff == NULL || data->rx_bytes == 0) {
- return ERRCODE_INVALID_PARAM;
- }
-
- ret = uapi_spi_param_check(bus, SPI_MODE_SLAVE, HAL_SPI_TRANS_MODE_TX);
+ ret = spi_param_check_read(bus, SPI_MODE_SLAVE, HAL_SPI_TRANS_MODE_TX, data, false);
if (ret != ERRCODE_SUCC) {
return ret;
}
if (data->rx_bytes > CONFIG_SPI_AUTO_SWITCH_DMA_THRESHOLD) {
uapi_spi_set_dma_mode(bus, true, NULL);
ret = spi_read_dma(bus, data, timeout_tmp);
+ if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) {
+ spi_mutex_unlock(bus);
+ return ERRCODE_SPI_TIMEOUT;
+ }
spi_mutex_unlock(bus);
return ret;
}
#if defined(CONFIG_SPI_SUPPORT_DMA) && (CONFIG_SPI_SUPPORT_DMA == 1)
if (g_dma_trans_rx[bus].is_enable) {
ret = spi_read_dma(bus, data, timeout_tmp);
+ if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, (uintptr_t)SPI_TX_FIFO_BUSY_TIMEOUT) != ERRCODE_SUCC) {
+ spi_mutex_unlock(bus);
+ return ERRCODE_SPI_TIMEOUT;
+ }
spi_mutex_unlock(bus);
return ret;
}
#endif /* CONFIG_SPI_SUPPORT_DMA */
#if defined(CONFIG_SPI_SUPPORT_INTERRUPT) && (CONFIG_SPI_SUPPORT_INTERRUPT == 1)
- if (g_spi_rx_state[bus]->is_enable) {
+ if (g_spi_rx_int_flag[bus]) {
ret = spi_register_rx_callback(bus, data);
spi_mutex_unlock(bus);
return ret;
uint32_t irq_sts = spi_porting_lock(bus);
ret = g_hal_funcs->read(bus, (hal_spi_xfer_data_t *)data, timeout_tmp);
+ if (g_hal_funcs->ctrl(bus, SPI_CTRL_CHECK_FIFO_BUSY, timeout_tmp) != ERRCODE_SUCC) {
+ spi_porting_unlock(bus, irq_sts);
+ spi_mutex_unlock(bus);
+ return ERRCODE_SPI_TIMEOUT;
+ }
spi_porting_unlock(bus, irq_sts);
spi_mutex_unlock(bus);
}
}
-static uint32_t hal_gpio_is_interrupt_asserted(pin_t pin)
+__attribute__((noinline)) static uint32_t hal_gpio_is_interrupt_asserted(pin_t pin)
{
gpio_channel_t channel = hal_gpio_get_channel(pin);
uint32_t channel_pin = hal_gpio_get_channel_pin(pin);
uint8_t data_ths_trail = tp->data_ths_trail;
uint8_t data_ths_prepare = tp->data_ths_prepare;
+#ifdef GPU_SUPPORT_VIDEO_MODE
+ /* data lp2hs,hs2lp time */
+ g_mipi_tx_regs_va->datalane_time.u32 = ((data_ths_trail - 2) << 16) + /* 2, 16 tx time param */
+ data_tpre_delay + data_tlpx + data_ths_prepare + data_ths_zero + 8 - 15; /* 8 - 15 tx time param */
+#else
/* data lp2hs,hs2lp time */
g_mipi_tx_regs_va->datalane_time.u32 = ((data_ths_trail - 2) << 16) + /* 2, 16 tx time param */
data_tpre_delay + data_tlpx + data_ths_prepare + data_ths_zero + 8; /* 8 tx time param */
+#endif
/* clk lp2hs,hs2lp time */
g_mipi_tx_regs_va->clklane_time.u32 = ((30 + data_ths_trail) << 16) + /* 30, 16 tx time param */
clk_tlpx + clk_tclk_prepare + clk_tclk_zero + 7; /* 7 tx time param */
g_mipi_tx_regs_va->mode_cfg.u32 = mode_cfg.u32;
}
-#ifdef MIPI_SUPPORT_VIDEO
+#ifdef GPU_SUPPORT_VIDEO_MODE
static void mipi_tx_hal_set_video_mode_type(uint32_t video_mode_type)
{
volatile reg_mode_cfg mode_cfg;
* 00: Non-burst with sync pulse
* 01: Non-burst with sync
*/
- mipi_tx_hal_set_cmd_video_mode(VIDEO_MODE);
mipi_tx_hal_set_video_mode_type(video_mode_type);
g_mipi_tx_regs_va->video_lp_en.u32 = 0x3f;
/* gen_vcid_rx */
g_mipi_tx_regs_va->gen_vc.u32 = 0x0;
-#ifdef MIPI_SUPPORT_VIDEO
+#ifdef GPU_SUPPORT_VIDEO_MODE
/* video mode cfg */
set_video_mode_cfg(dev_cfg);
if (dev_cfg->out_mode == OUT_MODE_DSI_VIDEO) {
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