drivers文件夹下chips文件夹合并提交

diff --git a/code/sdk/drivers/chips/brandy/config/pmp_config.c b/code/sdk/drivers/chips/brandy/config/pmp_config.c
index 0676c29..d209b98 100644 (file)
--- a/code/sdk/drivers/chips/brandy/config/pmp_config.c
+++ b/code/sdk/drivers/chips/brandy/config/pmp_config.c
@@ -40,18 +40,20 @@
 typedef enum {\r
     BOOTROM_IDX                = 0,\r
     ITCM_IDX                   = 1,\r
-    ITCM_SECOND_IDX            = 2,\r
-    DTCM_IDX                   = 3,\r
-    L2RAM_IDX                  = 4,\r
-    SHARE_MEM_IDX              = 5,\r
-    BT_RAM_APP_MAPPING_IDX     = 6,\r
-    REG_ADDR_0_IDX             = 7,  /* reg 0x5x */\r
-    REG_ADDR_1_IDX             = 8,  /* reg 0xa3 */\r
+    DTCM_IDX                   = 2,\r
+    L2RAM_IDX                  = 3,\r
+    SHARE_MEM_IDX              = 4,\r
+    BT_RAM_APP_MAPPING_IDX     = 5,\r
+    REG_ADDR_0_IDX             = 6,  /* reg 0x5x */\r
+    REG_ADDR_1_IDX             = 7,\r
+    REG_ADDR_1_SECOND_IDX      = 8,  /* reg 0xa3 */\r
+#ifdef SUPPORT_GPU_GMMU\r
+    L2RAM_SECOND_IDX,\r
+#endif\r
 #if defined(CONFIG_PSRAM_SUPPORT) || defined(TEST_SUITE)\r
     PSRAM_DYN_LOAD_IDX,\r
     PSRAM_TEXT_IDX,\r
     PSRAM_IDX,\r
-    PMP_DEBUG_IDX,  /* pmp调测预留idx */\r
     PSRAM_SECOND_IDX,\r
 #endif\r
     NOR_FLASH_IDX,\r
@@ -74,22 +76,13 @@ static void pmp_init_config(void)
 \r
     /* ITCM 第一段 可读可执行不可写 */\r
     g_region_attr[ITCM_IDX].idx = ITCM_IDX;\r
-    g_region_attr[ITCM_IDX].addr = APP_ITCM_ORIGIN;\r
-    g_region_attr[ITCM_IDX].size = ITCM_PMP_LENGTH;\r
+    g_region_attr[ITCM_IDX].addr = 0;\r
+    g_region_attr[ITCM_IDX].size = 0x40000;\r
     g_region_attr[ITCM_IDX].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE;\r
     g_region_attr[ITCM_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_READ_ONLY_EXECUTE;\r
     g_region_attr[ITCM_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT;\r
     g_region_attr[ITCM_IDX].conf.lock = true;\r
 \r
-    /* ITCM 第二段 可读可执行不可写 */\r
-    g_region_attr[ITCM_SECOND_IDX].idx = ITCM_SECOND_IDX;\r
-    g_region_attr[ITCM_SECOND_IDX].addr = (APP_ITCM_ORIGIN + ITCM_PMP_LENGTH);\r
-    g_region_attr[ITCM_SECOND_IDX].size = ITCM_PMP_SECOND_LENGTH;\r
-    g_region_attr[ITCM_SECOND_IDX].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE;\r
-    g_region_attr[ITCM_SECOND_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_READ_ONLY_EXECUTE;\r
-    g_region_attr[ITCM_SECOND_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT;\r
-    g_region_attr[ITCM_SECOND_IDX].conf.lock = true;\r
-\r
     /* DTCM 可读可写不可执行 */\r
     g_region_attr[DTCM_IDX].idx = DTCM_IDX;\r
     g_region_attr[DTCM_IDX].addr = APP_DTCM_ORIGIN;\r
@@ -101,8 +94,13 @@ static void pmp_init_config(void)
 \r
     /* L2MEM 可读可执行可写 no cache属性 */\r
     g_region_attr[L2RAM_IDX].idx = L2RAM_IDX;\r
+#ifndef CONFIG_PSRAM_SUPPORT\r
     g_region_attr[L2RAM_IDX].addr = 0x60000000;\r
-    g_region_attr[L2RAM_IDX].size = 0x2000000;\r
+    g_region_attr[L2RAM_IDX].size = 0x400000;\r
+#else\r
+    g_region_attr[L2RAM_IDX].addr = 0x60200000;\r
+    g_region_attr[L2RAM_IDX].size = 0x200000;\r
+#endif\r
     g_region_attr[L2RAM_IDX].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE;\r
     g_region_attr[L2RAM_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_RW_EXECUTE;\r
     g_region_attr[L2RAM_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT;\r
@@ -137,13 +135,21 @@ static void pmp_init_config(void)
 \r
     /* REG_ADDR_1_IDX 可读可写不可执行 不打开cache属性 */\r
     g_region_attr[REG_ADDR_1_IDX].idx = REG_ADDR_1_IDX;\r
-    g_region_attr[REG_ADDR_1_IDX].addr = 0xA0000000;\r
-    g_region_attr[REG_ADDR_1_IDX].size = 0x20000000;\r
+    g_region_attr[REG_ADDR_1_IDX].addr = 0xA3000000;\r
+    g_region_attr[REG_ADDR_1_IDX].size = 0x10000;\r
     g_region_attr[REG_ADDR_1_IDX].conf.pmp_attr = PMP_ATTR_DEVICE_NO_BUFFERABLE;\r
     g_region_attr[REG_ADDR_1_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_RW_NEXECUTE;\r
     g_region_attr[REG_ADDR_1_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT;\r
     g_region_attr[REG_ADDR_1_IDX].conf.lock = true;\r
 \r
+    g_region_attr[REG_ADDR_1_SECOND_IDX].idx = REG_ADDR_1_SECOND_IDX;\r
+    g_region_attr[REG_ADDR_1_SECOND_IDX].addr = 0xB0000000;\r
+    g_region_attr[REG_ADDR_1_SECOND_IDX].size = 0x10000000;\r
+    g_region_attr[REG_ADDR_1_SECOND_IDX].conf.pmp_attr = PMP_ATTR_DEVICE_NO_BUFFERABLE;\r
+    g_region_attr[REG_ADDR_1_SECOND_IDX].conf.rwx_permission = (rwx_permission_t)PMPCFG_RW_NEXECUTE;\r
+    g_region_attr[REG_ADDR_1_SECOND_IDX].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT;\r
+    g_region_attr[REG_ADDR_1_SECOND_IDX].conf.lock = true;\r
+\r
 #if defined(CONFIG_PSRAM_SUPPORT) || defined(TEST_SUITE)\r
     /* PSRAM syn load 可读可写可执行 打开cache属性 */\r
     g_region_attr[PSRAM_DYN_LOAD_IDX].idx = PSRAM_DYN_LOAD_IDX;\r
@@ -209,18 +215,22 @@ void pmp_init(void)
 \r
 void pmp_gpu_psram_init(void)\r
 {\r
-#if defined(SUPPORT_PMP_DEBUG) && defined(CONFIG_PSRAM_SUPPORT)\r
-    pmp_conf_t gpu_psram_pmp_region_attr[1] = {0};\r
-\r
-    /* PSRAM 第GPU段 可读不可写不可执行 关闭cache属性 */\r
-    gpu_psram_pmp_region_attr[0].idx = PMP_DEBUG_IDX;\r
-    gpu_psram_pmp_region_attr[0].addr = PSRAM_GPU_ADDR_START;\r
-    gpu_psram_pmp_region_attr[0].size = PSRAM_GPU_ADDR_LEN;\r
-    gpu_psram_pmp_region_attr[0].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE;\r
-    gpu_psram_pmp_region_attr[0].conf.rwx_permission = (rwx_permission_t)PMPCFG_READ_ONLY_NEXECUTE;\r
-    gpu_psram_pmp_region_attr[0].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT;\r
-    gpu_psram_pmp_region_attr[0].conf.lock = true;\r
-\r
-    uapi_pmp_config(gpu_psram_pmp_region_attr, 1);\r
-#endif\r
+\r
 }\r
+\r
+#ifdef SUPPORT_GPU_GMMU\r
+void pmp_configure_gmmu_region(int32_t flag)\r
+{\r
+    pmp_conf_t gpu_gmmu_pmp_region_attr[1] = {0};\r
+    gpu_gmmu_pmp_region_attr[0].idx = L2RAM_SECOND_IDX;\r
+    if (flag) {\r
+        gpu_gmmu_pmp_region_attr[0].addr = 0x61000000;\r
+        gpu_gmmu_pmp_region_attr[0].size = 0x1000000;\r
+        gpu_gmmu_pmp_region_attr[0].conf.pmp_attr = PMP_ATTR_NO_BUFFERABLE_AND_NO_CACHEABLE;\r
+        gpu_gmmu_pmp_region_attr[0].conf.rwx_permission = (rwx_permission_t)PMPCFG_RW_EXECUTE;\r
+        gpu_gmmu_pmp_region_attr[0].conf.addr_match = PMPCFG_ADDR_MATCH_NAPOT;\r
+        gpu_gmmu_pmp_region_attr[0].conf.lock = 0;\r
+    }\r
+    uapi_pmp_config(gpu_gmmu_pmp_region_attr, 1);\r
+}\r
+#endif\r

diff --git a/code/sdk/drivers/chips/brandy/config/pmp_config.h b/code/sdk/drivers/chips/brandy/config/pmp_config.h
index 210fb89..52a9510 100644 (file)
--- a/code/sdk/drivers/chips/brandy/config/pmp_config.h
+++ b/code/sdk/drivers/chips/brandy/config/pmp_config.h
@@ -18,6 +18,10 @@
 void pmp_init(void);\r
 void pmp_gpu_psram_init(void);\r
 \r
+#ifdef SUPPORT_GPU_GMMU\r
+void pmp_configure_gmmu_region(int32_t flag);\r
+#endif\r
+\r
 /**\r
  * @}\r
  */\r

diff --git a/code/sdk/drivers/chips/brandy/porting/uart/uart_porting.c b/code/sdk/drivers/chips/brandy/porting/uart/uart_porting.c
index dc93256..4ae9e54 100644 (file)
--- a/code/sdk/drivers/chips/brandy/porting/uart/uart_porting.c
+++ b/code/sdk/drivers/chips/brandy/porting/uart/uart_porting.c
@@ -347,11 +347,13 @@ uint32_t uart_port_get_clock_value(uart_bus_t bus)
 
 void uart_port_config_pinmux(uart_bus_t bus)
 {
-    UNUSED(bus);
-    uapi_pin_set_mode(g_uart_config[UART_BUS_1].pin.tx_pin, g_uart_config[UART_BUS_1].pin_mode.tx_pin_mode);
-    uapi_pin_set_mode(g_uart_config[UART_BUS_1].pin.rx_pin, g_uart_config[UART_BUS_1].pin_mode.rx_pin_mode);
-    uapi_pin_set_mode(g_uart_config[UART_BUS_0].pin.tx_pin, g_uart_config[UART_BUS_0].pin_mode.tx_pin_mode);
-    uapi_pin_set_mode(g_uart_config[UART_BUS_0].pin.rx_pin, g_uart_config[UART_BUS_0].pin_mode.rx_pin_mode);
+    if (bus == UART_BUS_1) {
+        uapi_pin_set_mode(g_uart_config[UART_BUS_1].pin.tx_pin, g_uart_config[UART_BUS_1].pin_mode.tx_pin_mode);
+        uapi_pin_set_mode(g_uart_config[UART_BUS_1].pin.rx_pin, g_uart_config[UART_BUS_1].pin_mode.rx_pin_mode);
+    } else if (bus == UART_BUS_0) {
+        uapi_pin_set_mode(g_uart_config[UART_BUS_0].pin.tx_pin, g_uart_config[UART_BUS_0].pin_mode.tx_pin_mode);
+        uapi_pin_set_mode(g_uart_config[UART_BUS_0].pin.rx_pin, g_uart_config[UART_BUS_0].pin_mode.rx_pin_mode);
+    }
 }
 
 void uart_port_register_irq(uart_bus_t bus)