)\r
endif()\r
\r
+if("AUDIO_SMARTPA_AW88082" IN_LIST DEFINES)\r
+set(COMPONENT_SRC ${COMPONENT_SRC}\r
+ ${CMAKE_CURRENT_SOURCE_DIR}/aw88082/aw88082.c\r
+)\r
+set(COMPONENT_INC ${COMPONENT_INC}\r
+ ${CMAKE_CURRENT_SOURCE_DIR}/aw88082\r
+)\r
+else()\r
if("${CFG_SAP_VENDOR_DRIVER_AW88166_SUPPORT}" STREQUAL "y")\r
set(COMPONENT_SRC ${COMPONENT_SRC}\r
${CMAKE_CURRENT_SOURCE_DIR}/aw88166/aw88166.c\r
${CMAKE_CURRENT_SOURCE_DIR}/aw88166/config/aw88166/mono/16bit\r
)\r
endif()\r
+endif()\r
if("${CFG_SAP_VENDOR_DRIVER_ANC_CODEC_SUPPORT}" STREQUAL "y")\r
set(COMPONENT_SRC ${COMPONENT_SRC}\r
${CMAKE_CURRENT_SOURCE_DIR}/anc_codec/anc_codec.c\r
--- /dev/null
+/*
+ * Copyright (c) CompanyNameMagicTag 2023-2023. All rights reserved.
+ * Description: source file for aw88082 driver
+ */
+
+#include "stdio.h"
+#include "audio_debug.h"
+#if (SAP_OS_TYPE != os_type_xtensa)
+#include "gpio.h"
+#include "hal_gpio.h"
+#include "i2c.h"
+#include "pinctrl.h"
+#else
+#include "i2c_test.h"
+#endif
+#include "vendor_common.h"
+#include "aw88082.h"
+
+#define I2C_WRITE_READ_CNT 5
+#define I2C_SEND_DATA_SHIFT_COUNT 8
+#define REC_I2C_DATA_LEN 2
+#define AW88082_I2C_BUS_ID I2C_BUS_3
+#define AW88082_I2C_ADDR 0x34
+#define AW88082_I2C_BAUDRATE 100000 /* 标准模式上限：100KHz，快速模式上限：400KHz，高速模式上限：3.4MKHz */
+
+static td_bool g_aw88082_i2c_inited = TD_FALSE;
+
+static td_s32 aw88082_write_reg(td_u8 reg, td_u16 val)
+{
+ td_s32 ret;
+ td_u8 send_data[] = {reg, (val >> I2C_SEND_DATA_SHIFT_COUNT), val & 0xff}; // size 3
+ td_u8 send_len = (td_u8)(sizeof(send_data) / sizeof(send_data[0]));
+
+#if (SAP_OS_TYPE != os_type_xtensa)
+ i2c_data_t data;
+ td_u8 tmp;
+
+ data.send_buf = send_data;
+ data.send_len = send_len;
+ data.receive_buf = NULL;
+ data.receive_len = 0;
+ for (tmp = 0; tmp < I2C_WRITE_READ_CNT; tmp++) {
+ ret = (td_s32)uapi_i2c_master_write(AW88082_I2C_BUS_ID, AW88082_I2C_ADDR, &data);
+ if (ret != ERRCODE_SUCC) {
+ vendor_printf("uapi_i2c_master_write failed");
+ vendor_log_fun_err(uapi_i2c_master_write, ret);
+ } else {
+ break;
+ }
+ }
+#else
+ ret = i2c_write(AW88082_I2C_ADDR, send_data, (td_u32)send_len);
+ if (ret != send_len) {
+ vendor_log_fun_err(i2c_write, ret);
+ return AUDIO_FAILURE;
+ }
+#endif
+
+ return ret;
+}
+
+static td_s32 aw88082_read_reg(td_u8 reg, td_u8 *val)
+{
+ td_s32 ret;
+ td_u8 x;
+
+#if (SAP_OS_TYPE != os_type_xtensa)
+ i2c_data_t data;
+ td_u8 tmp;
+
+ data.send_buf = ®
+ data.send_len = 1; /* 1: reg data len */
+ data.receive_buf = val;
+ data.receive_len = REC_I2C_DATA_LEN;
+ for (tmp = 0; tmp < I2C_WRITE_READ_CNT; tmp++) {
+ ret = (td_s32)uapi_i2c_master_writeread(AW88082_I2C_BUS_ID, AW88082_I2C_ADDR, &data);
+ if (ret != ERRCODE_SUCC) {
+ vendor_printf("uapi_i2c_master_writeread failed");
+ vendor_log_fun_err(uapi_i2c_master_writeread, ret);
+ } else {
+ break;
+ }
+ }
+
+ /* swap high and low byte since 88082 send big endian data. */
+ x = val[0];
+ val[0] = val[1];
+ val[1] = x;
+#else
+ ret = i2c_read(AW88082_I2C_ADDR, reg, val, REC_I2C_DATA_LEN);
+ if (ret != REC_I2C_DATA_LEN) {
+ vendor_log_fun_err(i2c_read, ret);
+ return AUDIO_FAILURE;
+ }
+#endif
+
+ return ret;
+}
+
+td_s32 i2c_write_bits(td_u8 reg_addr, td_u32 mask, td_u32 reg_data)
+{
+ td_s32 ret = -1;
+ td_u32 reg_val = 0;
+ ret = aw88082_read_reg(reg_addr, ®_val);
+ if (ret < 0) {
+ return ret;
+ }
+ reg_val &= mask;
+ reg_val |= reg_data;
+ ret = aw88082_write_reg(reg_addr, reg_val);
+ if (ret < 0) {
+ return ret;
+ }
+ return AUDIO_SUCCESS;
+}
+
+/* aw_init(): register configuration sequence */
+const td_u16 config_register[] = {
+ 0x03, 0x61FF,
+ 0x04, 0x2246,
+ 0x05, 0x8000,
+ 0x06, 0x0CE8,
+ 0x07, 0x0010,
+ 0x08, 0x0056,
+ 0x09, 0x5F6A,
+ 0x0A, 0x000F,
+ 0x0B, 0x01E0,
+ 0x0C, 0x1C1E,
+ 0x0D, 0x00D8,
+ 0x0E, 0x94B5,
+ 0x11, 0x025F,
+ 0x13, 0x1B00,
+ 0x14, 0x2180,
+ 0x15, 0x8398,
+ 0x16, 0x02BE,
+ 0x17, 0x441A,
+ 0x18, 0x4001,
+ 0x19, 0x0000,
+ 0x30, 0x460C,
+ 0x31, 0xC989,
+ 0x32, 0x3541,
+ 0x33, 0x4DB8,
+ 0x34, 0xD6F9,
+ 0x35, 0x7ACE,
+ 0x36, 0xEC7C,
+ 0x37, 0x000C,
+ 0x38, 0x0400,
+ 0x40, 0x2250,
+ 0x41, 0x9D0B,
+ 0x42, 0x1A60,
+ 0x54, 0x2768,
+ 0x55, 0x0202,
+ 0x56, 0x3800,
+ 0x57, 0x8C88,
+ 0x58, 0x8909,
+ 0x59, 0x28A4,
+ 0x5A, 0x0000,
+ 0x5B, 0x0000,
+ 0x5C, 0x0140,
+ 0x6F, 0x0002,
+ 0x70, 0x0000,
+ 0x71, 0x0043,
+};
+
+static td_void aw_reg_update()
+{
+ td_s32 i = 0;
+ uint16_t *data = NULL;
+ td_s32 data_len;
+ td_u32 reg_addr = 0;
+ td_u32 reg_val = 0;
+
+ data = (uint16_t *)config_register;
+ data_len = sizeof(config_register) / sizeof(uint16_t);
+
+ for (i = 0; i < data_len; i += 2) { /* 2 is offset */
+ reg_addr = data[i];
+ reg_val = data[i + 1];
+
+ /* Operate the specified register according to the timing requirements */
+ if (reg_addr == 0x04) {
+ reg_val |= (1<<0); // power down, set bit0 1
+ reg_val &= ~(1<<2); // pll disable, set bit2 0
+ reg_val &= ~(1<<1); // class D disable, set bit1 0
+ reg_val |= (1<<8); // mute enable, set bit8 1
+ }
+ aw88082_write_reg(reg_addr, reg_val); /* update register sequence */
+ }
+}
+
+td_void aw_init(td_void)
+{
+ aw_reg_update();
+}
+
+td_void aw_pa_stop(td_void)
+{
+ td_u32 reg_val = 0;
+
+ /* step1: clear inturrupt */
+ aw88082_read_reg(0x02, ®_val);
+ aw88082_read_reg(0x02, ®_val);
+
+ aw88082_write_reg(0x03, 0xffff);
+
+ /* step2:set mute */
+ i2c_write_bits(0x04, (~(1<<8)), 1<<8); /* 1, 8 for reg option */
+
+ vendor_msleep(5); /* delay 5ms */
+
+ /* step3:amppd down */
+ i2c_write_bits(0x04, (~(1<<1)), 0<<0);
+
+ /* step4:power down */
+ i2c_write_bits(0x04, (~(1<<2)), 0<<0); /* 1, 2 for reg option */
+ i2c_write_bits(0x04, (~(1<<0)), 1<<0);
+}
+
+static td_s32 aw_mode1_pll_check()
+{
+ td_s32 ret = AUDIO_FAILURE;
+ td_u8 i;
+ td_u32 reg_val = 0;
+
+ for (i = 0; i < 10; i++) { /* check 10 times */
+ aw88082_read_reg(0x01, ®_val);
+ if (reg_val & (1<<0)) {
+ ret = AUDIO_SUCCESS;
+ break;
+ } else {
+ vendor_msleep(2); /* delay 2ms */
+ }
+ }
+
+ return ret;
+}
+
+static td_s32 aw_mode2_pll_check()
+{
+ td_s32 ret = AUDIO_FAILURE;
+ td_u32 reg_val = 0;
+
+ aw88082_read_reg(0x54, ®_val);
+ reg_val &= (1<<13); /* 1, 13 for reg option */
+ if (reg_val == (0<<13)) { /* if divided, check failed */
+ return ret;
+ }
+
+ i2c_write_bits(0x54, (~(1<<13)), 0<<13); /* 1, 13 for reg option, change to divided */
+ ret = aw_mode1_pll_check();
+ i2c_write_bits(0x54, (~(1<<13)), 1<<13); /* 1, 13 for reg option, change to bypass */
+ if (ret == 0) {
+ vendor_msleep(2); /* delay 2ms */
+ ret = aw_mode1_pll_check();
+ }
+ return ret;
+}
+
+static td_s32 aw_syspll_check()
+{
+ td_s32 ret = AUDIO_FAILURE;
+
+ ret = aw_mode1_pll_check();
+ if (ret < 0) {
+ vendor_log_fun_err(aw_mode1_pll_check, ret);
+ ret= aw_mode2_pll_check();
+ if (ret < 0) { /* if mode2 check failed, syspll check failed */
+ vendor_log_fun_err(aw_mode2_pll_check, ret);
+ return ret;
+ }
+ }
+ return ret;
+}
+
+static td_s32 aw_sysst_check()
+{
+ td_s32 ret = AUDIO_FAILURE;
+ td_u8 i = 0;
+ td_u32 reg_val = 0;
+
+ for (i = 0; i < 10; i++) { /* check 10 times */
+ aw88082_read_reg(0x01, ®_val);
+ if (((reg_val & 0x4b1b) & 0x111) == 0x111) {
+ printf("aw_sysst_check succed\n");
+ ret = AUDIO_SUCCESS; /* check pass */
+ break;
+ } else {
+ vendor_msleep(2); /* if check failed, delay 2ms and check again */
+ }
+ }
+ return ret;
+}
+
+td_s32 aw_pa_start(td_void)
+{
+ td_s32 ret = AUDIO_FAILURE;
+ td_u32 reg_val = 0;
+
+ /* step1:power on */
+ i2c_write_bits(0x04, (~(1<<0)), 0<<0);
+ i2c_write_bits(0x04, (~(1<<2)), 1<<2); /* 1, 2 for reg option */
+
+ vendor_msleep(2); /* delay 2ms */
+ /* step2:syspll check */
+ ret = aw_syspll_check();
+ if (ret < 0) {
+ vendor_log_fun_err(aw_syspll_check, ret);
+ /* if syspll check failed, PA power down */
+ i2c_write_bits(0x04, (~(1<<0)), 1<<0);
+ return ret;
+ }
+
+ /* step3: amppd on */
+ i2c_write_bits(0x04, (~(1<<1)), 1<<1);
+
+ vendor_msleep(2); /* delay 2ms */
+
+ /* step4: sys check */
+ ret = aw_sysst_check();
+ if (ret < 0) {
+ vendor_log_fun_err(aw_sysst_check, ret);
+ /* if sys check failed, PA stop */
+ aw_pa_stop();
+ return ret;
+ }
+
+ /* step5: disable mute */
+ i2c_write_bits(0x04, (~(1<<8)), 0<<4); /* 1, 8, 4 for reg option */
+
+ /* step6: clear inturrupt */
+ aw88082_read_reg(0x02, ®_val);
+ aw88082_read_reg(0x02, ®_val);
+
+ printf("aw_pa_start \n");
+ return AUDIO_SUCCESS;
+}
+
+static td_s32 aw88082_i2c_init(td_void)
+{
+ td_s32 ret;
+ vendor_func_enter();
+
+#if (SAP_OS_TYPE != os_type_xtensa)
+ /* init i2c */
+ vendor_trace_log_u32(AW88082_I2C_BUS_ID);
+ ret = (td_s32)uapi_i2c_master_init(AW88082_I2C_BUS_ID, AW88082_I2C_BAUDRATE, 0);
+ if (ret != AUDIO_SUCCESS) {
+ vendor_log_fun_err(uapi_i2c_master_init, ret);
+ return ret;
+ }
+#endif
+
+ vendor_printf("aw88082 i2c init success\n");
+ vendor_func_exit();
+ return AUDIO_SUCCESS;
+}
+
+static td_s32 aw88082_i2c_deinit(td_void)
+{
+ td_s32 ret;
+ vendor_func_enter();
+
+#if (SAP_OS_TYPE != os_type_xtensa)
+ /* deinit i2c */
+ vendor_trace_log_u32(AW88082_I2C_BUS_ID);
+ ret = (td_s32)uapi_i2c_deinit(AW88082_I2C_BUS_ID);
+ if (ret != AUDIO_SUCCESS) {
+ vendor_log_fun_err(uapi_i2c_deinit, ret);
+ return ret;
+ }
+#endif
+
+ vendor_printf("aw88082 i2c deinit success\n");
+ vendor_func_exit();
+ return AUDIO_SUCCESS;
+}
+
+td_s32 audio_aw88082_init(const uapi_vendor_codec_attr *attr)
+{
+ td_s32 ret;
+
+ if (g_aw88082_i2c_inited != TD_TRUE) {
+ ret = aw88082_i2c_init();
+ if (ret != AUDIO_SUCCESS) {
+ vendor_log_fun_err(aw88082_i2c_init, ret);
+ return ret;
+ }
+ g_aw88082_i2c_inited = TD_TRUE;
+ } else {
+ ret = AUDIO_SUCCESS;
+ }
+
+ aw_init();
+
+ vendor_unused(attr);
+ return ret;
+}
+
+td_s32 audio_aw88082_start(td_void)
+{
+ /* awinic:The platform needs to output I2s first, and then start */
+ td_s32 ret;
+
+ vendor_msleep(100); /* delay 100ms */
+
+ if (g_aw88082_i2c_inited != TD_TRUE) {
+ ret = aw88082_i2c_init();
+ if (ret != AUDIO_SUCCESS) {
+ vendor_log_fun_err(aw88082_i2c_init, ret);
+ return ret;
+ }
+ g_aw88082_i2c_inited = TD_TRUE;
+ }
+
+ aw_init();
+
+ return aw_pa_start();
+}
+
+td_s32 audio_aw88082_deinit(td_void)
+{
+ td_s32 ret;
+
+ aw_pa_stop();
+
+ if (g_aw88082_i2c_inited != TD_FALSE) {
+ ret = aw88082_i2c_deinit();
+ if (ret != AUDIO_SUCCESS) {
+ vendor_log_fun_err(aw88082_i2c_deinit, ret);
+ return ret;
+ }
+ g_aw88082_i2c_inited = TD_FALSE;
+ } else {
+ ret = AUDIO_SUCCESS;
+ }
+
+ return AUDIO_SUCCESS;
+}
--- /dev/null
+/*\r
+ * Copyright (c) CompanyNameMagicTag 2020-2021. All rights reserved.\r
+ * Description: header file for AW88082 driver\r
+ */\r
+\r
+#ifndef AW88082_PA_H\r
+#define AW88082_PA_H\r
+\r
+#include "soc_uapi_vendor.h"\r
+\r
+td_s32 audio_aw88082_init(const uapi_vendor_codec_attr *attr);\r
+td_s32 audio_aw88082_deinit(td_void);\r
+\r
+#endif\r
#else
{ S_AGPIO_R10, BUTTON_1 },
#endif
+#ifdef BOARD_LEINIAO
+ { S_AGPIO_L12, BUTTON_2 },
+ { PIN_NONE, BUTTON_3 },//S_AGPIO_L28
+#else
{ PIN_NONE, BUTTON_2 },
- { PIN_NONE, BUTTON_3 },
+ { PIN_NONE, BUTTON_3 },//S_AGPIO_L28
+#endif
{ PIN_NONE, BUTTON_4 },
{ PIN_NONE, BUTTON_5 },
{ PIN_NONE, BUTTON_6 },
data.keyId = INDEV_KEY_FUNC;
} else if (id == BUTTON_2) {
data.keyId = INDEV_KEY_FUNC2;
+ } else if (id == BUTTON_3) {
+ data.keyId = INDEV_KEY_FUNC3;
}
data.state = state; // 2:longpress 1:press 0:release
g_button_event_cb(&data);
static void button_report_event(button_id_t id, event_button_t event)
{
input_dev_data_t data;
-
+ // printf("id : %d\n",id);
switch (event) {
case BUTTON_PWR_PRESS:
#ifdef SUPPORT_POWER_MANAGER
break;
case BUTTON1_CLICKUP:
button_report_event_to_gui(id, 0); // 0:release
-#ifdef BOARD_U8
+// #ifdef BOARD_U8
case BUTTON2_PRESS:
button_report_event_to_gui(id, 1); // 1:press
break;
case BUTTON2_CLICKUP:
button_report_event_to_gui(id, 0); // 0:release
-#endif
+
+ case BUTTON3_PRESS:
+ button_report_event_to_gui(id, 1); // 1:press
+ break;
+ case BUTTON3_CLICKUP:
+ button_report_event_to_gui(id, 0); // 0:release
+// #endif
default:
break;
}
if (id == BUTTON_1) {
event = BUTTON1_START;
}
-#ifdef BOARD_U8
if(id == BUTTON_2)
{
event = BUTTON2_START;
}
-#endif
+ if(id == BUTTON_3)
+ {
+ event = BUTTON3_START;
+ }
if ((state == BUTTON_PRESS) ||
(state == BUTTON_CLICK) ||
(state == BUTTON_DOUBLE_CLICK)||
BUTTON2_LONGPRESS_8S_OVER,
BUTTON2_LONGPRESS_9S_OVER,
BUTTON2_INVALID,
+
+ BUTTON3_START,
+ BUTTON3_PRESS,
+ BUTTON3_CLICKUP,
+ BUTTON3_CLICKUP_2,
+ BUTTON3_LONGPRESS_1S,
+ BUTTON3_LONGPRESS_2S,
+ BUTTON3_LONGPRESS_3S,
+ BUTTON3_LONGPRESS_4S,
+ BUTTON3_LONGPRESS_5S,
+ BUTTON3_LONGPRESS_6S,
+ BUTTON3_LONGPRESS_7S,
+ BUTTON3_LONGPRESS_8S,
+ BUTTON3_LONGPRESS_9S,
+ BUTTON3_LONGPRESS_1S_OVER,
+ BUTTON3_LONGPRESS_2S_OVER,
+ BUTTON3_LONGPRESS_3S_OVER,
+ BUTTON3_LONGPRESS_4S_OVER,
+ BUTTON3_LONGPRESS_5S_OVER,
+ BUTTON3_LONGPRESS_6S_OVER,
+ BUTTON3_LONGPRESS_7S_OVER,
+ BUTTON3_LONGPRESS_8S_OVER,
+ BUTTON3_LONGPRESS_9S_OVER,
+ BUTTON3_INVALID,
BUTTON_BUTT
} event_button_t;
* define AUDIO_SMARTPA_AW88166 : macro to init smartpa aw88166;\r
* define AUDIO_SMARTPA_AW88166_I2S_ID UAPI_SND_OUT_PORT_I2S0 : macro to specify i2s id connecting to smartpa aw88166;\r
*/\r
+\r
+#ifdef AUDIO_SMARTPA_AW88082\r
+#define AUDIO_SMARTPA_AW88082_I2S_ID UAPI_SND_OUT_PORT_I2S0\r
+#else\r
#if 0\r
#define AUDIO_SMARTPA_AW88262\r
#define AUDIO_SMARTPA_AW88262_I2S_ID UAPI_SND_OUT_PORT_I2S2\r
#define AUDIO_SMARTPA_AW88166\r
#define AUDIO_SMARTPA_AW88166_I2S_ID UAPI_SND_OUT_PORT_I2S0\r
#endif\r
+#endif\r
#endif /* DSP_EXIST */\r
#include "panic.h"\r
#include "los_exc.h"\r
}\r
#endif /* AUDIO_SMARTPA_AW88262 */\r
\r
+#ifdef AUDIO_SMARTPA_AW88082\r
+td_s32 audio_aw88082_init(const uapi_vendor_codec_attr *attr);\r
+td_s32 audio_aw88082_deinit(td_void);\r
+td_s32 audio_aw88082_start(td_void);\r
+\r
+static uapi_vendor_driver g_aw88082_driver = {\r
+ .out_port = AUDIO_SMARTPA_AW88082_I2S_ID,\r
+ .init = audio_aw88082_start,\r
+ .deinit = audio_aw88082_deinit,\r
+ .set_aef_profile = TD_NULL,\r
+};\r
+\r
+static td_s32 audio_aw88082_register_driver(void)\r
+{\r
+ const uapi_vendor_codec_attr attr = {};\r
+\r
+ audio_aw88082_init(&attr);\r
+\r
+ return uapi_audio_vendor_register(&g_aw88082_driver);\r
+}\r
+#endif /* AUDIO_SMARTPA_AW88082 */\r
+\r
#ifdef AUDIO_SMARTPA_AW88166\r
td_s32 audio_aw88166_init(const uapi_vendor_codec_attr *attr);\r
td_s32 audio_aw88166_deinit(td_void); /* Call when device power off */\r
}\r
#endif /* AUDIO_SMARTPA_AW88262 */\r
\r
+#ifdef AUDIO_SMARTPA_AW88082\r
+ ret = (uint32_t)audio_aw88082_register_driver();\r
+ if (ret != 0) {\r
+ PRINT("aw88082 register driver error\r\n");\r
+ }\r
+#endif /* AUDIO_SMARTPA_AW88082 */\r
+\r
#ifdef AUDIO_SMARTPA_AW88166\r
ret = (uint32_t)audio_aw88166_register_driver();\r
if (ret != 0) {\r
static void fs_init(void)
{
#ifdef GPIO_POWERON_FLASH
+#ifdef BOARD_LEINIAO
+ uapi_gpio_set_dir(S_AGPIO_L14,GPIO_DIRECTION_OUTPUT);
+ uapi_gpio_set_val(S_AGPIO_L14,GPIO_LEVEL_HIGH);
+#else
uapi_gpio_set_dir(S_AGPIO_L18,GPIO_DIRECTION_OUTPUT);
uapi_gpio_set_val(S_AGPIO_L18,GPIO_LEVEL_HIGH);
#endif
+#endif
#ifdef CFG_DRIVERS_NANDFLASH
nandflash_qspi_init();
#endif
set(SOURCES
${CMAKE_CURRENT_SOURCE_DIR}/nandflash_ds35x1g.c
${CMAKE_CURRENT_SOURCE_DIR}/nandflash_f35uqa001g.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/nandflash_gd5f2gm7re.c
${CMAKE_CURRENT_SOURCE_DIR}/nandflash_w25n01g.c
${CMAKE_CURRENT_SOURCE_DIR}/nandflash_config.c
${CMAKE_CURRENT_SOURCE_DIR}/hal_nandflash.c
--- /dev/null
+/*
+ * @Author: penglei 1624952103@qq.com
+ * @Date: 2025-09-04 10:28:47
+ * @LastEditors: penglei 1624952103@qq.com
+ * @LastEditTime: 2025-09-05 10:09:36
+ * @FilePath: /FD230/code/sdk/bootloader/flashboot/brandy/nandflash/include/nandflash_gd5f2gm7re.h
+ * @Description: 这是默认设置,请设置`customMade`, 打开koroFileHeader查看配置 进行设置: https://github.com/OBKoro1/koro1FileHeader/wiki/%E9%85%8D%E7%BD%AE
+ */
+/*
+ * Copyright (c) @CompanyNameMagicTag 2018-2020. All rights reserved.
+ * Description: NON-OS NANDFLASH DRIVER
+ * Author: @CompanyNameTag
+ * Create: 2020-10-15
+ */
+
+#ifndef NANDFLASH_GD5F2GM7RE_H
+#define NANDFLASH_GD5F2GM7RE_H
+
+#define GD5F2GM7RE_BYTES_PER_PAGE 2048
+#define GD5F2GM7RE_BYTES_PER_OOB 64
+#define GD5F2GM7RE_PAGES_PER_BLOCK 64
+#define GD5F2GM7RE_TOTAL_BLOCKS 2048
+#define GD5F2GM7RE_CHIP_ID 0xC881
+#define GD5F2GM7RE_OOB_TOTAL_LEN 4
+#define GD5F2GM7RE_OOB_PER_SIZE 8
+#define GD5F2GM7RE_OOB_1_OFFSET 0
+#define GD5F2GM7RE_OOB_2_OFFSET 16
+#define GD5F2GM7RE_OOB_3_OFFSET 32
+#define GD5F2GM7RE_OOB_4_OFFSET 48
+
+extern struct nand_driver_struct g_gd5f2gm7re_driver;
+
+#endif /* End of #ifndef MC_NAND_GD5F2GM7RE_H */
#include "nandflash_ds35x1g.h"\r
#include "nandflash_w25n01g.h"\r
#include "nandflash_f35uqa001g.h"\r
+#include "nandflash_gd5f2gm7re.h"\r
#include "nandflash_inner.h"\r
#include "nandflash.h"\r
#include "hal_nandflash.h"\r
return &g_ds35x1g_driver;\r
#elif defined(NANDFLASH_F35UQA)\r
return &g_f35uqa001g_driver;\r
+ #elif defined(NANDFLASH_GD5F2G)\r
+ return &g_gd5f2gm7re_driver; \r
#else\r
return &g_ds35x1g_driver; \r
#endif\r
--- /dev/null
+/*
+ * Copyright (c) @CompanyNameMagicTag 2018-2020. All rights reserved.
+ * Description: NON-OS NANDFLASH DRIVER
+ * Author: @CompanyNameTag
+ * Create: 2020-10-15
+ */
+
+#include <stdint.h>
+#include "debug_print.h"
+#include "nandflash_inner.h"
+#include "nandflash.h"
+#include "hal_nandflash.h"
+#include "nandflash_config.h"
+#include "nandflash_gd5f2gm7re.h"
+
+#define GD5F2GM7RE_GET_ECC_STATUS(x) ((0x30 & (x)) >> 4)
+#define GD5F2GM7RE_ECC_CORRECTION 0x00
+#define GD5F2GM7RE_ECC_1BIT_CORRET 0x01
+#define GD5F2GM7RE_ECC_4BIT_CORRET 0x02
+#define GD5F2GM7RE_ECC_ERROR 0x03
+#define NAND_ID_DATA_SIZE 0x2
+
+static qspi_data_type_def g_qspi_data = {0};
+
+static uint32_t mc_gd5f2gm7re_read_page(
+ uint32_t nand_page, uint8_t *data, uint32_t data_len, uint8_t *oob, uint32_t oob_len, const uint32_t *ecc_result)
+{
+ uint32_t ret;
+ uint8_t status_reg;
+
+ UNUSED(ecc_result);
+ ret = mc_flash_read_page(nand_page, data, data_len, oob, oob_len, &status_reg);
+ if (get_nand_flash()->enable_ecc == true) {
+ if (GD5F2GM7RE_GET_ECC_STATUS(status_reg) >= GD5F2GM7RE_ECC_ERROR) {
+ return MC_FAILURE;
+ } else {
+ return MC_SUCCESS;
+ }
+ }
+ return ret;
+}
+
+static uint32_t mc_gd5f2gm7re_init(void)
+{
+ nand_driver_init(SPEED_MID);
+ PRINT("gd5f2gm7re_init \r\n");
+ uint32_t ret;
+ mc_flash_write_cmd(CMD_FLASH_RESET); /* tRST 5us,no command will be accepted */
+ mc_flash_busy_wait();
+ write_cmd(CMD_FLASH_WREN);
+ ret = mc_flash_write_sr(CMD_FLASH_SR1_ADDR, 0x0); /* set SR1 0,Clear block protect bits */
+ if (get_nand_flash()->enable_ecc == true) {
+ ret = mc_flash_write_sr(CMD_FLASH_SR2_ADDR, 0x11); /* set SR1 0,Clear block protect bits */
+ } else {
+ ret = mc_flash_write_sr(CMD_FLASH_SR2_ADDR, 0x01); /* set SR1 0,Clear block protect bits */
+ }
+ PRINT("nandflash mc_flash_write_sr ret %d \r\n", ret);
+ uint8_t status_reg;
+ mc_flash_read_sr(CMD_FLASH_SR1_ADDR, (uint8_t *)&status_reg);
+ PRINT("nandflash A0 Reg:0x%x \r\n", status_reg);
+ mc_flash_read_sr(CMD_FLASH_SR2_ADDR, (uint8_t *)&status_reg);
+ PRINT("nandflash B0 Reg:0x%x \r\n", status_reg);
+ mc_flash_read_sr(CMD_FLASH_SR3_ADDR, (uint8_t *)&status_reg);
+ PRINT("nandflash C0 Reg:0x%x \r\n", status_reg);
+ if (ret != MC_SUCCESS || status_reg != 0x2) {
+ return MC_FAILURE;
+ }
+ return MC_SUCCESS;
+}
+
+static uint16_t mc_gd5f2gm7re_check_id(void)
+{
+ g_qspi_data.instruction = CMD_FLASH_ID;
+ g_qspi_data.address_mode = MC_OSPI_ADDRESS_NONE;
+ g_qspi_data.address = 0;
+ g_qspi_data.address_size = 0;
+ g_qspi_data.dummy_cycles = MC_OSPI_CYCLES_8_BITS;
+ g_qspi_data.data_mode = MC_OSPI_DATA_1_LINE;
+ g_qspi_data.data_size = NAND_ID_DATA_SIZE;
+ uint16_t nand_flash_id = read_id(&g_qspi_data);
+ PRINT("nandflash id 0x%04X \r\n",nand_flash_id);
+ return nand_flash_id;
+}
+
+struct nand_driver_struct g_gd5f2gm7re_driver = {mc_gd5f2gm7re_init,
+ mc_gd5f2gm7re_check_id,
+ mc_gd5f2gm7re_read_page,
+ mc_flash_write_page,
+ mc_flash_erase_block,
+ mc_flash_mark_bad_block,
+ mc_flash_check_bad_block,
+ GD5F2GM7RE_BYTES_PER_PAGE,
+ GD5F2GM7RE_BYTES_PER_OOB,
+ GD5F2GM7RE_PAGES_PER_BLOCK,
+ GD5F2GM7RE_TOTAL_BLOCKS,
+ GD5F2GM7RE_CHIP_ID,
+ GD5F2GM7RE_OOB_TOTAL_LEN,
+ GD5F2GM7RE_OOB_PER_SIZE,
+ GD5F2GM7RE_OOB_PER_SIZE,
+ GD5F2GM7RE_OOB_PER_SIZE,
+ GD5F2GM7RE_OOB_PER_SIZE,
+ GD5F2GM7RE_OOB_1_OFFSET,
+ GD5F2GM7RE_OOB_2_OFFSET,
+ GD5F2GM7RE_OOB_3_OFFSET,
+ GD5F2GM7RE_OOB_4_OFFSET,
+#ifdef ENABLE_ECC
+ true
+#else
+ false
+#endif
+ };
'SINGLE_USER_PARTITION',
# 'TPTYPE_FT6X46',
# 'ROTARYENCODER_HX3507',
- 'NANDFLASH_F35UQA',
+ # 'NANDFLASH_F35UQA',
+ 'NANDFLASH_GD5F2G',
'BLE_INSTRUCT',
- '-:SUPPORT_ALIPAY_SEC'
+ '-:SUPPORT_ALIPAY_SEC',
# 'AILPAY_SUPPORT',
# 'SUPPORT_FACTORY_SERVICE',
# 'MEMORY_CORRUPTION',
-
+ 'SAP_EFFECT_SWS_SUPPORT',
+ 'AUDIO_SMARTPA_AW88082',
],
#添加自定义应用
'ram_component': [
'defines': [
'BOARD_LEINIAO',
'FT_SINGLE_UART',
- 'NANDFLASH_F35UQA',
+ # 'NANDFLASH_F35UQA',
+ 'NANDFLASH_GD5F2G',
# 'TPTYPE_FT6X46',
'CFG_FLASH_SIZE=16',
'LEINIAO',
'CFG_DRIVERS_NANDFLASH',
'CFG_FLASH_SIZE=16',
'LEINIAO',
- 'NANDFLASH_F35UQA'
+ # 'NANDFLASH_F35UQA',
+ 'NANDFLASH_GD5F2G',
+ 'GPIO_POWERON_FLASH'
]
},
}
#include "gpio_porting.h"
#include "platform_types.h"
-#ifdef ENABLE_BN02
-extern void bp_int_callback(pin_t pin, uintptr_t param);
-#endif
-
-#ifdef SUPPORT_PPG_SERVICE
-extern void ppg_int_callback(pin_t pin, uintptr_t param);
-#endif
-
-#ifdef SUPPORT_GYRO_SERVICE
-extern void gyro_int_callback(pin_t pin, uintptr_t param);
-#endif
-
-#ifdef ROTARYENCODER_MIXO
-extern void mixo_int_callback(pin_t pin, uintptr_t param);
-#endif
-
-#ifdef SUPPORT_CYWEE_SERVICE
-extern void cywee_int_callback(pin_t pin, uintptr_t param);
-#endif
-
/**
* @addtogroup connectivity_config_boards
* @{
{ HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_MAX, HAL_PIO_IE_ENBALE }, // S_AGPIO_L12 i2c data HX3507_SDIO
{ HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_MAX, HAL_PIO_IE_DISABLE }, // S_AGPIO_L13 i2c CLK HX3507_SCLK
- { HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_DOWN, HAL_PIO_IE_DISABLE }, // S_AGPIO_L14 NC
+ { HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_UP, HAL_PIO_IE_DISABLE }, // S_AGPIO_L14 NC
{ HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_DOWN, HAL_PIO_IE_DISABLE }, // S_AGPIO_L15 NC
{ HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_DOWN, HAL_PIO_IE_DISABLE }, // S_AGPIO_L16 NC
{ HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_DOWN, HAL_PIO_IE_DISABLE }, // S_AGPIO_L17 HX3507_INT not use
- { HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_UP, HAL_PIO_IE_DISABLE }, // S_AGPIO_L18 VDDEN //暂时无用，采用VDDIO 默认开启 EXt V3.0 EXt V1.8
+ { HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_MAX, HAL_PIO_IE_DISABLE }, // S_AGPIO_L18 VDDEN //暂时无用，采用VDDIO 默认开启 EXt V3.0 EXt V1.8
{ HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_UP, HAL_PIO_IE_DISABLE }, // S_AGPIO_L19 G_INT2 //暂时不用
{ HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_MAX, HAL_PIO_IE_DISABLE }, // S_AGPIO_L25 //////////// audio pa reset
{ HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_MAX, HAL_PIO_IE_DISABLE }, // S_AGPIO_L26 心率复位 PPG reset
{ HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_MAX, HAL_PIO_IE_DISABLE }, // S_AGPIO_L27 LCM reset
- { HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_MAX, HAL_PIO_IE_DISABLE }, // S_AGPIO_L28 CAT_1复位 CAT1_RESET_N 拉低有效
+ { HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_MAX, HAL_PIO_IE_ENBALE }, // S_AGPIO_L28 CAT_1复位 CAT1_RESET_N 拉低有效 key4
{ HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_MAX, HAL_PIO_IE_ENBALE }, // S_AGPIO_L29 charge done info 检测是否充满电
{ HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_MAX, HAL_PIO_IE_DISABLE }, // S_AGPIO_L30 KP_MKIN1 唤醒 CAT1 ，输出
{ HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_MAX, HAL_PIO_IE_ENBALE }, // S_AGPIO_L31 KP_MKOUIT1 唤醒 蓝牙 ,输入
// #else
{ HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_DOWN, HAL_PIO_IE_DISABLE }, // S_AGPIO_R2 VIBR_PWM 马达控制脚 兼容预留马达驱动复位脚
// #endif
-#ifdef BOARD_LEINIAO
+#ifdef BOARD_N9
{ HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_UP, HAL_PIO_IE_ENBALE }, // S_AGPIO_R3 NC
#else
{ HAL_PIO_FUNC_GPIO, HAL_PIO_DRIVE_MAX, HAL_PIO_PULL_UP, HAL_PIO_IE_DISABLE },
// S_AGPIO_L23 CAT_1_PWR_ON ----- high power on
{ S_AGPIO_L23, HAL_GPIO_DIRECTION_OUTPUT, HAL_GPIO_LEVEL_HIGH, 0, NULL },
// S_AGPIO_L28 Cat1 reset ---- low reset
- { S_AGPIO_L28, HAL_GPIO_DIRECTION_OUTPUT, HAL_GPIO_LEVEL_HIGH, 0, NULL },
+ { S_AGPIO_L24, HAL_GPIO_DIRECTION_OUTPUT, HAL_GPIO_LEVEL_HIGH, 0, NULL },
#else
// S_AGPIO_L23 CAT_1_PWR_ON ----- high power on
{ S_AGPIO_L23, HAL_GPIO_DIRECTION_OUTPUT, HAL_GPIO_LEVEL_LOW, 0, NULL },
// S_AGPIO_L28 Cat1 reset ---- low reset
- { S_AGPIO_L28, HAL_GPIO_DIRECTION_OUTPUT, HAL_GPIO_LEVEL_LOW, 0, NULL },
+ // { S_AGPIO_L28, HAL_GPIO_DIRECTION_OUTPUT, HAL_GPIO_LEVEL_LOW, 0, NULL },
#endif
// S_AGPIO_L17 HX3507_INT
// { S_AGPIO_L17, HAL_GPIO_DIRECTION_INPUT, HAL_GPIO_LEVEL_LOW, 0, NULL },
// S_AGPIO_L12 SDIO_BT
- { S_AGPIO_L12, HAL_GPIO_DIRECTION_OUTPUT, HAL_GPIO_LEVEL_LOW, 0, NULL },
- // S_AGPIO_L13 SCLK_BT
- { S_AGPIO_L13, HAL_GPIO_DIRECTION_OUTPUT, HAL_GPIO_LEVEL_LOW, 0, NULL },
+ // { S_AGPIO_L12, HAL_GPIO_DIRECTION_OUTPUT, HAL_GPIO_LEVEL_LOW, 0, NULL },
+ // // S_AGPIO_L13 SCLK_BT
+ // { S_AGPIO_L13, HAL_GPIO_DIRECTION_OUTPUT, HAL_GPIO_LEVEL_LOW, 0, NULL },
// S_AGPIO_L26 心率复位 PPG reset
{ S_AGPIO_L26, HAL_GPIO_DIRECTION_OUTPUT, HAL_GPIO_LEVEL_LOW, 0, NULL },
//默认关闭马达
{ S_AGPIO_R2, HAL_GPIO_DIRECTION_OUTPUT, HAL_GPIO_LEVEL_LOW, 0, NULL },
//默认开启 EXT LDO V3.0 V1.8
- { S_AGPIO_L18, HAL_GPIO_DIRECTION_OUTPUT, HAL_GPIO_LEVEL_HIGH, 0, NULL },
+ // { S_AGPIO_L18, HAL_GPIO_DIRECTION_OUTPUT, HAL_GPIO_LEVEL_HIGH, 0, NULL },
+ { S_AGPIO_L14, HAL_GPIO_DIRECTION_OUTPUT, HAL_GPIO_LEVEL_HIGH, 0, NULL },
+
#ifdef SUPPORT_CYWEE_SERVICE
/**G sensor G_INT1 S_AGPIO_L11 G_INT2 S_AGPIO_L19 采用timer 时这些中断要屏蔽*/
// { S_AGPIO_L31, HAL_GPIO_DIRECTION_INPUT, NULL, GPIO_INTERRUPT_RISING_EDGE, cat1_ring_isr_callback},
#endif
-#ifdef SUPPORT_GYRO_SERVICE
- { S_AGPIO_R8, HAL_GPIO_DIRECTION_INPUT, NULL, GPIO_INTERRUPT_RISING_EDGE, gyro_int_callback },
-#else
- /**S_AGPIO_L32 GPO gps reset*/
- // { S_AGPIO_L32, HAL_GPIO_DIRECTION_OUTPUT, HAL_GPIO_LEVEL_LOW, 0, NULL },
-#endif
-#ifdef ENABLE_BN02
- { S_AGPIO_R3, HAL_GPIO_DIRECTION_INPUT, NULL, GPIO_INTERRUPT_RISING_EDGE, bp_int_callback },
-#endif
-#ifdef SUPPORT_PPG_SERVICE
-#ifdef PPG_GH3X2X
- { S_AGPIO_R6, HAL_GPIO_DIRECTION_INPUT, NULL, GPIO_INTERRUPT_RISING_EDGE, ppg_int_callback},
-#elif defined PPG_PAH8009
- // { S_AGPIO_R6, HAL_GPIO_DIRECTION_INPUT, NULL, GPIO_INTERRUPT_FALLING_EDGE, ppg_int_callback},
-#endif
-#endif
-#ifdef ROTARYENCODER_MIXO
- { S_AGPIO_L0, HAL_GPIO_DIRECTION_INPUT, NULL, GPIO_INTERRUPT_FALLING_EDGE, mixo_int_callback},
-#endif
};
/**
* @}
#define BUILTIN_SND_OUT_AUDIO_CH 2 // 参考 soc_uapi_audio.h 中 UAPI_AUDIO_CHANNEL_2 枚举
#define BUILTIN_SND_OUT_BIT_DEPTH 16 // 参考 soc_uapi_audio.h 中 UAPI_AUDIO_BIT_DEPTH_16 枚举
#define BUILTIN_SND_OUT_SAMPLE_RATE 48000 // 参考 soc_uapi_audio.h 中 UAPI_AUDIO_SAMPLE_RATE_48K 枚举
+#ifdef SAP_EFFECT_SWS_SUPPORT
+#define BUILTIN_SND_OUT_I2S_ATTR_I2S_BCLK 4 // 参考 soc_uapi_audio.h 中 UAPI_AUDIO_I2S_BCLK_8_DIV 枚举
+#define BUILTIN_SND_OUT_I2S_ATTR_BIT_DEPTH 32 // 参考 soc_uapi_audio.h 中 UAPI_AUDIO_BIT_DEPTH_16 枚举
+#else
#define BUILTIN_SND_OUT_I2S_ATTR_I2S_BCLK 8 // 参考 soc_uapi_audio.h 中 UAPI_AUDIO_I2S_BCLK_8_DIV 枚举
-#define BUILTIN_SND_OUT_I2S_ATTR_BIT_DEPTH 16 // 参考 soc_uapi_audio.h 中 UAPI_AUDIO_BIT_DEPTH_16 枚举
+#define BUILTIN_SND_OUT_I2S_ATTR_BIT_DEPTH 16
+#endif
#define BUILTIN_SND_OUT_I2S_ATTR_AUDIO_CH 2 // 参考 soc_uapi_audio.h 中 UAPI_AUDIO_CHANNEL_2 枚举
#define BUILTIN_SND_OUT_I2S_ATTR_I2S_STD_MODE 0 // 参考 soc_uapi_audio.h 中 UAPI_AUDIO_I2S_STD_MODE 枚举
#define BUILTIN_SND_OUT_I2S_ATTR_MASTER 1 // 1:主设备,0:从设备
#define CONFIG_SUPPORT_BUTTON_DOUBLE_CLICK YES
// LCD VCI_EN
+#ifdef BOARD_LEINIAO
+#define VCI_LCD_GPIO S_AGPIO_L25
+#else
#define VCI_LCD_GPIO S_AGPIO_L24
+#endif
#define DISPLAY_TE_GPIO S_AGPIO_L22
#define RESET_LCD_GPIO S_AGPIO_L27
//GNSS Config
#define GNSS_RESET_PIN
// TRACK MODE
+#ifdef SAP_EFFECT_SWS_SUPPORT
+#define SND_TRACK_MODE_BT_MUSIC 0 // 参考 soc_uapi_sound.h 中 UAPI_SND_TRACK_STEREO 枚举
+#define SND_TRACK_MODE_BT_SCO 0 // 参考 soc_uapi_sound.h 中 UAPI_SND_TRACK_DOUBLE_MONO 枚举
+#define SND_TRACK_MODE_LOCAL_CAT1 0 // 参考 soc_uapi_sound.h 中 UAPI_SND_TRACK_DOUBLE_MONO 枚举
+#define SND_TRACK_MODE_BT_CAT1 0 // 参考 soc_uapi_sound.h 中 UAPI_SND_TRACK_STEREO 枚举
+#define SND_TRACK_MODE_LOCAL_MUSIC 0 // 参考 soc_uapi_sound.h 中 UAPI_SND_TRACK_DOUBLE_MONO 枚举
+#else
#define SND_TRACK_MODE_BT_MUSIC 0 // 参考 soc_uapi_sound.h 中 UAPI_SND_TRACK_STEREO 枚举
#define SND_TRACK_MODE_BT_SCO 1 // 参考 soc_uapi_sound.h 中 UAPI_SND_TRACK_DOUBLE_MONO 枚举
#define SND_TRACK_MODE_LOCAL_CAT1 1 // 参考 soc_uapi_sound.h 中 UAPI_SND_TRACK_DOUBLE_MONO 枚举
#define SND_TRACK_MODE_BT_CAT1 0 // 参考 soc_uapi_sound.h 中 UAPI_SND_TRACK_STEREO 枚举
#define SND_TRACK_MODE_LOCAL_MUSIC 1 // 参考 soc_uapi_sound.h 中 UAPI_SND_TRACK_DOUBLE_MONO 枚举
-
+#endif
// AEF
#if defined(MEMORY_MINI)
#define SND_PORT_AEF_TYPE 0x130 // 参考 soc_uapi_aef.h 中 UAPI_AEF_TYPE_SWS1 枚举
#else
+#ifdef SAP_EFFECT_SWS_SUPPORT
+#define SND_PORT_AEF_TYPE 0x130 // 参考 soc_uapi_aef.h 中 UAPI_AEF_TYPE_SMARTPA 枚举
+#else
#define SND_PORT_AEF_TYPE 0x180 // 参考 soc_uapi_aef.h 中 UAPI_AEF_TYPE_SMARTPA 枚举
#endif
+#endif
#define SND_PORT_AEF_ENABLE true // true代表开启aef算法，false代表关闭aef算法
#define OPUS_ENC_BIT_RATE 16000 // opus编码码率
return ERR_AO_NULL_PTR;
}
+#ifdef SAP_EFFECT_SWS_SUPPORT
+ /* sws effect do not need to get param */
+ return AUDIO_SUCCESS;
+#endif
+
ret = ao_get_aef_param_bin_by_profile(aef_profile, lib_buf, &lib_buf_size);
if (ret == (td_s32)ERR_AO_NOT_SUPPORTED) {
sap_warn_log_info("No need to load aef alp param bin.");
set(SOURCES
${CMAKE_CURRENT_SOURCE_DIR}/nand/nandflash_ds35x1g.c
${CMAKE_CURRENT_SOURCE_DIR}/nand/nandflash_f35uqa001g.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/nand/nandflash_gd5f2gm7re.c
${CMAKE_CURRENT_SOURCE_DIR}/nand/nandflash_tc58cyg.c
${CMAKE_CURRENT_SOURCE_DIR}/nand/nandflash_w25n01g.c
${CMAKE_CURRENT_SOURCE_DIR}/nand/nandflash_config.c
--- /dev/null
+/*
+ * @Author: penglei 1624952103@qq.com
+ * @Date: 2025-09-04 10:04:03
+ * @LastEditors: penglei 1624952103@qq.com
+ * @LastEditTime: 2025-09-05 10:09:32
+ * @FilePath: /FD230/code/sdk/drivers/drivers/driver/nand_flash/nand/include/nandflash_gd5f2gm7re.h
+ * @Description: 这是默认设置,请设置`customMade`, 打开koroFileHeader查看配置 进行设置: https://github.com/OBKoro1/koro1FileHeader/wiki/%E9%85%8D%E7%BD%AE
+ */
+/*
+ * Copyright (c) @CompanyNameMagicTag 2018-2020. All rights reserved.
+ * Description: NON-OS NANDFLASH DRIVER
+ * Author: @CompanyNameTag
+ * Create: 2020-10-15
+ */
+
+#ifndef NANDFLASH_GD5F2GM7RE_H
+#define NANDFLASH_GD5F2GM7RE_H
+
+#define GD5F2GM7RE_BYTES_PER_PAGE 2048
+#define GD5F2GM7RE_BYTES_PER_OOB 64
+#define GD5F2GM7RE_PAGES_PER_BLOCK 64
+#define GD5F2GM7RE_TOTAL_BLOCKS 2048
+#define GD5F2GM7RE_CHIP_ID 0xC881
+#define GD5F2GM7RE_OOB_TOTAL_LEN 4
+#define GD5F2GM7RE_OOB_PER_SIZE 8
+#define GD5F2GM7RE_OOB_1_OFFSET 0
+#define GD5F2GM7RE_OOB_2_OFFSET 16
+#define GD5F2GM7RE_OOB_3_OFFSET 32
+#define GD5F2GM7RE_OOB_4_OFFSET 48
+
+extern struct nand_driver_struct g_gd5f2gm7re_driver;
+
+#endif /* End of #ifndef MC_NAND_GD5F2GM7RE_H */
#include "nandflash_tc58cyg.h"\r
#include "nandflash_ds35x1g.h"\r
#include "nandflash_f35uqa001g.h"\r
+#include "nandflash_gd5f2gm7re.h"\r
#include "nandflash_w25n01g.h"\r
#include "nandflash_to_os.h"\r
#include "nandflash_inner.h"\r
return &g_ds35x1g_driver;\r
#elif defined(NANDFLASH_F35UQA)\r
return &g_f35uqa001g_driver;\r
+ #elif defined(NANDFLASH_GD5F2G)\r
+ return &g_gd5f2gm7re_driver; \r
#else\r
return &g_ds35x1g_driver; \r
#endif\r
--- /dev/null
+/*
+ * Copyright (c) @CompanyNameMagicTag 2018-2020. All rights reserved.
+ * Description: NON-OS NANDFLASH DRIVER
+ * Author: @CompanyNameTag
+ * Create: 2020-10-15
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include "debug_print.h"
+#include "nandflash_inner.h"
+#include "nandflash.h"
+#include "hal_nandflash.h"
+#include "nandflash_config.h"
+#include "nandflash_gd5f2gm7re.h"
+
+#define GD5F2GM7RE_GET_ECC_STATUS(x) ((0x30 & (x)) >> 4)
+#define GD5F2GM7RE_ECC_CORRECTION 0x00
+#define GD5F2GM7RE_ECC_1BIT_CORRET 0x01
+#define GD5F2GM7RE_ECC_4BIT_CORRET 0x02
+#define GD5F2GM7RE_ECC_ERROR 0x03
+#define NAND_ID_DATA_SIZE 0x2
+
+static qspi_data_type_def g_qspi_data = {0};
+
+static uint32_t mc_gd5f2gm7re_read_page(uint32_t nand_page, uint8_t *data, uint32_t data_len, uint8_t *oob,
+ uint32_t oob_len, const uint32_t *ecc_result, enum nandflash_trans_type type)
+{
+ unused(ecc_result);
+ uint32_t ret;
+ uint8_t status_reg;
+ ret = mc_flash_read_page(nand_page, data, data_len, oob, oob_len, &status_reg, type);
+ if (get_nand_flash()->enable_ecc == true) {
+ if (GD5F2GM7RE_GET_ECC_STATUS(status_reg) >= GD5F2GM7RE_ECC_ERROR) {
+ return MC_FAILURE;
+ } else {
+ return MC_SUCCESS;
+ }
+ }
+ return ret;
+}
+
+static uint32_t mc_gd5f2gm7re_init(void)
+{
+ nand_driver_init(SPEED_MID);
+ nand_driver_sem_init();
+ PRINT("gd5f2gm7re_init \r\n");
+ uint32_t ret;
+ mc_flash_write_cmd(CMD_FLASH_RESET); /* tRST 5us,no command will be accepted */
+ mc_flash_busy_wait();
+ write_cmd(CMD_FLASH_WREN);
+ ret = mc_flash_write_sr(CMD_FLASH_SR1_ADDR, 0x0); /* set SR1 0,Clear block protect bits */
+ if (get_nand_flash()->enable_ecc == true) {
+ ret = mc_flash_write_sr(CMD_FLASH_SR2_ADDR, 0x11); /* set SR1 0,Clear block protect bits */
+ } else {
+ ret = mc_flash_write_sr(CMD_FLASH_SR2_ADDR, 0x01); /* set SR1 0,Clear block protect bits */
+ }
+ uint8_t status_reg;
+ mc_flash_read_sr(CMD_FLASH_SR1_ADDR, (uint8_t *)&status_reg);
+ PRINT("nandflash A0 Reg:0x%x \r\n", status_reg);
+ mc_flash_read_sr(CMD_FLASH_SR2_ADDR, (uint8_t *)&status_reg);
+ PRINT("nandflash B0 Reg:0x%x \r\n", status_reg);
+ mc_flash_read_sr(CMD_FLASH_SR3_ADDR, (uint8_t *)&status_reg);
+ PRINT("nandflash C0 Reg:0x%x \r\n", status_reg);
+ if (ret != MC_SUCCESS || status_reg != 0x2) {
+ return MC_FAILURE;
+ }
+ return MC_SUCCESS;
+}
+
+static uint16_t mc_gd5f2gm7re_check_id(void)
+{
+ g_qspi_data.instruction = CMD_FLASH_ID;
+ g_qspi_data.address_mode = MC_OSPI_ADDRESS_NONE;
+ g_qspi_data.address = 0;
+ g_qspi_data.address_size = 0;
+ g_qspi_data.dummy_cycles = MC_OSPI_CYCLES_8_BITS;
+ g_qspi_data.data_mode = MC_OSPI_DATA_1_LINE;
+ g_qspi_data.data_size = NAND_ID_DATA_SIZE;
+ return read_id(&g_qspi_data);
+}
+
+struct nand_driver_struct g_gd5f2gm7re_driver = {mc_gd5f2gm7re_init,
+ mc_gd5f2gm7re_check_id,
+ mc_gd5f2gm7re_read_page,
+ mc_flash_write_page,
+ mc_flash_erase_block,
+ mc_flash_mark_bad_block,
+ mc_flash_check_bad_block,
+ GD5F2GM7RE_BYTES_PER_PAGE,
+ GD5F2GM7RE_BYTES_PER_OOB,
+ GD5F2GM7RE_PAGES_PER_BLOCK,
+ GD5F2GM7RE_TOTAL_BLOCKS,
+ GD5F2GM7RE_CHIP_ID,
+ GD5F2GM7RE_OOB_TOTAL_LEN,
+ GD5F2GM7RE_OOB_PER_SIZE,
+ GD5F2GM7RE_OOB_PER_SIZE,
+ GD5F2GM7RE_OOB_PER_SIZE,
+ GD5F2GM7RE_OOB_PER_SIZE,
+ GD5F2GM7RE_OOB_1_OFFSET,
+ GD5F2GM7RE_OOB_2_OFFSET,
+ GD5F2GM7RE_OOB_3_OFFSET,
+ GD5F2GM7RE_OOB_4_OFFSET,
+#ifdef ENABLE_ECC
+ true
+#else
+ false
+#endif
+ };
INDEV_KEY_POWER,
INDEV_KEY_FUNC,
INDEV_KEY_FUNC2,
+ INDEV_KEY_FUNC3,
INDEV_KEY_UNKNOWN,
} InputDevKeyId;
1,
S_AGPIO_L30,//wakemodem_pin
1,
- #elif defined(BOARD_W9) || defined(BOARD_N9) || defined(BOARD_LEINIAO)
+ #elif defined(BOARD_W9) || defined(BOARD_N9)
S_AGPIO_L17, //bat_pin
1,
S_AGPIO_L23, // pwr_pin
1,
- PIN_NONE,//reset_pin
- 0,
+ S_AGPIO_L28,//reset_pin
+ 1,
S_AGPIO_L31,//ring_pin
1,
S_AGPIO_L30,//wakemodem_pin
1,
+ #elif defined(BOARD_LEINIAO)
+ S_AGPIO_L18, //bat_pin
+ 1,
+ S_AGPIO_L23, // pwr_pin
+ 1,
+ S_AGPIO_L24,//reset_pin
+ 0,
+ PIN_NONE,//ring_pin
+ 0,
+ PIN_NONE,//wakemodem_pin
+ 0,
#else
PIN_NONE, //bat_pin
1,
uint32_t uapi_cat1_reset(uint32_t pwron)
{
+ pin_t reset_pin = S_AGPIO_L28;
+#if defined(BOARD_LEINIAO)
+ reset_pin = S_AGPIO_L24;
+#endif
-#if defined(BOARD_FD230)
if( pwron == 0)
{
- uapi_gpio_set_dir(S_AGPIO_L28, GPIO_DIRECTION_OUTPUT);
- uapi_gpio_set_val(S_AGPIO_L28, GPIO_LEVEL_HIGH);
+ uapi_gpio_set_dir(reset_pin, GPIO_DIRECTION_OUTPUT);
+ uapi_gpio_set_val(reset_pin, GPIO_LEVEL_HIGH);
printf("clear reset Cat1! L28 high \r\n");
}else{
- uapi_gpio_set_dir(S_AGPIO_L28, GPIO_DIRECTION_OUTPUT);
- uapi_gpio_set_val(S_AGPIO_L28, GPIO_LEVEL_LOW);
+ uapi_gpio_set_dir(reset_pin, GPIO_DIRECTION_OUTPUT);
+ uapi_gpio_set_val(reset_pin, GPIO_LEVEL_LOW);
printf("Reset Cat1! L28 low\r\n");
}
-#endif
+
return 0;
}
uint32_t uapi_cat1_bat_on(uint32_t pwron)
{
-#if defined(BOARD_W9) || defined(BOARD_N9) || defined(BOARD_LEINIAO)
+#if defined(BOARD_W9) || defined(BOARD_N9)
pin_t bat_en_pin = S_AGPIO_L17;
-
+#elif defined(BOARD_LEINIAO)
+ pin_t bat_en_pin = S_AGPIO_L18;
if( pwron == 0)
{
uapi_gpio_set_dir(bat_en_pin, GPIO_DIRECTION_OUTPUT);
1,
S_AGPIO_L30,//wakemodem_pin
1,
- #elif defined(BOARD_W9) || defined(BOARD_N9) || defined(BOARD_LEINIAO)
+ #elif defined(BOARD_W9) || defined(BOARD_N9)
S_AGPIO_L17, //bat_pin
1,
S_AGPIO_L23, // pwr_pin
1,
- PIN_NONE,//reset_pin
- 0,
+ S_AGPIO_L28,//reset_pin
+ 1,
S_AGPIO_L31,//ring_pin
1,
S_AGPIO_L30,//wakemodem_pin
1,
+ #elif defined(BOARD_LEINIAO)
+ S_AGPIO_L18, //bat_pin
+ 1,
+ S_AGPIO_L23, // pwr_pin
+ 1,
+ S_AGPIO_L24,//reset_pin
+ 1,
+ PIN_NONE,//ring_pin
+ 0,
+ PIN_NONE,//wakemodem_pin
+ 0,
#else
PIN_NONE, //bat_pin
1,
projects / mirrors / FD230.git / commitdiff