return;
}
//训练基本信息更新
- if (request->msgId == TOPIC_EVENT_ACTIVITY_UPDATE) {
- act_result_t *cyweeInfo = new act_result_t();
- int rets = memcpy_s(cyweeInfo, sizeof(act_result_t),
- (act_result_t *)request->data, request->len);
- if (rets != EOK) {
- delete cyweeInfo; // 处理内存分配失败的情况
- cyweeInfo = NULL;
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP,
- "memcpy_s act_result_t fail ret = %d", rets);
- return;
- }
- TraingModel::GetInstance()->AnalysisData(cyweeInfo);
- // 更新其他目标完成度
- TraingModel::GetInstance()->CheckSportTag();
- delete cyweeInfo; // 释放内存
- }
- //训练额外信息
- if (request->msgId == TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE) {
- act_ext_result_t *cyweeInfo_ext = new act_ext_result_t();
- int rets = memcpy_s(cyweeInfo_ext, sizeof(act_ext_result_t),
- (act_ext_result_t *)request->data, request->len);
- if (rets != EOK) {
- delete cyweeInfo_ext; // 处理内存分配失败的情况
- cyweeInfo_ext = NULL;
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP,
- "memcpy_s act_ext_result_t fail ret = %d", rets);
- return;
- }
- TraingModel::GetInstance()->AnalysisExtraData(cyweeInfo_ext);
- delete cyweeInfo_ext; // 释放内存
- }
+ // if (request->msgId == TOPIC_EVENT_ACTIVITY_UPDATE) {
+ // act_result_t *cyweeInfo = new act_result_t();
+ // int rets = memcpy_s(cyweeInfo, sizeof(act_result_t),
+ // (act_result_t *)request->data, request->len);
+ // if (rets != EOK) {
+ // delete cyweeInfo; // 处理内存分配失败的情况
+ // cyweeInfo = NULL;
+ // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP,
+ // "memcpy_s act_result_t fail ret = %d", rets);
+ // return;
+ // }
+ // TraingModel::GetInstance()->AnalysisData(cyweeInfo);
+ // // 更新其他目标完成度
+ // TraingModel::GetInstance()->CheckSportTag();
+ // delete cyweeInfo; // 释放内存
+ // }
+ // //训练额外信息
+ // if (request->msgId == TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE) {
+ // act_ext_result_t *cyweeInfo_ext = new act_ext_result_t();
+ // int rets = memcpy_s(cyweeInfo_ext, sizeof(act_ext_result_t),
+ // (act_ext_result_t *)request->data, request->len);
+ // if (rets != EOK) {
+ // delete cyweeInfo_ext; // 处理内存分配失败的情况
+ // cyweeInfo_ext = NULL;
+ // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP,
+ // "memcpy_s act_ext_result_t fail ret = %d", rets);
+ // return;
+ // }
+ // TraingModel::GetInstance()->AnalysisExtraData(cyweeInfo_ext);
+ // delete cyweeInfo_ext; // 释放内存
+ // }
//训练心率
- if (request->msgId == TOPIC_EVENT_HEARTRATE_UPDATA) {
- uint8_t heart = *((u_int8_t *)(request->data)); // 进行类型转换
- TraingModel::GetInstance()->AnalysisHeartData(heart);
- }
+ // if (request->msgId == TOPIC_EVENT_HEARTRATE_UPDATA) {
+ // uint8_t heart = *((u_int8_t *)(request->data)); // 进行类型转换
+ // TraingModel::GetInstance()->AnalysisHeartData(heart);
+ // }
#endif
}
#ifdef __cplusplus
TOPIC_EVENT_SPORT_DISTANCE,\r
TOPIC_EVENT_LOCATION,\r
TOPIC_EVENT_HFP_HINT,\r
-// #ifdef SUPPORT_CYWEE_SERVICE\r
- TOPIC_EVENT_ACTIVITY_UPDATE,\r
- TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,\r
+#ifdef SUPPORT_CYWEE_SERVICE\r
+ // TOPIC_EVENT_ACTIVITY_UPDATE,\r
+ // TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,\r
TOPIC_EVENT_AR_ALERT_TYPE_UPDATE,\r
TOPIC_EVENT_INACTIVITY_UPDATE,\r
- TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,\r
+ // TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,\r
+#endif\r
TOPIC_EVENT_BLE_TRAINING,\r
TOPIC_EVENT_BLE_TRANSMIT,\r
TOPIC_EVENT_GOAL_SHOW_VIEW,\r
-// #endif\r
TOPIC_EVENT_CHARGE_PLUG,\r
TOPIC_EVENT_CHARGE_UNPLUG,\r
TOPIC_EVENT_LOWPOWER_ALARM,\r
{TOPIC_EVENT_STATIC_HEARTRATE_UPDATA, A_CORE_MASK, 1},
{TOPIC_EVENT_BLE_TRAINING,A_CORE_MASK,1},
{TOPIC_EVENT_BLE_TRANSMIT,A_CORE_MASK,1},
-#ifdef CYWEE_SPORT
- {TOPIC_EVENT_ACTIVITY_UPDATE, A_CORE_MASK, 1},
- {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, A_CORE_MASK, 1},
+#ifdef SUPPORT_CYWEE_SERVICE
+ // {TOPIC_EVENT_ACTIVITY_UPDATE, A_CORE_MASK, 1},
+ // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, A_CORE_MASK, 1},
{TOPIC_EVENT_AR_ALERT_TYPE_UPDATE, A_CORE_MASK, 1},
{TOPIC_EVENT_INACTIVITY_UPDATE, A_CORE_MASK, 1},
- {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, A_CORE_MASK, 1},
- {TOPIC_EVENT_GOAL_SHOW_VIEW,A_CORE_MASK,1},
-
+ // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, A_CORE_MASK, 1},
#endif
+ {TOPIC_EVENT_GOAL_SHOW_VIEW,A_CORE_MASK,1},
#ifdef SUPPORT_SPO2_NOTIFICATION
{TOPIC_EVENT_SPO2_UPDATE, A_CORE_MASK, 1},
{TOPIC_EVENT_START_HRS_MONITORING, A_CORE_MASK, 1},
#endif
{TOPIC_EVENT_ON_TIME,PRIORITY_TWO},
-#if 0
- {TOPIC_EVENT_ACTIVITY_UPDATE,PRIORITY_TWO},
- {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,PRIORITY_TWO},
+#ifdef SUPPORT_CYWEE_SERVICE
+ // {TOPIC_EVENT_ACTIVITY_UPDATE,PRIORITY_TWO},
+ // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,PRIORITY_TWO},
{TOPIC_EVENT_AR_ALERT_TYPE_UPDATE,PRIORITY_TWO},
{TOPIC_EVENT_INACTIVITY_UPDATE,PRIORITY_TWO},
- {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,PRIORITY_TWO},
- {TOPIC_EVENT_GOAL_SHOW_VIEW,PRIORITY_TWO},
+ // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,PRIORITY_TWO},
#endif
+ {TOPIC_EVENT_GOAL_SHOW_VIEW,PRIORITY_TWO},
{TOPIC_EVENT_STEPDATA_UPDATE,PRIORITY_TWO},
MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_PHONE_TO_WATCH);
MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_WATCH_TO_PHONE);
MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_HINT);
- MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_UPDATE);
- MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE);
+ // MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_UPDATE);
+ // MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE);
MsgCenterSubscribeTopic(TOPIC_EVENT_AR_ALERT_TYPE_UPDATE);
MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_UPDATE);
- MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE);
+ // MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE);
MsgCenterSubscribeTopic(TOPIC_EVENT_BLE_TRAINING);
MsgCenterSubscribeTopic(TOPIC_EVENT_BLE_TRANSMIT);
MsgCenterSubscribeTopic(TOPIC_EVENT_GOAL_SHOW_VIEW);
}
-#if 0
+#ifdef SUPPORT_CYWEE_SERVICE
//每日训练数据刷新
- void MsgCenterNotifyActivityProc(const Topic topic, Request* req)
- {
- unused(topic);
- cywee_activity_result_t* c_activity_result_t = (cywee_activity_result_t *) malloc(req->len);
- if(c_activity_result_t==NULL)
- {
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure");
- return;
- }
-
- int rets = memcpy_s(c_activity_result_t, req->len, (cywee_activity_result_t*)req->data, req->len);
- if (rets != EOK)
- {
- free(c_activity_result_t);
- c_activity_result_t = NULL;
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_t failed, ret = %d", rets);
- return;
- }
- if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_NORMAL)
- {
- /*更新卡路里数据*/
- //if(c_activity_result_t->calories!=0)
- {
- set_calories_data(c_activity_result_t->calories);
- #if DIALDATASET
- uint32_t calories= OHOS::GoalModel::GetInstance().show_data_calories_refresh();
+ // void MsgCenterNotifyActivityProc(const Topic topic, Request* req)
+ // {
+ // unused(topic);
+ // cywee_activity_result_t* c_activity_result_t = (cywee_activity_result_t *) malloc(req->len);
+ // if(c_activity_result_t==NULL)
+ // {
+ // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure");
+ // return;
+ // }
+
+ // int rets = memcpy_s(c_activity_result_t, req->len, (cywee_activity_result_t*)req->data, req->len);
+ // if (rets != EOK)
+ // {
+ // free(c_activity_result_t);
+ // c_activity_result_t = NULL;
+ // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_t failed, ret = %d", rets);
+ // return;
+ // }
+ // if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_NORMAL)
+ // {
+ // /*更新卡路里数据*/
+ // //if(c_activity_result_t->calories!=0)
+ // {
+ // set_calories_data(c_activity_result_t->calories);
+ // #if DIALDATASET
+ // uint32_t calories= OHOS::GoalModel::GetInstance().show_data_calories_refresh();
- DialModelCalorie::GetInstance()->UpdateCalorie(calories);
- #endif
- }
- /*更新距离数据*/
- //if(c_activity_result_t->distance != 0)
- {
- set_distance_data(c_activity_result_t->distance);
- #if DIALDATASET
- float distance= OHOS::GoalModel::GetInstance().show_data_distance_refresh();
- DialModelDistance::GetInstance()->UpdateDistance(distance);
- #endif
- }
- }
- else if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_FREE_TRAINING && c_activity_result_t->MHR_zone >= 2)
- {
- /*更新燃脂时间数据*/
- set_fat_time_data(1);
- }
+ // DialModelCalorie::GetInstance()->UpdateCalorie(calories);
+ // #endif
+ // }
+ // /*更新距离数据*/
+ // //if(c_activity_result_t->distance != 0)
+ // {
+ // set_distance_data(c_activity_result_t->distance);
+ // #if DIALDATASET
+ // float distance= OHOS::GoalModel::GetInstance().show_data_distance_refresh();
+ // DialModelDistance::GetInstance()->UpdateDistance(distance);
+ // #endif
+ // }
+ // }
+ // else if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_FREE_TRAINING && c_activity_result_t->MHR_zone >= 2)
+ // {
+ // /*更新燃脂时间数据*/
+ // set_fat_time_data(1);
+ // }
- free(c_activity_result_t);
- c_activity_result_t = NULL;
- }
- static int train_fat_time = 0;
- void MsgCenterNotifyActivityExtraInfoProc(const Topic topic, Request* req)
- {
- unused(topic);
- cywee_activity_result_extre_info_t* c_activity_result_extre_info_t = (cywee_activity_result_extre_info_t *) malloc(req->len);
- if(c_activity_result_extre_info_t==NULL)
- {
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure");
- return;
- }
-
- int rets = memcpy_s(c_activity_result_extre_info_t, req->len, (cywee_activity_result_extre_info_t*)req->data, req->len);
- if (rets != EOK)
- {
- free(c_activity_result_extre_info_t);
- c_activity_result_extre_info_t = NULL;
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_extre_info_t failed, ret = %d", rets);
- return;
- }
-
- if(uapi_dev_runtime_get_train_status() && c_activity_result_extre_info_t->ativity_zone_high_duration)
- {
- train_fat_time = c_activity_result_extre_info_t->ativity_zone_high_duration;
- }
- /*更新燃脂时间数据*/
- else if(uapi_dev_runtime_get_train_status() == 0 && train_fat_time)
- {
- set_fat_time_data(train_fat_time);
- train_fat_time = 0;
- }
+ // free(c_activity_result_t);
+ // c_activity_result_t = NULL;
+ // }
+ // static int train_fat_time = 0;
+ // void MsgCenterNotifyActivityExtraInfoProc(const Topic topic, Request* req)
+ // {
+ // unused(topic);
+ // cywee_activity_result_extre_info_t* c_activity_result_extre_info_t = (cywee_activity_result_extre_info_t *) malloc(req->len);
+ // if(c_activity_result_extre_info_t==NULL)
+ // {
+ // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure");
+ // return;
+ // }
+
+ // int rets = memcpy_s(c_activity_result_extre_info_t, req->len, (cywee_activity_result_extre_info_t*)req->data, req->len);
+ // if (rets != EOK)
+ // {
+ // free(c_activity_result_extre_info_t);
+ // c_activity_result_extre_info_t = NULL;
+ // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_extre_info_t failed, ret = %d", rets);
+ // return;
+ // }
+
+ // if(uapi_dev_runtime_get_train_status() && c_activity_result_extre_info_t->ativity_zone_high_duration)
+ // {
+ // train_fat_time = c_activity_result_extre_info_t->ativity_zone_high_duration;
+ // }
+ // /*更新燃脂时间数据*/
+ // else if(uapi_dev_runtime_get_train_status() == 0 && train_fat_time)
+ // {
+ // set_fat_time_data(train_fat_time);
+ // train_fat_time = 0;
+ // }
+
+ // free(c_activity_result_extre_info_t);
+ // c_activity_result_extre_info_t = NULL;
+ // }
- free(c_activity_result_extre_info_t);
- c_activity_result_extre_info_t = NULL;
- }
-#endif
/*运动识别*/
void MsgCenterNotifyArAlertProc(const Topic topic, Request* req)
{
void MsgCenterNotifyInactivityProc(const Topic topic, Request *req)
{
WEARABLE_LOGI(WEARABLE_LOG_MODULE_APP, "MsgCenterNotifyInactivityProc !");
-#ifdef SUPPORT_CYWEE_SERVICE
inact_result_t *cywee_Inactivity_Info = (inact_result_t *)malloc(req->len);
if (!cywee_Inactivity_Info)
{
free(cywee_Inactivity_Info);
cywee_Inactivity_Info = NULL;
-#endif
}
+#endif
+
//查找手表通知
void MsgCenterNotifyFindWatchProc(const Topic topic, Request* req)
{
{TOPIC_EVENT_HFP_PHONE_TO_WATCH, MsgCenterNotifyHfpWatchProc},
{TOPIC_EVENT_HFP_HINT, MsgCenterNotifyHfpWatchHintProc},
-#if 0
- {TOPIC_EVENT_ACTIVITY_UPDATE, MsgCenterNotifyActivityProc},
- {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, MsgCenterNotifyActivityExtraInfoProc},
+#ifdef SUPPORT_CYWEE_SERVICE
+ // {TOPIC_EVENT_ACTIVITY_UPDATE, MsgCenterNotifyActivityProc},
+ // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, MsgCenterNotifyActivityExtraInfoProc},
{TOPIC_EVENT_AR_ALERT_TYPE_UPDATE, MsgCenterNotifyArAlertProc},
{TOPIC_EVENT_INACTIVITY_UPDATE, MsgCenterNotifyInactivityProc},
- {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, MsgCenterNotifyInactivityAccumulateTimeProc},
- {TOPIC_EVENT_GOAL_SHOW_VIEW, MsgCenterNotifygoalnotificationviewProc},
+ // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, MsgCenterNotifyInactivityAccumulateTimeProc},
#endif
+ // {TOPIC_EVENT_GOAL_SHOW_VIEW, MsgCenterNotifygoalnotificationviewProc},//编译不过
{TOPIC_EVENT_BLE_TRANSMIT, MsgCenterNotifybleTransmit},
{TOPIC_EVENT_CHARGE_PLUG, MsgCenterNotifyChargePlugProc},
return;
}
//训练基本信息更新
- if (request->msgId == TOPIC_EVENT_ACTIVITY_UPDATE) {
- act_result_t *cyweeInfo = new act_result_t();
- int rets = memcpy_s(cyweeInfo, sizeof(act_result_t),
- (act_result_t *)request->data, request->len);
- if (rets != EOK) {
- delete cyweeInfo; // 处理内存分配失败的情况
- cyweeInfo = NULL;
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP,
- "memcpy_s act_result_t fail ret = %d", rets);
- return;
- }
- TraingModel::GetInstance()->AnalysisData(cyweeInfo);
- // 更新其他目标完成度
- TraingModel::GetInstance()->CheckSportTag();
- delete cyweeInfo; // 释放内存
- }
- //训练额外信息
- if (request->msgId == TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE) {
- act_ext_result_t *cyweeInfo_ext = new act_ext_result_t();
- int rets = memcpy_s(cyweeInfo_ext, sizeof(act_ext_result_t),
- (act_ext_result_t *)request->data, request->len);
- if (rets != EOK) {
- delete cyweeInfo_ext; // 处理内存分配失败的情况
- cyweeInfo_ext = NULL;
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP,
- "memcpy_s act_ext_result_t fail ret = %d", rets);
- return;
- }
- TraingModel::GetInstance()->AnalysisExtraData(cyweeInfo_ext);
- delete cyweeInfo_ext; // 释放内存
- }
- //训练心率
- if (request->msgId == TOPIC_EVENT_HEARTRATE_UPDATA) {
- uint8_t heart = *((u_int8_t *)(request->data)); // 进行类型转换
- TraingModel::GetInstance()->AnalysisHeartData(heart);
- }
+ // if (request->msgId == TOPIC_EVENT_ACTIVITY_UPDATE) {
+ // act_result_t *cyweeInfo = new act_result_t();
+ // int rets = memcpy_s(cyweeInfo, sizeof(act_result_t),
+ // (act_result_t *)request->data, request->len);
+ // if (rets != EOK) {
+ // delete cyweeInfo; // 处理内存分配失败的情况
+ // cyweeInfo = NULL;
+ // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP,
+ // "memcpy_s act_result_t fail ret = %d", rets);
+ // return;
+ // }
+ // TraingModel::GetInstance()->AnalysisData(cyweeInfo);
+ // // 更新其他目标完成度
+ // TraingModel::GetInstance()->CheckSportTag();
+ // delete cyweeInfo; // 释放内存
+ // }
+ // //训练额外信息
+ // if (request->msgId == TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE) {
+ // act_ext_result_t *cyweeInfo_ext = new act_ext_result_t();
+ // int rets = memcpy_s(cyweeInfo_ext, sizeof(act_ext_result_t),
+ // (act_ext_result_t *)request->data, request->len);
+ // if (rets != EOK) {
+ // delete cyweeInfo_ext; // 处理内存分配失败的情况
+ // cyweeInfo_ext = NULL;
+ // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP,
+ // "memcpy_s act_ext_result_t fail ret = %d", rets);
+ // return;
+ // }
+ // TraingModel::GetInstance()->AnalysisExtraData(cyweeInfo_ext);
+ // delete cyweeInfo_ext; // 释放内存
+ // }
+ // //训练心率
+ // if (request->msgId == TOPIC_EVENT_HEARTRATE_UPDATA) {
+ // uint8_t heart = *((u_int8_t *)(request->data)); // 进行类型转换
+ // TraingModel::GetInstance()->AnalysisHeartData(heart);
+ // }
#endif
}
#ifdef __cplusplus
TOPIC_EVENT_SPORT_DISTANCE,\r
TOPIC_EVENT_LOCATION,\r
TOPIC_EVENT_HFP_HINT,\r
-// #ifdef SUPPORT_CYWEE_SERVICE\r
- TOPIC_EVENT_ACTIVITY_UPDATE,\r
- TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,\r
+#ifdef SUPPORT_CYWEE_SERVICE\r
+ // TOPIC_EVENT_ACTIVITY_UPDATE,\r
+ // TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,\r
TOPIC_EVENT_AR_ALERT_TYPE_UPDATE,\r
TOPIC_EVENT_INACTIVITY_UPDATE,\r
- TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,\r
+ // TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,\r
+#endif\r
TOPIC_EVENT_BLE_TRAINING,\r
TOPIC_EVENT_BLE_TRANSMIT,\r
TOPIC_EVENT_GOAL_SHOW_VIEW,\r
-// #endif\r
TOPIC_EVENT_CHARGE_PLUG,\r
TOPIC_EVENT_CHARGE_UNPLUG,\r
TOPIC_EVENT_LOWPOWER_ALARM,\r
{TOPIC_EVENT_STATIC_HEARTRATE_UPDATA, A_CORE_MASK, 1},
{TOPIC_EVENT_BLE_TRANSMIT,A_CORE_MASK,1},
{TOPIC_EVENT_BLE_TRAINING,A_CORE_MASK,1},
-#ifdef CYWEE_SPORT
- {TOPIC_EVENT_ACTIVITY_UPDATE, A_CORE_MASK, 1},
- {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, A_CORE_MASK, 1},
+#ifdef SUPPORT_CYWEE_SERVICE
+ // {TOPIC_EVENT_ACTIVITY_UPDATE, A_CORE_MASK, 1},
+ // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, A_CORE_MASK, 1},
{TOPIC_EVENT_AR_ALERT_TYPE_UPDATE, A_CORE_MASK, 1},
{TOPIC_EVENT_INACTIVITY_UPDATE, A_CORE_MASK, 1},
- {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, A_CORE_MASK, 1},
- {TOPIC_EVENT_GOAL_SHOW_VIEW,A_CORE_MASK,1},
+ // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, A_CORE_MASK, 1},
#endif
+ {TOPIC_EVENT_GOAL_SHOW_VIEW,A_CORE_MASK,1},
#ifdef SUPPORT_SPO2_NOTIFICATION
{TOPIC_EVENT_SPO2_UPDATE, A_CORE_MASK, 1},
{TOPIC_EVENT_START_HRS_MONITORING, A_CORE_MASK, 1},
#endif
{TOPIC_EVENT_ON_TIME,PRIORITY_TWO},
-#if 0
- {TOPIC_EVENT_ACTIVITY_UPDATE,PRIORITY_TWO},
- {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,PRIORITY_TWO},
+#ifdef SUPPORT_CYWEE_SERVICE
+ // {TOPIC_EVENT_ACTIVITY_UPDATE,PRIORITY_TWO},
+ // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,PRIORITY_TWO},
{TOPIC_EVENT_AR_ALERT_TYPE_UPDATE,PRIORITY_TWO},
- {TOPIC_EVENT_STEPDATA_UPDATE,PRIORITY_TWO},
+ // {TOPIC_EVENT_STEPDATA_UPDATE,PRIORITY_TWO},
{TOPIC_EVENT_INACTIVITY_UPDATE,PRIORITY_TWO},
- {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,PRIORITY_TWO},
- {TOPIC_EVENT_GOAL_SHOW_VIEW,PRIORITY_TWO},
-#endif
+ // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,PRIORITY_TWO}
+#endif
+ {TOPIC_EVENT_GOAL_SHOW_VIEW,PRIORITY_TWO},
{TOPIC_EVENT_BLE_TRAINING,PRIORITY_TWO},
{TOPIC_EVENT_BLE_TRANSMIT,PRIORITY_ONE},
MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_PHONE_TO_WATCH);
MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_WATCH_TO_PHONE);
MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_HINT);
- MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_UPDATE);
- MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE);
+ // MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_UPDATE);
+ // MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE);
MsgCenterSubscribeTopic(TOPIC_EVENT_AR_ALERT_TYPE_UPDATE);
MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_UPDATE);
- MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE);
+ // MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE);
MsgCenterSubscribeTopic(TOPIC_EVENT_BLE_TRAINING);
MsgCenterSubscribeTopic(TOPIC_EVENT_BLE_TRANSMIT);
MsgCenterSubscribeTopic(TOPIC_EVENT_GOAL_SHOW_VIEW);
}
- //每日训练数据刷新
- void MsgCenterNotifyActivityProc(const Topic topic, Request* req)
- {
- unused(topic);
- cywee_activity_result_t* c_activity_result_t = (cywee_activity_result_t *) malloc(req->len);
- if(c_activity_result_t==NULL)
- {
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure");
- return;
- }
- int rets = memcpy_s(c_activity_result_t, req->len, (cywee_activity_result_t*)req->data, req->len);
- if (rets != EOK)
- {
- free(c_activity_result_t);
- c_activity_result_t = NULL;
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_t failed, ret = %d", rets);
- return;
- }
- if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_NORMAL)
- {
- /*更新卡路里数据*/
- //if(c_activity_result_t->calories!=0)
- {
- set_calories_data(c_activity_result_t->calories);
- #if DIALDATASET
- uint32_t calories= OHOS::GoalModel::GetInstance().show_data_calories_refresh();
+#endif
+
+#ifdef SUPPORT_CYWEE_SERVICE
+
+// //每日训练数据刷新
+// void MsgCenterNotifyActivityProc(const Topic topic, Request* req)
+// {
+// unused(topic);
+// cywee_activity_result_t* c_activity_result_t = (cywee_activity_result_t *) malloc(req->len);
+// if(c_activity_result_t==NULL)
+// {
+// WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure");
+// return;
+// }
+
+// int rets = memcpy_s(c_activity_result_t, req->len, (cywee_activity_result_t*)req->data, req->len);
+// if (rets != EOK)
+// {
+// free(c_activity_result_t);
+// c_activity_result_t = NULL;
+// WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_t failed, ret = %d", rets);
+// return;
+// }
+// if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_NORMAL)
+// {
+// /*更新卡路里数据*/
+// //if(c_activity_result_t->calories!=0)
+// {
+// set_calories_data(c_activity_result_t->calories);
+// #if DIALDATASET
+// uint32_t calories= OHOS::GoalModel::GetInstance().show_data_calories_refresh();
- DialModelCalorie::GetInstance()->UpdateCalorie(calories);
- #endif
- }
- /*更新距离数据*/
- //if(c_activity_result_t->distance != 0)
- {
- set_distance_data(c_activity_result_t->distance);
- #if DIALDATASET
- float distance= OHOS::GoalModel::GetInstance().show_data_distance_refresh();
- DialModelDistance::GetInstance()->UpdateDistance(distance);
- #endif
- }
- }
- else if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_FREE_TRAINING && c_activity_result_t->MHR_zone >= 2)
- {
- /*更新燃脂时间数据*/
- set_fat_time_data(1);
- }
+// DialModelCalorie::GetInstance()->UpdateCalorie(calories);
+// #endif
+// }
+// /*更新距离数据*/
+// //if(c_activity_result_t->distance != 0)
+// {
+// set_distance_data(c_activity_result_t->distance);
+// #if DIALDATASET
+// float distance= OHOS::GoalModel::GetInstance().show_data_distance_refresh();
+// DialModelDistance::GetInstance()->UpdateDistance(distance);
+// #endif
+// }
+// }
+// else if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_FREE_TRAINING && c_activity_result_t->MHR_zone >= 2)
+// {
+// /*更新燃脂时间数据*/
+// set_fat_time_data(1);
+// }
- free(c_activity_result_t);
- c_activity_result_t = NULL;
- }
- static int train_fat_time = 0;
- void MsgCenterNotifyActivityExtraInfoProc(const Topic topic, Request* req)
- {
- unused(topic);
- cywee_activity_result_extre_info_t* c_activity_result_extre_info_t = (cywee_activity_result_extre_info_t *) malloc(req->len);
- if(c_activity_result_extre_info_t==NULL)
- {
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure");
- return;
- }
-
- int rets = memcpy_s(c_activity_result_extre_info_t, req->len, (cywee_activity_result_extre_info_t*)req->data, req->len);
- if (rets != EOK)
- {
- free(c_activity_result_extre_info_t);
- c_activity_result_extre_info_t = NULL;
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_extre_info_t failed, ret = %d", rets);
- return;
- }
-
- if(uapi_dev_runtime_get_train_status() && c_activity_result_extre_info_t->ativity_zone_high_duration)
- {
- train_fat_time = c_activity_result_extre_info_t->ativity_zone_high_duration;
- }
- /*更新燃脂时间数据*/
- else if(uapi_dev_runtime_get_train_status() == 0 && train_fat_time)
- {
- set_fat_time_data(train_fat_time);
- train_fat_time = 0;
- }
+// free(c_activity_result_t);
+// c_activity_result_t = NULL;
+// }
+// static int train_fat_time = 0;
+// void MsgCenterNotifyActivityExtraInfoProc(const Topic topic, Request* req)
+// {
+// unused(topic);
+// cywee_activity_result_extre_info_t* c_activity_result_extre_info_t = (cywee_activity_result_extre_info_t *) malloc(req->len);
+// if(c_activity_result_extre_info_t==NULL)
+// {
+// WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure");
+// return;
+// }
+
+// int rets = memcpy_s(c_activity_result_extre_info_t, req->len, (cywee_activity_result_extre_info_t*)req->data, req->len);
+// if (rets != EOK)
+// {
+// free(c_activity_result_extre_info_t);
+// c_activity_result_extre_info_t = NULL;
+// WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_extre_info_t failed, ret = %d", rets);
+// return;
+// }
+
+// if(uapi_dev_runtime_get_train_status() && c_activity_result_extre_info_t->ativity_zone_high_duration)
+// {
+// train_fat_time = c_activity_result_extre_info_t->ativity_zone_high_duration;
+// }
+// /*更新燃脂时间数据*/
+// else if(uapi_dev_runtime_get_train_status() == 0 && train_fat_time)
+// {
+// set_fat_time_data(train_fat_time);
+// train_fat_time = 0;
+// }
+
+// free(c_activity_result_extre_info_t);
+// c_activity_result_extre_info_t = NULL;
+// }
- free(c_activity_result_extre_info_t);
- c_activity_result_extre_info_t = NULL;
- }
-#endif
/*运动识别*/
void MsgCenterNotifyArAlertProc(const Topic topic, Request* req)
{
void MsgCenterNotifyInactivityProc(const Topic topic, Request *req)
{
WEARABLE_LOGI(WEARABLE_LOG_MODULE_APP, "MsgCenterNotifyInactivityProc !");
-#ifdef SUPPORT_CYWEE_SERVICE
inact_result_t *cywee_Inactivity_Info = (inact_result_t *)malloc(req->len);
if (!cywee_Inactivity_Info)
{
free(cywee_Inactivity_Info);
cywee_Inactivity_Info = NULL;
-#endif
}
+#endif
+
//查找手表通知
void MsgCenterNotifyFindWatchProc(const Topic topic, Request* req)
{
{TOPIC_EVENT_HFP_PHONE_TO_WATCH, MsgCenterNotifyHfpWatchProc},
{TOPIC_EVENT_HFP_HINT, MsgCenterNotifyHfpWatchHintProc},
-#if 0
- {TOPIC_EVENT_ACTIVITY_UPDATE, MsgCenterNotifyActivityProc},
- {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, MsgCenterNotifyActivityExtraInfoProc},
+#ifdef SUPPORT_CYWEE_SERVICE
+ // {TOPIC_EVENT_ACTIVITY_UPDATE, MsgCenterNotifyActivityProc},
+ // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, MsgCenterNotifyActivityExtraInfoProc},
{TOPIC_EVENT_AR_ALERT_TYPE_UPDATE, MsgCenterNotifyArAlertProc},
{TOPIC_EVENT_INACTIVITY_UPDATE, MsgCenterNotifyInactivityProc},
- {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, MsgCenterNotifyInactivityAccumulateTimeProc},
- {TOPIC_EVENT_BLE_TRAINING, MsgCenterNotifybleAPPtraining},
- {TOPIC_EVENT_GOAL_SHOW_VIEW, MsgCenterNotifygoalnotificationviewProc},
+ // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, MsgCenterNotifyInactivityAccumulateTimeProc},
#endif
+ {TOPIC_EVENT_BLE_TRAINING, MsgCenterNotifybleAPPtraining},
+ // {TOPIC_EVENT_GOAL_SHOW_VIEW, MsgCenterNotifygoalnotificationviewProc},//编译不过
+
{TOPIC_EVENT_BLE_TRANSMIT, MsgCenterNotifybleTransmit},
{TOPIC_EVENT_CHARGE_PLUG, MsgCenterNotifyChargePlugProc},
return;
}
//训练基本信息更新
- if (request->msgId == TOPIC_EVENT_ACTIVITY_UPDATE) {
- act_result_t *cyweeInfo = new act_result_t();
- int rets = memcpy_s(cyweeInfo, sizeof(act_result_t),
- (act_result_t *)request->data, request->len);
- if (rets != EOK) {
- delete cyweeInfo; // 处理内存分配失败的情况
- cyweeInfo = NULL;
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP,
- "memcpy_s act_result_t fail ret = %d", rets);
- return;
- }
- TraingModel::GetInstance()->AnalysisData(cyweeInfo);
- // 更新其他目标完成度
- TraingModel::GetInstance()->CheckSportTag();
- delete cyweeInfo; // 释放内存
- }
- //训练额外信息
- if (request->msgId == TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE) {
- act_ext_result_t *cyweeInfo_ext = new act_ext_result_t();
- int rets = memcpy_s(cyweeInfo_ext, sizeof(act_ext_result_t),
- (act_ext_result_t *)request->data, request->len);
- if (rets != EOK) {
- delete cyweeInfo_ext; // 处理内存分配失败的情况
- cyweeInfo_ext = NULL;
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP,
- "memcpy_s act_ext_result_t fail ret = %d", rets);
- return;
- }
- TraingModel::GetInstance()->AnalysisExtraData(cyweeInfo_ext);
- delete cyweeInfo_ext; // 释放内存
- }
- //训练心率
- if (request->msgId == TOPIC_EVENT_HEARTRATE_UPDATA) {
- uint8_t heart = *((u_int8_t *)(request->data)); // 进行类型转换
- TraingModel::GetInstance()->AnalysisHeartData(heart);
- }
+ // if (request->msgId == TOPIC_EVENT_ACTIVITY_UPDATE) {
+ // act_result_t *cyweeInfo = new act_result_t();
+ // int rets = memcpy_s(cyweeInfo, sizeof(act_result_t),
+ // (act_result_t *)request->data, request->len);
+ // if (rets != EOK) {
+ // delete cyweeInfo; // 处理内存分配失败的情况
+ // cyweeInfo = NULL;
+ // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP,
+ // "memcpy_s act_result_t fail ret = %d", rets);
+ // return;
+ // }
+ // TraingModel::GetInstance()->AnalysisData(cyweeInfo);
+ // // 更新其他目标完成度
+ // TraingModel::GetInstance()->CheckSportTag();
+ // delete cyweeInfo; // 释放内存
+ // }
+ // //训练额外信息
+ // if (request->msgId == TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE) {
+ // act_ext_result_t *cyweeInfo_ext = new act_ext_result_t();
+ // int rets = memcpy_s(cyweeInfo_ext, sizeof(act_ext_result_t),
+ // (act_ext_result_t *)request->data, request->len);
+ // if (rets != EOK) {
+ // delete cyweeInfo_ext; // 处理内存分配失败的情况
+ // cyweeInfo_ext = NULL;
+ // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP,
+ // "memcpy_s act_ext_result_t fail ret = %d", rets);
+ // return;
+ // }
+ // TraingModel::GetInstance()->AnalysisExtraData(cyweeInfo_ext);
+ // delete cyweeInfo_ext; // 释放内存
+ // }
+ // //训练心率
+ // if (request->msgId == TOPIC_EVENT_HEARTRATE_UPDATA) {
+ // uint8_t heart = *((u_int8_t *)(request->data)); // 进行类型转换
+ // TraingModel::GetInstance()->AnalysisHeartData(heart);
+ // }
#endif
}
#ifdef __cplusplus
TOPIC_EVENT_SPORT_DISTANCE,\r
TOPIC_EVENT_LOCATION,\r
TOPIC_EVENT_HFP_HINT,\r
-// #ifdef SUPPORT_CYWEE_SERVICE\r
- TOPIC_EVENT_ACTIVITY_UPDATE,\r
- TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,\r
+#ifdef SUPPORT_CYWEE_SERVICE\r
+ // TOPIC_EVENT_ACTIVITY_UPDATE,\r
+ // TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,\r
TOPIC_EVENT_AR_ALERT_TYPE_UPDATE,\r
TOPIC_EVENT_INACTIVITY_UPDATE,\r
- TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,\r
+ // TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,\r
+#endif\r
TOPIC_EVENT_BLE_TRAINING,\r
TOPIC_EVENT_BLE_TRANSMIT,\r
TOPIC_EVENT_GOAL_SHOW_VIEW,\r
-// #endif\r
TOPIC_EVENT_CHARGE_PLUG,\r
TOPIC_EVENT_CHARGE_UNPLUG,\r
TOPIC_EVENT_LOWPOWER_ALARM,\r
{TOPIC_EVENT_STATIC_HEARTRATE_UPDATA, A_CORE_MASK, 1},
{TOPIC_EVENT_BLE_TRAINING,A_CORE_MASK,1},
{TOPIC_EVENT_BLE_TRANSMIT,A_CORE_MASK,1},
-#ifdef CYWEE_SPORT
- {TOPIC_EVENT_ACTIVITY_UPDATE, A_CORE_MASK, 1},
- {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, A_CORE_MASK, 1},
+#ifdef SUPPORT_CYWEE_SERVICE
+ // {TOPIC_EVENT_ACTIVITY_UPDATE, A_CORE_MASK, 1},
+ // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, A_CORE_MASK, 1},
{TOPIC_EVENT_AR_ALERT_TYPE_UPDATE, A_CORE_MASK, 1},
{TOPIC_EVENT_INACTIVITY_UPDATE, A_CORE_MASK, 1},
- {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, A_CORE_MASK, 1},
- {TOPIC_EVENT_GOAL_SHOW_VIEW,A_CORE_MASK,1},
+ // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, A_CORE_MASK, 1},
#endif
+ {TOPIC_EVENT_GOAL_SHOW_VIEW,A_CORE_MASK,1},
#ifdef SUPPORT_SPO2_NOTIFICATION
{TOPIC_EVENT_SPO2_UPDATE, A_CORE_MASK, 1},
{TOPIC_EVENT_START_HRS_MONITORING, A_CORE_MASK, 1},
#endif
{TOPIC_EVENT_ON_TIME,PRIORITY_TWO},
-#if 0
- {TOPIC_EVENT_ACTIVITY_UPDATE,PRIORITY_TWO},
- {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,PRIORITY_TWO},
+#ifdef SUPPORT_CYWEE_SERVICE
+ // {TOPIC_EVENT_ACTIVITY_UPDATE,PRIORITY_TWO},
+ // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,PRIORITY_TWO},
{TOPIC_EVENT_AR_ALERT_TYPE_UPDATE,PRIORITY_TWO},
- {TOPIC_EVENT_STEPDATA_UPDATE,PRIORITY_TWO},
+ // {TOPIC_EVENT_STEPDATA_UPDATE,PRIORITY_TWO},
{TOPIC_EVENT_INACTIVITY_UPDATE,PRIORITY_TWO},
- {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,PRIORITY_TWO},
- {TOPIC_EVENT_GOAL_SHOW_VIEW,PRIORITY_TWO},
+ // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,PRIORITY_TWO},
#endif
-
+ {TOPIC_EVENT_GOAL_SHOW_VIEW,PRIORITY_TWO},
{TOPIC_EVENT_BLE_TRAINING,PRIORITY_TWO},
{TOPIC_EVENT_BLE_TRANSMIT,PRIORITY_ONE},
MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_PHONE_TO_WATCH);
MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_WATCH_TO_PHONE);
MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_HINT);
- MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_UPDATE);
- MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE);
+ // MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_UPDATE);
+ // MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE);
MsgCenterSubscribeTopic(TOPIC_EVENT_AR_ALERT_TYPE_UPDATE);
- MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_UPDATE);
- MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE);
+ // MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_UPDATE);
+ // MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE);
MsgCenterSubscribeTopic(TOPIC_EVENT_BLE_TRAINING);
MsgCenterSubscribeTopic(TOPIC_EVENT_BLE_TRANSMIT);
MsgCenterSubscribeTopic(TOPIC_EVENT_GOAL_SHOW_VIEW);
-#if 0
+#if 0 //编译不过
//每日活动
void MsgCenterNotifygoalnotificationviewProc(const Topic topic, Request* req)
{
#endif
}
+ }
+#endif
- }
- //每日训练数据刷新
- void MsgCenterNotifyActivityProc(const Topic topic, Request* req)
- {
- unused(topic);
- cywee_activity_result_t* c_activity_result_t = (cywee_activity_result_t *) malloc(req->len);
- if(c_activity_result_t==NULL)
- {
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure");
- return;
- }
+#ifdef SUPPORT_CYWEE_SERVICE
- int rets = memcpy_s(c_activity_result_t, req->len, (cywee_activity_result_t*)req->data, req->len);
- if (rets != EOK)
- {
- free(c_activity_result_t);
- c_activity_result_t = NULL;
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_t failed, ret = %d", rets);
- return;
- }
- if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_NORMAL)
- {
- /*更新卡路里数据*/
- //if(c_activity_result_t->calories!=0)
- {
- set_calories_data(c_activity_result_t->calories);
- #if DIALDATASET
- uint32_t calories= OHOS::GoalModel::GetInstance().show_data_calories_refresh();
+ // //每日训练数据刷新
+ // void MsgCenterNotifyActivityProc(const Topic topic, Request* req)
+ // {
+ // unused(topic);
+ // cywee_activity_result_t* c_activity_result_t = (cywee_activity_result_t *) malloc(req->len);
+ // if(c_activity_result_t==NULL)
+ // {
+ // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure");
+ // return;
+ // }
+
+ // int rets = memcpy_s(c_activity_result_t, req->len, (cywee_activity_result_t*)req->data, req->len);
+ // if (rets != EOK)
+ // {
+ // free(c_activity_result_t);
+ // c_activity_result_t = NULL;
+ // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_t failed, ret = %d", rets);
+ // return;
+ // }
+ // if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_NORMAL)
+ // {
+ // /*更新卡路里数据*/
+ // //if(c_activity_result_t->calories!=0)
+ // {
+ // set_calories_data(c_activity_result_t->calories);
+ // #if DIALDATASET
+ // uint32_t calories= OHOS::GoalModel::GetInstance().show_data_calories_refresh();
- DialModelCalorie::GetInstance()->UpdateCalorie(calories);
- #endif
- }
- /*更新距离数据*/
- //if(c_activity_result_t->distance != 0)
- {
- set_distance_data(c_activity_result_t->distance);
- #if DIALDATASET
- float distance= OHOS::GoalModel::GetInstance().show_data_distance_refresh();
- DialModelDistance::GetInstance()->UpdateDistance(distance);
- #endif
- }
- }
- else if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_FREE_TRAINING && c_activity_result_t->MHR_zone >= 2)
- {
- /*更新燃脂时间数据*/
- set_fat_time_data(1);
- }
+ // DialModelCalorie::GetInstance()->UpdateCalorie(calories);
+ // #endif
+ // }
+ // /*更新距离数据*/
+ // //if(c_activity_result_t->distance != 0)
+ // {
+ // set_distance_data(c_activity_result_t->distance);
+ // #if DIALDATASET
+ // float distance= OHOS::GoalModel::GetInstance().show_data_distance_refresh();
+ // DialModelDistance::GetInstance()->UpdateDistance(distance);
+ // #endif
+ // }
+ // }
+ // else if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_FREE_TRAINING && c_activity_result_t->MHR_zone >= 2)
+ // {
+ // /*更新燃脂时间数据*/
+ // set_fat_time_data(1);
+ // }
- free(c_activity_result_t);
- c_activity_result_t = NULL;
- }
- static int train_fat_time = 0;
- void MsgCenterNotifyActivityExtraInfoProc(const Topic topic, Request* req)
- {
- unused(topic);
- cywee_activity_result_extre_info_t* c_activity_result_extre_info_t = (cywee_activity_result_extre_info_t *) malloc(req->len);
- if(c_activity_result_extre_info_t==NULL)
- {
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure");
- return;
- }
-
- int rets = memcpy_s(c_activity_result_extre_info_t, req->len, (cywee_activity_result_extre_info_t*)req->data, req->len);
- if (rets != EOK)
- {
- free(c_activity_result_extre_info_t);
- c_activity_result_extre_info_t = NULL;
- WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_extre_info_t failed, ret = %d", rets);
- return;
- }
+ // free(c_activity_result_t);
+ // c_activity_result_t = NULL;
+ // }
- if(uapi_dev_runtime_get_train_status() && c_activity_result_extre_info_t->ativity_zone_high_duration)
- {
- train_fat_time = c_activity_result_extre_info_t->ativity_zone_high_duration;
- }
- /*更新燃脂时间数据*/
- else if(uapi_dev_runtime_get_train_status() == 0 && train_fat_time)
- {
- set_fat_time_data(train_fat_time);
- train_fat_time = 0;
- }
+ // static int train_fat_time = 0;
+ // void MsgCenterNotifyActivityExtraInfoProc(const Topic topic, Request* req)
+ // {
+ // unused(topic);
+ // cywee_activity_result_extre_info_t* c_activity_result_extre_info_t = (cywee_activity_result_extre_info_t *) malloc(req->len);
+ // if(c_activity_result_extre_info_t==NULL)
+ // {
+ // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure");
+ // return;
+ // }
+
+ // int rets = memcpy_s(c_activity_result_extre_info_t, req->len, (cywee_activity_result_extre_info_t*)req->data, req->len);
+ // if (rets != EOK)
+ // {
+ // free(c_activity_result_extre_info_t);
+ // c_activity_result_extre_info_t = NULL;
+ // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_extre_info_t failed, ret = %d", rets);
+ // return;
+ // }
+
+ // if(uapi_dev_runtime_get_train_status() && c_activity_result_extre_info_t->ativity_zone_high_duration)
+ // {
+ // train_fat_time = c_activity_result_extre_info_t->ativity_zone_high_duration;
+ // }
+ // /*更新燃脂时间数据*/
+ // else if(uapi_dev_runtime_get_train_status() == 0 && train_fat_time)
+ // {
+ // set_fat_time_data(train_fat_time);
+ // train_fat_time = 0;
+ // }
+
+ // free(c_activity_result_extre_info_t);
+ // c_activity_result_extre_info_t = NULL;
+ // }
- free(c_activity_result_extre_info_t);
- c_activity_result_extre_info_t = NULL;
- }
-#endif
/*运动识别*/
void MsgCenterNotifyArAlertProc(const Topic topic, Request* req)
{
void MsgCenterNotifyInactivityProc(const Topic topic, Request *req)
{
WEARABLE_LOGI(WEARABLE_LOG_MODULE_APP, "MsgCenterNotifyInactivityProc !");
-#ifdef SUPPORT_CYWEE_SERVICE
+
inact_result_t *cywee_Inactivity_Info = (inact_result_t *)malloc(req->len);
if (!cywee_Inactivity_Info)
{
free(cywee_Inactivity_Info);
cywee_Inactivity_Info = NULL;
-#endif
}
+#endif
+
//查找手表通知
void MsgCenterNotifyFindWatchProc(const Topic topic, Request* req)
{
{TOPIC_EVENT_HFP_PHONE_TO_WATCH, MsgCenterNotifyHfpWatchProc},
{TOPIC_EVENT_HFP_HINT, MsgCenterNotifyHfpWatchHintProc},
-#if 0
- {TOPIC_EVENT_ACTIVITY_UPDATE, MsgCenterNotifyActivityProc},
- {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, MsgCenterNotifyActivityExtraInfoProc},
+#ifdef SUPPORT_CYWEE_SERVICE
+ // {TOPIC_EVENT_ACTIVITY_UPDATE, MsgCenterNotifyActivityProc},
+ // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, MsgCenterNotifyActivityExtraInfoProc},
{TOPIC_EVENT_AR_ALERT_TYPE_UPDATE, MsgCenterNotifyArAlertProc},
{TOPIC_EVENT_INACTIVITY_UPDATE, MsgCenterNotifyInactivityProc},
- {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, MsgCenterNotifyInactivityAccumulateTimeProc},
- {TOPIC_EVENT_GOAL_SHOW_VIEW, MsgCenterNotifygoalnotificationviewProc},
+ // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, MsgCenterNotifyInactivityAccumulateTimeProc},
#endif
+
+ // {TOPIC_EVENT_GOAL_SHOW_VIEW, MsgCenterNotifygoalnotificationviewProc}, //编译不过
+
{TOPIC_EVENT_BLE_TRAINING, MsgCenterNotifybleAPPtraining},
{TOPIC_EVENT_BLE_TRANSMIT, MsgCenterNotifybleTransmit},
static int history_fat=0; //历史数据
static int history_fat_=0; //一小时前燃脂数据
+// 燃脂时间计算相关变量
+static uint32_t last_fat_burn_timestamp = 0; // 上次燃脂状态更新的时间戳
+static int last_mhr_zone = -1; // 上次的心率区间状态
+
+/**
+ * @brief 更新燃脂时间
+ * @param current_mhr_zone 当前心率区间 (2表示燃脂区间)
+ */
+static void update_fat_burn_time(int current_mhr_zone)
+{
+ uint32_t current_timestamp = 0;
+ uapi_get_timestampe_ss(¤t_timestamp);
+
+ // 如果上次时间戳有效且上次是燃脂状态
+ if (last_fat_burn_timestamp > 0 && last_mhr_zone == 2) {
+ // 计算时间差 (秒)
+ uint32_t time_diff = current_timestamp - last_fat_burn_timestamp;
+
+ // 防止异常时间跳跃 (超过10分钟认为异常)
+ if (time_diff > 0 && time_diff <= 600) {
+ new_fat += time_diff;
+ CWM_OS_dbgPrintf("Fat burn time updated: +%d seconds, total: %d seconds\n",
+ time_diff, new_fat);
+ }
+ }
+
+ // 更新状态
+ last_fat_burn_timestamp = current_timestamp;
+ last_mhr_zone = current_mhr_zone;
+}
+
static char chipInfo[64] = {0};
static int sedentary_interval = 1;
history_distances=0;
history_fat=0;
// new_fat = 0; //当前燃脂数据
+
+ // 重置燃脂时间计算相关状态
+ last_fat_burn_timestamp = 0;
+ last_mhr_zone = -1;
}
void cywee_reset_daily_data(void)
c_act_ext_result_t.MHR_zone = (int)sensorEVT->fData[13];
c_act_ext_result_t.distance_motion = (int)sensorEVT->fData[14];
+ // 燃脂时间计算：当MHR_zone = 2时表示燃脂状态
+ update_fat_burn_time(c_act_ext_result_t.MHR_zone);
+
// cywee_func(CYWEE_MSG_TYPE_ACTIVITY_EXTRA_INFO_UPDATE,&c_act_ext_result_t,sizeof(act_ext_result_t));
//CustomEventPublish(TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, &c_act_ext_result_t, sizeof(act_ext_result_t));
// CWM_OS_dbgPrintf("PAH:avg_step_freq[%d], avg_step_len[%f],avg_pace[%d], max_step_freq[%d], max_pace[%d]\n",
c_act_result_t.calories = (int)sensorEVT->fData[1];
c_act_result_t.duration = (int)sensorEVT->fData[5];
c_act_result_t.MHR_zone = (int)sensorEVT->fData[6];
+
+ // 燃脂时间计算：当MHR_zone = 2时表示燃脂状态
+ update_fat_burn_time(c_act_result_t.MHR_zone);
+
// c_act_result_t.hrs = hrs;
// hrs = 0; //每次上报完 清除心率值
// cywee_func(CYWEE_MSG_TYPE_ACTIVITY_UPDATE,&c_act_result_t,sizeof(act_result_t));
if("PPG_HX3695" IN_LIST DEFINES)
set(SOURCES ${SOURCES}
${CMAKE_CURRENT_SOURCE_DIR}/hx3695.c
- ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_check_touch.c
+ # ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_check_touch.c
${CMAKE_CURRENT_SOURCE_DIR}/hx3695_factory_test.c
- ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_hrs_agc.c
- ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_hrv_agc.c
- ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_spo2_agc.c
+ # ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_hrs_agc.c
+ # ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_hrv_agc.c
+ # ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_spo2_agc.c
#${CMAKE_CURRENT_SOURCE_DIR}/hx3695_hal.c
${CMAKE_CURRENT_SOURCE_DIR}/hx3695_hrs_custom.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_agc.c
+
)
set(PUBLIC_HEADER
${CMAKE_CURRENT_SOURCE_DIR}
if("PPG_HX3695" IN_LIST DEFINES)
find_library(LIB_PATH_HX3695 libhx3695.a ${CMAKE_CURRENT_SOURCE_DIR})
- target_link_libraries(${TARGET_NAME} PRIVATE -Wl,--whole-archive ${LIB_PATH_HX3695} PRIVATE -Wl,--whole-archive)
+ find_library(LIB_PATH_HX3695_HRV libHX3697_hs_20241230_103__01_hrv.a ${CMAKE_CURRENT_SOURCE_DIR})
+ find_library(LIB_PATH_HX3695_HRS libHX3697_hs_20241230_3153__01_hrs.a ${CMAKE_CURRENT_SOURCE_DIR})
+ find_library(LIB_PATH_HX3695_SPO libHX3697_hs_20240607_3333__02_spo.a ${CMAKE_CURRENT_SOURCE_DIR})
+
+ target_link_libraries(${TARGET_NAME} PRIVATE -Wl,--whole-archive
+ # ${LIB_PATH_HX3695}
+ ${LIB_PATH_HX3695_HRV}
+ ${LIB_PATH_HX3695_HRS}
+ ${LIB_PATH_HX3695_SPO}
+ PRIVATE -Wl,--whole-archive)
endif()
build_component()
#include <math.h>\r
\r
#include "tyhx_hrs_custom.h"\r
-//#include "tyhx_mems.h"\r
-\r
-#ifdef CHIP_HX3695\r
#include "hx3695.h"\r
-#ifdef HRS_ALG_LIB\r
-#include "hx3695_hrs_agc.h"\r
+#ifdef TYHX_DEMO\r
+#include "demo_ctrl.h"\r
+#include "twi_master.h"\r
+#include "SEGGER_RTT.h"\r
+#include "app_timer.h"\r
+#include "nrf_delay.h"\r
+#include "nrf_gpio.h"\r
+#include "nrf_drv_gpiote.h"\r
+#include "drv_oled.h"\r
+#include "opr_oled.h"\r
+\r
+#include "oled_iic.h"\r
+#include "word.h"\r
+#include "iic.h"\r
+#endif\r
+#include "hx3695_agc.h"\r
#include "tyhx_hrs_alg.h"\r
-#endif\r
-#ifdef SPO2_ALG_LIB\r
-#include "hx3695_spo2_agc.h"\r
-#include "tyhx_spo2_alg.h"\r
-#endif\r
-#ifdef HRV_ALG_LIB\r
-#include "hx3695_hrv_agc.h"\r
#include "tyhx_hrv_alg.h"\r
-#endif\r
-#ifdef CHECK_TOUCH_LIB\r
-#include "hx3695_check_touch.h"\r
-#endif\r
+#include "tyhx_spo2_alg.h"\r
#include "hx3695_factory_test.h"\r
-//#include "app_ble_factory_test.h"\r
\r
-// #include "ui.h"\r
-// #include "app_heart_rate.h"\r
-// #include "lv_dev.h"\r
-// #include "app_task.h"\r
\r
#ifdef SUPPORT_CYWEE_SERVICE\r
#include "cywee_hal.h"\r
\r
#include "ppg_hal.h"\r
\r
+uint8_t read_fifo_first_flg = 0;\r
+uint8_t s_ppg_state = 0;\r
+uint8_t s_cal_state = 0;\r
+uint8_t check_touch_cnt = 0;\r
+static wear_msg_code_t wear_status = MSG_NO_WEAR;\r
+static wear_msg_code_t wear_status_pre = MSG_NO_INIT;\r
+WORK_MODE_T work_mode_flag = HRS_MODE;\r
+ppg_sensor_data_t ppg_sensor_data;\r
+int16_t gsen_data_x_fifo[64];\r
+int16_t gsen_data_y_fifo[64];\r
+int16_t gsen_data_z_fifo[64];\r
\r
-FT_CUSTOM_RESULTS_t hrsresult ={0};\r
-\r
-int16_t gsen_fifo_x[64]={0};\r
-int16_t gsen_fifo_y[64]={0};\r
-int16_t gsen_fifo_z[64]={0};\r
-\r
+static uint8_t hrs_ble_falg = 0;\r
+// static int history_wear_status = -1;\r
+static uint8_t wear_result = 0;\r
+static uint8_t spo2_ret = 0;\r
+static int32_t factory_data = 0;\r
+static uint8_t hx3695_chip_id = 0;\r
#ifdef SUPPORT_CYWEE_SERVICE\r
-gsenson_t gsensordata[32];\r
+static gsenson_t gsensordata[32];\r
#endif\r
+// static uint8_t his_wear = 2;\r
+// static uint8_t wear_cnt = 0;\r
\r
-static uint8_t msg_count = 0;\r
-\r
-#ifdef SPO2_VECTOR\r
-#include "spo2_vec.h"\r
-uint32_t spo2_send_cnt = 0;\r
-uint32_t spo2_send_cnt1 = 0;\r
-int32_t red_buf_vec[8];\r
-int32_t ir_buf_vec[8];\r
-int32_t green_buf_vec[8];\r
-#endif\r
+uint8_t alg_ram[11 * 1024] __attribute__((aligned(4)));\r
\r
-#ifdef HR_VECTOR\r
-#include "hr_vec.h"\r
-uint32_t vec_send_cnt = 0;\r
-int32_t PPG_buf_vec[8];\r
-#endif\r
\r
-#ifdef HRV_TESTVEC\r
-#include "hrv_testvec.h"\r
-#endif\r
-// #include "sys_init.h"\r
-// #include "cwm_api.h"\r
+//////// spo2 para and switches\r
+const uint8_t COUNT_BLOCK_NUM = 25; // delay the block of some single good signal after a series of bad signal\r
+const uint8_t SPO2_LOW_XCORR_THRE = 30; //(64*xcorr)'s square below this threshold, means error signal\r
+const uint8_t SPO2_CALI = 1; // spo2_result cali mode\r
+const uint8_t XCORR_MODE = 1; // xcorr mode switch\r
+const uint8_t QUICK_RESULT = 1; // come out the spo2 result quickly ;0 is normal,1 is quick\r
+const uint16_t MEAN_NUM = 32; // the length of smooth-average ;the value of MEAN_NUM can be given only 256 and 512\r
+const uint8_t G_SENSOR = 0; // if =1, open the gsensor mode\r
+const uint8_t SPO2_GSEN_POW_THRE = 150; // gsen pow judge move, range:0-200;\r
+const uint32_t SPO2_BASE_LINE_INIT = 153000; // spo2 baseline init, = 103000 + ratio(a variable quantity,depends on different cases)*SPO2_SLOPE\r
+const int32_t SOP2_DEGLITCH_THRE = 100000; // remove signal glitch over this threshold\r
+const int32_t SPO2_REMOVE_JUMP_THRE = 50000; // remove signal jump over this threshold\r
+const uint32_t SPO2_SLOPE = 50000; // increase this slope, spo2 reduce more\r
+const uint16_t SPO2_LOW_CLIP_END_TIME = 1500; // low clip mode before this data_cnt, normal clip mode after this\r
+const uint16_t SPO2_LOW_CLIP_DN = 150; // spo2 reduce 0.15/s at most in low clip mode\r
+const uint16_t SPO2_NORMAL_CLIP_DN = 500; // spo2 reduce 0.5/s at most in normal clip mode\r
+const uint8_t SPO2_LOW_SNR_THRE = 40; // snr below this threshold, means error signal\r
+const uint16_t IR_AC_TOUCH_THRE = 200; // AC_min*0.3\r
+const uint16_t IR_FFT_POW_THRE = 500; // fft_pow_min\r
+const uint8_t SLOPE_PARA_MAX = 28;\r
+const uint8_t SLOPE_PARA_MIN = 3;\r
\r
-static uint8_t hrs_ble_falg = 0;\r
-#define PPG_DATA_LEN_MAX 17\r
-int32_t s_buf[256];\r
-uint32_t cnt_num = 0;\r
-uint32_t phase3_rdy_num = 0;\r
-uint8_t fifo_data_buf[768];\r
-uint8_t hrs_phase_num= 3;\r
-uint8_t spo2_phase_num= 4;\r
-uint8_t hrv_phase_num = 4;\r
-extern uint8_t data_count;\r
-extern uint8_t hr_no_living_dur;\r
-extern uint8_t spo2_no_living_dur;\r
-\r
-extern int tyhx_long_timer_tick; \r
-//spo2 agc\r
-const uint8_t hx3695_spo2_agc_red_idac = RED_AGC_OFFSET;\r
-const uint8_t hx3695_spo2_agc_ir_idac = IR_AGC_OFFSET;\r
-const uint8_t hx3695_spo2_agc_ir_idac1 = IR_AGC_OFFSET;\r
-const uint8_t hx3695_spo2_agc_ir_idac2 = IR_AGC_OFFSET;\r
-const uint8_t hx3695_spo2_agc_green_idac = GREEN_AGC_OFFSET;\r
-//hrs agc\r
-const uint8_t hx3695_hrs_agc_idac = HR_GREEN_AGC_OFFSET;\r
-const uint8_t hx3695_hrs_g1_agc_idac = HR_GREEN1_AGC_OFFSET;\r
-const uint8_t hx3695_hrs_g2_agc_idac = HR_GREEN2_AGC_OFFSET; \r
-const uint8_t hx3695_hrs_g3_agc_idac = HR_GREEN3_AGC_OFFSET;\r
-//hrv agc\r
-const uint8_t hx3695_hrv_agc_idac = HR_GREEN_AGC_OFFSET;\r
-\r
-const uint8_t green_led_max_init = 255;\r
-const uint8_t red_led_max_init = 255;\r
-const uint8_t ir_led_max_init = 255;\r
-\r
-uint8_t low_vbat_flag =0;\r
-WORK_MODE_T work_mode_flag = HRS_MODE;\r
const uint16_t static_thre_val = 150;\r
const uint8_t gsen_lv_val = 0;\r
-uint8_t read_fifo_first_flg = 0;\r
-\r
-//HRS_INFRARED_THRES\r
-const int32_t hrs_ir_unwear_thres = 10000;\r
-const int32_t hrs_ir_wear_thres = 15000;\r
-//HRV_INFRARED_THRES\r
-const int32_t hrv_ir_unwear_thres = 8000; //demo143b 25000\r
-const int32_t hrv_ir_wear_thres = 10000;\r
-//SPO2_INFRARED_THRES\r
-const int32_t spo2_ir_unwear_thres = 8000; //demo143b 25000 30000\r
-const int32_t spo2_ir_wear_thres = 10000;\r
-const uint8_t spo2_ir_wear_offset = 15;\r
-//CHECK_WEAR_MODE_THRES\r
-const int32_t check_mode_unwear_thre = 20000;\r
-const int32_t check_mode_wear_thre = 22000;\r
-\r
-\r
-uint8_t alg_ram[11 * 1024] __attribute__((aligned(4)));\r
-//uint8_t alg_ram[10] = {0};\r
-ppg_sensor_data_t ppg_s_data;\r
-\r
-static int history_wear_status = -1;\r
-static uint8_t wear_status = 0;\r
-static uint8_t spo2_result = 0;\r
-static int32_t factory_data = 0;\r
-static uint8_t hx3695_chip_id = 0;\r
\r
-// static int timeout = 0;\r
-\r
-//////// spo2 para and switches\r
-const uint8_t COUNT_BLOCK_NUM = 25; //delay the block of some single good signal after a series of bad signal\r
-const uint8_t SPO2_LOW_XCORR_THRE = 30; //(64*xcorr)'s square below this threshold, means error signal\r
-const uint8_t SPO2_CALI = 1; //spo2_result cali mode\r
-const uint8_t XCORR_MODE = 1; //xcorr mode switch\r
-const uint8_t QUICK_RESULT = 1; //come out the spo2 result quickly ;0 is normal,1 is quick\r
-const uint16_t MEAN_NUM = 32; //the length of smooth-average ;the value of MEAN_NUM can be given only 256 and 512\r
-const uint8_t G_SENSOR = 0; //if =1, open the gsensor mode\r
-const uint8_t SPO2_GSEN_POW_THRE = 150; //gsen pow judge move, range:0-200;\r
-const uint32_t SPO2_BASE_LINE_INIT = 138000; //spo2 baseline init, = 103000 + ratio(a variable quantity,depends on different cases)*SPO2_SLOPE\r
-const int32_t SOP2_DEGLITCH_THRE = 100000; //remove signal glitch over this threshold\r
-const int32_t SPO2_REMOVE_JUMP_THRE = 50000; //remove signal jump over this threshold\r
-const uint32_t SPO2_SLOPE = 50000; //increase this slope, spo2 reduce more\r
-const uint16_t SPO2_LOW_CLIP_END_TIME = 1500; //low clip mode before this data_cnt, normal clip mode after this\r
-const uint16_t SPO2_LOW_CLIP_DN = 150; //spo2 reduce 0.15/s at most in low clip mode\r
-const uint16_t SPO2_NORMAL_CLIP_DN = 500; //spo2 reduce 0.5/s at most in normal clip mode\r
-const uint8_t SPO2_LOW_SNR_THRE = 40; //snr below this threshold, means error signal\r
-const uint16_t IR_AC_TOUCH_THRE = 200; //AC_min*0.3\r
-const uint16_t IR_FFT_POW_THRE = 500; //fft_pow_min\r
-const uint8_t SLOPE_PARA_MAX = 28;\r
-const uint8_t SLOPE_PARA_MIN = 3;\r
-\r
-#ifdef SPO2_DATA_CALI\r
-static int32_t red_data_fifo[4] = {0};\r
-static int32_t ir_data_fifo[4] = {0};\r
-static int32_t red_dc_temp = 0;\r
-static int32_t ir_dc_temp = 0;\r
-static int32_t red_data_pre = 0;\r
-static int32_t ir_data_pre = 0;\r
-static int32_t red_jump_delta = 0;\r
-static int32_t ir_jump_delta = 0;\r
-static int32_t cali_data_cnt = 0;\r
-#endif\r
-\r
-// us 延时函数， 客户需填写\r
+void hx3695_spi_bus_init(void)\r
+{\r
+ \r
+}\r
+// us ��ʱ������ �ͻ�����д\r
void hx3695_delay_us(uint32_t us)\r
{\r
tyhx_delay_us(us);\r
\r
void hx3695_delay_ms(uint32_t ms)\r
{\r
- tyhx_delay_ms(ms);\r
+ tyhx_delay_ms(ms);\r
}\r
\r
// i2c 写函数， 客户需填写, 地址0x44(7bit)\r
bool hx3695_write_reg(uint8_t addr, uint8_t data)\r
{\r
- custom_i2c_write_reg(HX3695_I2C_DEV_8ADDR,addr,1,&data,1,I2C_BUS_2);\r
+ custom_i2c_write_reg(HX3695_I2C_DEV_8ADDR,addr,1,&data,1,I2C_BUS_2);\r
return true;\r
}\r
\r
-// i2c 读函数， 客户需填写\r
uint8_t hx3695_read_reg(uint8_t addr)\r
{\r
uint8_t data_buf = 0;\r
}\r
\r
// i2c 连读函数， 客户需填写\r
-bool hx3695_brust_read_reg(uint8_t addr, uint8_t *buf, uint16_t length)\r
+void hx3695_brust_read_reg(uint8_t addr, uint8_t *buf, uint16_t length)\r
{\r
//TYHX_LOG("brust read\r\n");\r
custom_i2c_read_regs(HX3695_I2C_DEV_8ADDR,addr,1,buf,length,I2C_BUS_2);\r
- return true;\r
-}\r
-\r
-void Efuse_Mode_Check(void)\r
-{\r
-#if 1//def TEST_RELEASE_USE\r
- PRINT("@@@@@@@@@ Efuse_Mode_Check\r\n");\r
- uint8_t REG_50_E, REG_51_E, REG_52_E, REG_53_E;\r
- \r
- hx3695_write_reg(0x5c, 0x08) ; //0x5c\r
- hx3695_write_reg(0x5d, 0x02) ; //0x5d\r
- hx3695_delay_us(10);\r
- \r
- hx3695_write_reg(0x5a,0x10); //0x5A\r
- \r
- hx3695_write_reg(0x5b,0x04);\r
- hx3695_write_reg(0x5b,0x00);\r
- hx3695_delay_us(10);\r
- hx3695_write_reg(0x5b,0x44);\r
- hx3695_write_reg(0x5b,0x40);\r
- \r
- REG_50_E = hx3695_read_reg(0x50);\r
- REG_51_E = hx3695_read_reg(0x51);\r
- REG_52_E = hx3695_read_reg(0x52);\r
- REG_53_E = hx3695_read_reg(0x53);\r
- \r
- hx3695_write_reg(0x5a,0x20); //0x5A\r
- hx3695_write_reg(0x50,REG_50_E);\r
- hx3695_write_reg(0x51,REG_51_E);\r
- hx3695_write_reg(0x52,REG_52_E);\r
- hx3695_write_reg(0x53,REG_53_E);\r
-\r
- TYHX_LOG("EFUSE MC2: 0x50=0x%2x 0x51= 0x%2x 0x52= 0x%2x 0x53= 0x%2x \r\n",REG_50_E,REG_51_E,REG_52_E,REG_53_E);\r
- \r
- hx3695_write_reg(0x5a,0x00); \r
- hx3695_write_reg(0x5c,0x00); //0x5c\r
- hx3695_write_reg(0x5d,0x00); //0x5d\r
-#endif \r
-}\r
-bool Efuse_judge(void)\r
-{\r
- uint8_t REG_50, REG_51, REG_52, REG_53,REG_50_A;\r
- \r
- REG_50 = hx3695_read_reg(0x50); //32k\r
- REG_51 = hx3695_read_reg(0x51);\r
- REG_52 = hx3695_read_reg(0x52); \r
- REG_53 = hx3695_read_reg(0x53); //bit<7> efuse trim flg ==1\r
- \r
-// hx3695_write_reg(0x5d,0x00); \r
-// hx3695_write_reg(0x5a,0x20); \r
-// REG_50_A=REG_50+1;\r
-// hx3695_write_reg(0x50,REG_50_A); // REG_50+1 \r
-// TYHX_LOG("EFUSE 0x50=%x \r\n",REG_50_A);\r
-// hx3695_write_reg(0x50,REG_51); \r
-// hx3695_write_reg(0x50,REG_52); \r
-// hx3695_write_reg(0x50,REG_53); \r
- \r
- //TYHX_LOG("EFUSE MC1 :0x50=0x%2x 0x51= 0x%2x 0x52= 0x%2x 0x53= 0x%2x \r\n",REG_50,REG_51,REG_52,REG_53);\r
- if ((REG_50 == 0x40) && (REG_51 ==0x50) && (REG_52 ==0x10) && (REG_53 ==0x22))\r
- { \r
- Efuse_Mode_Check(); \r
- //TYHX_LOG("this chip is before MC \r\n"); \r
- }\r
- else\r
- {\r
- //TYHX_LOG("EFUSE MC3 :0x50=0x%2x 0x51= 0x%2x 0x52= 0x%2x 0x53= 0x%2x \r\n",REG_50,REG_51,REG_52,REG_53);\r
- //TYHX_LOG("this chip is after MC \r\n");\r
- }\r
- return true;\r
}\r
\r
uint32_t hx3695_wear_mode_timers_start(void)\r
}\r
\r
\r
-/* 完成读取PPG数据定时器接口， 循环调用， 默认320ms\r
-void heart_rate_meas_timeout_handler(void * p_context)\r
-*/\r
+/* ��ɶ�ȡPPG���ݶ�ʱ���ӿڣ� ѭ�����ã� Ĭ��320ms*/\r
+// void heart_rate_meas_timeout_handler(void *p_context)\r
void hx3695_320ms_timer_cfg(bool en)\r
{\r
if(en)\r
}\r
\r
\r
-#if defined(INT_MODE)\r
-/* 如采用中断模式， 如完成中断开启和关闭接口\r
-void hx3695_ppg_Int_handle(void)\r
-*/\r
void hx3695_gpioint_cfg(bool en)\r
{\r
- if(en)\r
- {\r
- hx3695_gpioint_enable();\r
- }\r
- else\r
- {\r
- hx3695_gpioint_disable();\r
- }\r
+ // if (en)\r
+ // {\r
+ // hx3695_gpioint_enable();\r
+ // }\r
+ // else\r
+ // {\r
+ // hx3695_gpioint_disable();\r
+ // }\r
+}\r
+\r
+void Efuse_Mode_Check(void)\r
+{\r
+ uint8_t REG_50_E, REG_51_E, REG_52_E, REG_53_E;\r
+\r
+ hx3695_write_reg(0x5c, 0x08);\r
+ hx3695_write_reg(0x5d, 0x02);\r
+ hx3695_delay_us(10);\r
+\r
+ hx3695_write_reg(0x5a,0x10);\r
+\r
+ hx3695_write_reg(0x5b,0x04);\r
+ hx3695_write_reg(0x5b,0x00);\r
+ hx3695_delay_us(10);\r
+ hx3695_write_reg(0x5b,0x44);\r
+ hx3695_write_reg(0x5b,0x40);\r
+\r
+ REG_50_E = hx3695_read_reg(0x50);\r
+ REG_51_E = hx3695_read_reg(0x51);\r
+ REG_52_E = hx3695_read_reg(0x52);\r
+ REG_53_E = hx3695_read_reg(0x53);\r
+\r
+ hx3695_write_reg(0x5a,0x20);\r
+ hx3695_write_reg(0x50,REG_50_E);\r
+ hx3695_write_reg(0x51,REG_51_E);\r
+ hx3695_write_reg(0x52,REG_52_E);\r
+ hx3695_write_reg(0x53,REG_53_E);\r
+\r
+// DEBUG_PRINTF("EFUSE MC2: 0x50=0x%2x 0x51= 0x%2x 0x52= 0x%2x 0x53= 0x%2x \r\n",REG_50_E,REG_51_E,REG_52_E,REG_53_E);\r
+\r
+ hx3695_write_reg(0x5a,0x00);\r
+ hx3695_write_reg(0x5c,0x00); //0x5c\r
+ hx3695_write_reg(0x5d,0x00); //0x5d\r
+\r
}\r
-#endif\r
\r
uint8_t hx3695_chip_check(void)\r
{\r
return chip_id;\r
}\r
\r
-void hx3695_get_id(uint8_t *ppg_id)\r
-{\r
- *ppg_id = hx3695_chip_id;\r
-}\r
-\r
uint8_t hx3695_read_fifo_size(void)\r
{\r
- uint8_t data_len_h,data_len_l;\r
- uint16_t fifo_data_length;\r
- data_len_h = hx3695_read_reg(0x21);\r
- data_len_l = hx3695_read_reg(0x20);\r
- fifo_data_length = (((data_len_h&0x01)<<8)|data_len_l);\r
-\r
+ uint8_t data_len_h, data_len_l;\r
+ uint16_t fifo_data_length;\r
+ data_len_h = hx3695_read_reg(0x21);\r
+ data_len_l = hx3695_read_reg(0x20);\r
+ fifo_data_length = (((data_len_h & 0x01) << 8) | data_len_l);\r
return fifo_data_length;\r
}\r
\r
+uint16_t hx3695_led_data_analysis(ppg_sensor_data_t *ppg_sensor_dat, uint16_t fifo_read_length, uint8_t sig)\r
+{\r
+ int32_t data_temp = 0;\r
+ uint8_t fifo_data_flag = 0;\r
+ uint16_t count = 0;\r
+ uint32_t ii = 0;\r
+ for(ii=0; ii<fifo_read_length; ii++)\r
+ {\r
+ fifo_data_flag = ppg_sensor_dat->s_buf[ii*3+2]>>5;\r
+ count = ii/ppg_sensor_dat->led_activated;\r
+ if(sig==0)\r
+ {\r
+ data_temp = (int32_t)(ppg_sensor_dat->s_buf[ii*3]|(ppg_sensor_dat->s_buf[ii*3+1]<<8)|((ppg_sensor_dat->s_buf[ii*3+2]&0x1f)<<16));\r
+ }\r
+ else\r
+ {\r
+ if((ppg_sensor_dat->s_buf[ii*3+2]&0x10)!=0)\r
+ {\r
+ data_temp = (int32_t)(ppg_sensor_dat->s_buf[ii*3]|(ppg_sensor_dat->s_buf[ii*3+1]<<8)|((ppg_sensor_dat->s_buf[ii*3+2]&0x0f)<<16))-1048576;\r
+ }\r
+ else\r
+ {\r
+ data_temp = (int32_t)(ppg_sensor_dat->s_buf[ii*3]|(ppg_sensor_dat->s_buf[ii*3+1]<<8)|((ppg_sensor_dat->s_buf[ii*3+2]&0x1f)<<16));\r
+ }\r
+ }\r
+ //DEBUG_PRINTF("fifo_data: %d %d\r\n", ii, data_temp);\r
+ ppg_sensor_dat->led_data[fifo_data_flag].data_val[count] = data_temp;\r
+ }\r
+ for(ii=0;ii<4;ii++)\r
+ {\r
+ if(ppg_sensor_dat->led_data[ii].led_state == Activated)\r
+ {\r
+ ppg_sensor_dat->led_data[ii].data_count = count+1;\r
+ }\r
+ }\r
+ return count+1;\r
+}\r
\r
-uint16_t hx3695_read_fifo_data(int32_t *buf, uint8_t phase_num, uint8_t sig)\r
+void hx3695_get_led_para(ppg_sensor_data_t *ppg_sensor_dat)\r
{\r
- uint8_t data_flg_start = 0;\r
- uint8_t data_flg_end = 0;\r
-// int32_t data;\r
- uint8_t databuf[3];\r
- uint32_t ii=0;\r
- uint16_t data_len_h = 0;\r
- uint16_t data_len_l = 0;\r
- uint16_t fifo_data_length = 0;\r
- uint16_t fifo_read_length = 0;\r
- uint16_t fifo_read_bytes = 0;\r
- uint16_t fifo_out_length = 0;\r
- uint16_t fifo_out_count = 0;\r
- \r
- data_len_h = hx3695_read_reg(0x21);\r
- data_len_l = hx3695_read_reg(0x20);\r
- fifo_data_length = (((data_len_h&0x01)<<8)|data_len_l);\r
-// SEGGER_RTT_printf(0,"fifo_data_length = %d\r\n", fifo_data_length); \r
- if(fifo_data_length<2*phase_num)\r
- {\r
- return 0;\r
- }\r
- fifo_read_length = ((fifo_data_length-phase_num)/phase_num)*phase_num;\r
-// SEGGER_RTT_printf(0,"fifo_data_length_change = %d\r\n", fifo_read_length);\r
- fifo_read_bytes = fifo_read_length*3;\r
- if(read_fifo_first_flg == 1)\r
- {\r
- hx3695_brust_read_reg(0x22, databuf, 3); \r
- read_fifo_first_flg = 0;\r
- } \r
- hx3695_brust_read_reg(0x22, fifo_data_buf, fifo_read_bytes); \r
- // for(ii=0; ii<fifo_read_bytes; ii++)\r
- // {\r
- // PRINT("%d/%d, %d\r\n", ii+1,fifo_read_bytes,fifo_data_buf[ii]); \r
- // }\r
- for(ii=0; ii<fifo_read_length; ii++)\r
- {\r
- if(sig==0)\r
- {\r
- buf[ii] = (int32_t)(fifo_data_buf[ii*3]|(fifo_data_buf[ii*3+1]<<8)|((fifo_data_buf[ii*3+2]&0x1f)<<16));\r
- }\r
- else\r
- {\r
- if((fifo_data_buf[ii*3+2]&0x10)!=0)\r
- {\r
- buf[ii] = (int32_t)(fifo_data_buf[ii*3]|(fifo_data_buf[ii*3+1]<<8)|((fifo_data_buf[ii*3+2]&0x0f)<<16))-1048576;\r
- }\r
- else\r
- {\r
- buf[ii] = (int32_t)(fifo_data_buf[ii*3]|(fifo_data_buf[ii*3+1]<<8)|((fifo_data_buf[ii*3+2]&0x1f)<<16));\r
- }\r
- }\r
- SEGGER_RTT_printf(0,"fifo_length = %d/%d, %d %d\r\n", ii+1,fifo_read_length,buf[ii],fifo_data_buf[ii*3+2]>>5); \r
- }\r
- data_flg_start = fifo_data_buf[2]>>5;\r
- data_flg_end = fifo_data_buf[fifo_read_bytes-1]>>5;\r
- fifo_out_length = fifo_read_length;\r
- if(data_flg_start>0)\r
- {\r
- fifo_out_length = fifo_read_length-phase_num + data_flg_start;\r
- for(ii=0; ii<fifo_out_length; ii++)\r
- {\r
- buf[ii] = buf[ii+ phase_num - data_flg_start];\r
- }\r
- for(ii= fifo_out_length; ii< fifo_read_length; ii++)\r
- {\r
- buf[ii] = 0;\r
- }\r
- }\r
- if(data_flg_end < phase_num -1)\r
- {\r
- for(ii=fifo_out_length; ii<fifo_out_length+phase_num-data_flg_end-1; ii++)\r
- hx3695_brust_read_reg(0x22, databuf, 3);\r
- buf[ii] = (int32_t)(databuf[0]|(databuf[1]<<8)|((databuf[2]&0x1f)<<16)); \r
- } \r
- for(ii=0; ii<fifo_out_length; ii++)\r
+ uint8_t led_index = 0;\r
+ for(led_index=0;led_index<4;led_index++)\r
+ {\r
+ if(ppg_sensor_dat->led_data[led_index].led_state == Activated)\r
{\r
-// SEGGER_RTT_printf(0,"fifo_buf %d/%d, %d\r\n", ii+1,fifo_out_length,buf[ii]); \r
+ hx3695_write_reg(0X43, led_index*2+1);\r
+ ppg_sensor_dat->led_data[led_index].led_current = hx3695_read_reg(0x45);\r
+ ppg_sensor_dat->led_data[led_index].offset_idac = hx3695_read_reg(0x48);\r
+ ppg_sensor_dat->led_data[led_index].tia_rf = hx3695_read_reg(0x44)&0x0f;\r
}\r
- fifo_out_length = fifo_out_length+phase_num-data_flg_end - 1;\r
- fifo_out_count = fifo_out_length/phase_num;\r
- return fifo_out_count;\r
+ }\r
}\r
\r
-void hx3695_vin_check(uint16_t led_vin)\r
+uint16_t hx3695_read_fifo_data(ppg_sensor_data_t *ppg_sensor_dat)\r
{\r
- low_vbat_flag = 0;\r
- if(led_vin < 3700)\r
+ uint8_t databuf[3];\r
+// uint32_t ii=0;\r
+ uint16_t data_len_h = 0;\r
+ uint16_t data_len_l = 0;\r
+ uint16_t fifo_data_length = 0;\r
+ uint16_t fifo_read_length = 0;\r
+ uint16_t fifo_read_bytes = 0;\r
+ uint16_t fifo_out_count = 0;\r
+\r
+ data_len_h = hx3695_read_reg(0x21);\r
+ data_len_l = hx3695_read_reg(0x20);\r
+ fifo_data_length = (((data_len_h&0x01)<<8)|data_len_l);\r
+\r
+ DEBUG_PRINTF("fifo_data_length: %d\r\n", fifo_data_length);\r
+ \r
+ if (fifo_data_length>FIFO_DATA_LENGTH)\r
+ {\r
+ fifo_data_length = FIFO_DATA_LENGTH;\r
+ }\r
+ \r
+ if(fifo_data_length<2*ppg_sensor_dat->led_activated)\r
+ {\r
+ return 0;\r
+ }\r
+ fifo_read_length = ((fifo_data_length-ppg_sensor_dat->led_activated)/ppg_sensor_dat->led_activated)*ppg_sensor_dat->led_activated;\r
+ fifo_read_bytes = fifo_read_length*3;\r
+ if(read_fifo_first_flg == 1)\r
{\r
- low_vbat_flag = 1;\r
+ hx3695_brust_read_reg(0x22, databuf, 3);\r
+ read_fifo_first_flg = 0;\r
}\r
+ hx3695_brust_read_reg(0x22, ppg_sensor_dat->s_buf, fifo_read_bytes);\r
+ fifo_out_count = hx3695_led_data_analysis(ppg_sensor_dat,fifo_read_length,1);\r
+\r
+ hx3695_get_led_para(ppg_sensor_dat);\r
+\r
+ return fifo_out_count;\r
}\r
\r
-void hx3695_ppg_off(void)\r
+void hx3695_read_phase_data(int32_t *s_buf)\r
{\r
+ uint8_t databuf1[6] = {0};\r
+ uint8_t databuf2[6] = {0};\r
+ uint8_t databuf3[6] = {0};\r
+ uint8_t databuf4[6] = {0};\r
+\r
+ hx3695_brust_read_reg(0x03, databuf1, 6);\r
+ hx3695_brust_read_reg(0x09, databuf2, 6);\r
+ hx3695_brust_read_reg(0x0f, databuf3, 6);\r
+ hx3695_brust_read_reg(0x15, databuf4, 6);\r
+\r
+ s_buf[0] = ((databuf1[0])|(databuf1[1]<<8)|(databuf1[2]<<16));\r
+ s_buf[1] = ((databuf1[3])|(databuf1[4]<<8)|(databuf1[5]<<16));\r
+ s_buf[2] = ((databuf2[0])|(databuf2[1]<<8)|(databuf2[2]<<16));\r
+ s_buf[3] = ((databuf2[3])|(databuf2[4]<<8)|(databuf2[5]<<16));\r
+ s_buf[4] = ((databuf3[0])|(databuf3[1]<<8)|(databuf3[2]<<16));\r
+ s_buf[5] = ((databuf3[3])|(databuf3[4]<<8)|(databuf3[5]<<16));\r
+ s_buf[6] = ((databuf4[0])|(databuf4[1]<<8)|(databuf4[2]<<16));\r
+ s_buf[7] = ((databuf4[3])|(databuf4[4]<<8)|(databuf4[5]<<16));\r
+ DEBUG_PRINTF("phase_buf = %d,%d,%d,%d,%d,%d,%d,%d \r\n", s_buf[0],s_buf[1],s_buf[2],s_buf[3],s_buf[4],s_buf[5],s_buf[6],s_buf[7]);\r
+}\r
\r
- hx3695_delay_ms(5);\r
+void hx3695_read_led_data(int32_t *s_buf)\r
+{\r
+ uint8_t databuf1[3] = {0};\r
+ uint8_t databuf2[3] = {0};\r
+ uint8_t databuf3[3] = {0};\r
+ uint8_t databuf4[3] = {0};\r
+\r
+ hx3695_brust_read_reg(0x06, databuf1, 3);\r
+ hx3695_brust_read_reg(0x0c, databuf2, 3);\r
+ hx3695_brust_read_reg(0x12, databuf3, 3);\r
+ hx3695_brust_read_reg(0x18, databuf4, 3);\r
+\r
+ s_buf[0] = ((databuf1[0])|(databuf1[1]<<8)|(databuf1[2]<<16));\r
+ s_buf[1] = ((databuf2[0])|(databuf2[1]<<8)|(databuf2[2]<<16));\r
+ s_buf[2] = ((databuf3[0])|(databuf3[1]<<8)|(databuf3[2]<<16));\r
+ s_buf[3] = ((databuf4[0])|(databuf4[1]<<8)|(databuf4[2]<<16));\r
+// DEBUG_PRINTF("led_buf = %d,%d,%d,%d\r\n", s_buf[0],s_buf[1],s_buf[2],s_buf[3]);\r
+}\r
+\r
+void hx3695_ppg_off(void)\r
+{\r
hx3695_write_reg(0x02, 0x01);\r
}\r
\r
hx3695_delay_ms(5);\r
}\r
\r
-void hx3695_data_reset(void)\r
+void hx3695_software_reset(void)\r
{\r
-#if defined(TIMMER_MODE)\r
- hx3695_320ms_timer_cfg(false);\r
- hx3695_40ms_timer_cfg(false);\r
-#elif defined(INT_MODE)\r
- hx3695_gpioint_cfg(false);\r
-#endif\r
-#if defined(HRS_ALG_LIB)\r
- hx3695_hrs_data_reset();\r
-#endif\r
-#if defined(SPO2_ALG_LIB)\r
- hx3695_spo2_data_reset();\r
-#endif\r
-#if defined(HRV_ALG_LIB)\r
- hx3695_hrv_data_reset();\r
-#endif\r
- AGC_LOG("hx3695 data reset!\r\n");\r
+ uint8_t ii = 0;\r
+ ppg_sensor_data.mode = NULL_MODE;\r
+ ppg_sensor_data.fs = 25;\r
+ ppg_sensor_data.watermark = 0;\r
+ ppg_sensor_data.led_activated = 0;\r
+ for(ii=0;ii<4;ii++)\r
+ {\r
+ ppg_sensor_data.led_data[ii].isneed_cal_start = false;\r
+ ppg_sensor_data.led_data[ii].led_current = 0;\r
+ ppg_sensor_data.led_data[ii].offset_idac = 0;\r
+ ppg_sensor_data.led_data[ii].tia_rf = 0;\r
+ ppg_sensor_data.led_data[ii].led_state = InActivated;\r
+ }\r
+ read_fifo_first_flg = 0;\r
+ s_ppg_state = 0;\r
+ s_cal_state = 0;\r
+ check_touch_cnt = 0;\r
+ hx3695_agc_reset();\r
+ #if defined(INT_MODE)\r
+ hx3695_gpioint_cfg(false);\r
+ #else\r
+ hx3695_320ms_timer_cfg(false);\r
+ hx3695_40ms_timer_cfg(false);\r
+ #endif\r
}\r
\r
-#ifdef HRS_ALG_LIB\r
-// 心率模式下ppg 初始化配置\r
-void hx3695_hrs_ppg_init(void) // ppg fs=25hz, phase conversion ready interupt en\r
+bool hx3695_check_wear(ppg_sensor_data_t *ppg_sensor_dat)\r
{\r
- uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
- uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */\r
- \r
- uint16_t fifo_watermark= 81 ;\r
- uint8_t adc_rst_post_num=0; /* 00=16,01=32,10=64,11=128*/ \r
- uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
- uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/\r
- uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/\r
- uint8_t phase7_8_internal = 0; /* phase7 and phase8 prf internal cfg */\r
- \r
- uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */\r
- uint8_t phase5_enable = 1; /*phase5_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase6_enable = 1; /*phase6_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase7_enable = 1; /*phase7_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ \r
-\r
- uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- \r
- uint8_t phase1_mux_sel = 0; /* sel phase1*/\r
- uint8_t phase2_mux_sel = 1; /* sel phase2*/\r
- uint8_t phase3_mux_sel = 2; /* sel phase3*/\r
- uint8_t phase4_mux_sel = 3; /* sel phase4*/\r
- uint8_t phase5_mux_sel = 4; /* sel phase5*/\r
- uint8_t phase6_mux_sel = 5; /* sel phase6*/\r
- uint8_t phase7_mux_sel = 6; /* sel phase7*/\r
- uint8_t phase8_mux_sel = 7; /* sel phase8*/\r
- \r
+ uint8_t ii = 0;\r
+ \r
+ for(ii=0;ii<ppg_sensor_dat->led_data[3].data_count;ii++)\r
+ {\r
+ if(ppg_sensor_dat->led_data[3].data_val[ii] > CHECK_WEAR_THRE)\r
+ {\r
+ if(check_touch_cnt < CHECK_TOUCH_NUM)\r
+ {\r
+ check_touch_cnt++; \r
+ } \r
+ if(check_touch_cnt >= CHECK_TOUCH_NUM) \r
+ {\r
+ wear_status = MSG_WEAR;\r
+ } \r
+ }\r
+ else if(ppg_sensor_dat->led_data[3].data_val[ii] < CHECK_UNWEAR_THRE)\r
+ {\r
+ if(check_touch_cnt>0)\r
+ {\r
+ check_touch_cnt--;\r
+ }\r
+ if(check_touch_cnt == 0)\r
+ {\r
+ wear_status = MSG_NO_WEAR; \r
+ } \r
+ }\r
+\r
+ DEBUG_PRINTF("data:%d, wear_status_pre:%d, wear_status:%d \r\n",ppg_sensor_dat->led_data[3].data_val[ii],wear_status_pre, wear_status);\r
+\r
+ if(wear_status_pre != wear_status)\r
+ {\r
+ // printf("wear_status:%d\n",wear_status);\r
+ wear_status_pre = wear_status;\r
+#ifdef SUPPORT_CYWEE_SERVICE\r
+ cywee_wear_status_update(&wear_status);\r
+#endif\r
+ // if(wear_status == MSG_NO_WEAR)\r
+ // {\r
+ // hx3695_wear_low_power(ppg_sensor_dat); \r
+ // }\r
+ // else if(wear_status == MSG_WEAR)\r
+ // {\r
+ // hx3695_init(work_mode_flag);\r
+ // } \r
+ } \r
+ }\r
+ return 1;\r
+}\r
\r
- uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase1_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */\r
- uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */\r
- uint8_t phase1_pd_sel = HRS_PD; //0x03 /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase1_ldr2_cur = 0;\r
+void hx3695_ppg_para_init(ppg_sensor_data_t *ppg_sensor_dat)\r
+{\r
+ uint16_t sample_rate = 25;\r
+ uint32_t prf_clk_num = 32000/sample_rate;\r
+// uint16_t watermark = 40;\r
+\r
+ uint8_t adc_rst_post_num=0;\r
+ uint8_t samp_delay_leden_num = 0;\r
+ uint8_t samp_copy_avg = 0;\r
+ uint8_t data_avg_num = 0;\r
+ uint8_t phase7_8_internal = 0;\r
+\r
+ uint8_t phase1_enable = 0;\r
+ uint8_t phase2_enable = 0;\r
+ uint8_t phase3_enable = 0;\r
+ uint8_t phase4_enable = 0;\r
+ uint8_t phase5_enable = 0;\r
+ uint8_t phase6_enable = 0;\r
+ uint8_t phase7_enable = 0;\r
+ uint8_t phase8_enable = 0;\r
+\r
+ uint8_t phase1_adc_osr = 3;\r
+ uint8_t phase2_adc_osr = 3;\r
+ uint8_t phase3_adc_osr = 3;\r
+ uint8_t phase4_adc_osr = 3;\r
+ uint8_t phase5_adc_osr = 3;\r
+ uint8_t phase6_adc_osr = 3;\r
+ uint8_t phase7_adc_osr = 3;\r
+ uint8_t phase8_adc_osr = 3;\r
+\r
+ uint8_t phase1_mux_sel = 0;\r
+ uint8_t phase2_mux_sel = 1;\r
+ uint8_t phase3_mux_sel = 2;\r
+ uint8_t phase4_mux_sel = 3;\r
+ uint8_t phase5_mux_sel = 4;\r
+ uint8_t phase6_mux_sel = 5;\r
+ uint8_t phase7_mux_sel = 6;\r
+ uint8_t phase8_mux_sel = 7;\r
+\r
+ uint8_t phase1_inner_avg = 0;\r
+ uint8_t phase1_tia_res = 0;\r
+ uint8_t phase1_tia_cap = 4;\r
+ uint8_t phase1_led_drv1_cha_sel = 0;\r
+ uint8_t phase1_led_drv2_cha_sel = 0;\r
+ uint8_t phase1_pd_sel = LED0_PD_SEL;\r
+ uint8_t phase1_als_offset_idac = 0;\r
+ uint8_t phase1_led_offset_idac = 0;\r
+ uint8_t phase1_ldr1_cur = 0;\r
+ uint8_t phase1_ldr2_cur = 0;\r
uint8_t phase1_ad_inr_ctrl = 3;\r
uint8_t phase1_ad_of_idac_ctrl = 0;\r
- uint8_t phase1_led_en = 1; /* phase1 led enable*/ \r
- uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
-\r
-\r
- uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase2_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase2_led_drv1_cha_sel = GREEN_LED_SLE; //0x10 //GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase2_led_drv2_cha_sel = 0;\r
- uint8_t phase2_pd_sel = HRS_PD; //0x0C //0x03 /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase2_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase2_ldr2_cur = 0;\r
+ uint8_t phase1_led_en = 1;\r
+ uint8_t phase1_dsp_mov_avg_num = 0;\r
+ uint8_t phase1_dsp_iir_lp_coeff = 0;\r
+\r
+ uint8_t phase2_inner_avg = 0;\r
+ uint8_t phase2_tia_res = 0;\r
+ uint8_t phase2_tia_cap = 4;\r
+ uint8_t phase2_led_drv1_cha_sel = LED0_LDR_SEL;\r
+ uint8_t phase2_led_drv2_cha_sel = LED0_LDR_SEL;\r
+ uint8_t phase2_pd_sel = LED0_PD_SEL;\r
+ uint8_t phase2_als_offset_idac = 0;\r
+ uint8_t phase2_led_offset_idac = 0;\r
+ uint8_t phase2_ldr1_cur = 0;\r
+ uint8_t phase2_ldr2_cur = 0;\r
uint8_t phase2_ad_inr_ctrl = 3;\r
uint8_t phase2_ad_of_idac_ctrl = 0;\r
- uint8_t phase2_led_en = 1; /* phase1 led enable*/ \r
- uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- \r
- uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase3_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase3_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase2_led_en = 1;\r
+ uint8_t phase2_dsp_mov_avg_num = 0;\r
+ uint8_t phase2_dsp_iir_lp_coeff = 0;\r
+\r
+ uint8_t phase3_inner_avg = 0;\r
+ uint8_t phase3_tia_res = 0;\r
+ uint8_t phase3_tia_cap = 4;\r
+ uint8_t phase3_led_drv1_cha_sel = 0;\r
uint8_t phase3_led_drv2_cha_sel = 0;\r
- uint8_t phase3_pd_sel = HRS_PD; //0x03 /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase3_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase3_ldr2_cur = 0;\r
+ uint8_t phase3_pd_sel = LED1_PD_SEL;\r
+ uint8_t phase3_als_offset_idac = 0;\r
+ uint8_t phase3_led_offset_idac = 0;\r
+ uint8_t phase3_ldr1_cur = 0;\r
+ uint8_t phase3_ldr2_cur = 0;\r
uint8_t phase3_ad_inr_ctrl = 3;\r
uint8_t phase3_ad_of_idac_ctrl = 0;\r
- uint8_t phase3_led_en = 1; /* phase1 led enable*/ \r
- uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- \r
- uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase4_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase4_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase4_led_drv2_cha_sel = 0;\r
- uint8_t phase4_pd_sel = HRS_PD; //0x0C /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase4_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase4_ldr2_cur = 0;\r
-// uint8_t phase4_of_idac1_cur = 0;\r
-// uint8_t phase4_of_idac2_cur = 0;\r
+ uint8_t phase3_led_en = 1;\r
+ uint8_t phase3_dsp_mov_avg_num = 0;\r
+ uint8_t phase3_dsp_iir_lp_coeff = 0;\r
+\r
+ uint8_t phase4_inner_avg = 0;\r
+ uint8_t phase4_tia_res = 0;\r
+ uint8_t phase4_tia_cap = 4;\r
+ uint8_t phase4_led_drv1_cha_sel = LED1_LDR_SEL;\r
+ uint8_t phase4_led_drv2_cha_sel = LED1_LDR_SEL;\r
+ uint8_t phase4_pd_sel = LED1_PD_SEL;\r
+ #ifdef DOUBLE_GREEN\r
+ if(ppg_sensor_dat->mode == HRS_MODE)\r
+ {\r
+ phase4_led_drv1_cha_sel = LED1N_LDR_SEL;\r
+ phase4_led_drv2_cha_sel = LED1N_LDR_SEL;\r
+ phase4_pd_sel = LED1N_PD_SEL;\r
+ }\r
+ #endif\r
+ uint8_t phase4_als_offset_idac = 0;\r
+ uint8_t phase4_led_offset_idac = 0;\r
+ uint8_t phase4_ldr1_cur = 0;\r
+ uint8_t phase4_ldr2_cur = 0;\r
uint8_t phase4_ad_inr_ctrl = 3;\r
uint8_t phase4_ad_of_idac_ctrl = 0;\r
-// uint8_t phase4_afe_offset = 0;\r
- uint8_t phase4_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase5_led_drv1_cha_sel = 0; //0x10 /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase4_led_en = 1;\r
+ uint8_t phase4_dsp_mov_avg_num = 0;\r
+ uint8_t phase4_dsp_iir_lp_coeff = 0;\r
+\r
+ uint8_t phase5_inner_avg = 0;\r
+ uint8_t phase5_tia_res = 0;\r
+ uint8_t phase5_tia_cap = 4;\r
+ uint8_t phase5_led_drv1_cha_sel = 0;\r
uint8_t phase5_led_drv2_cha_sel = 0;\r
- uint8_t phase5_pd_sel = HRS_PD; //0x0C /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase5_ldr2_cur = 0;\r
-// uint8_t phase5_of_idac1_cur = 0;\r
-// uint8_t phase5_of_idac2_cur = 0;\r
+ uint8_t phase5_pd_sel = LED2_PD_SEL;\r
+ uint8_t phase5_als_offset_idac = 0;\r
+ uint8_t phase5_led_offset_idac = 0;\r
+ uint8_t phase5_ldr1_cur = 0;\r
+ uint8_t phase5_ldr2_cur = 0;\r
uint8_t phase5_ad_inr_ctrl = 3;\r
uint8_t phase5_ad_of_idac_ctrl = 0;\r
-// uint8_t phase5_afe_offset = 0;\r
- uint8_t phase5_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase6_led_drv2_cha_sel = 0;\r
- uint8_t phase6_pd_sel = HRS_PD; //0x0C /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase6_ldr2_cur = 0;\r
-// uint8_t phase6_of_idac1_cur = 0;\r
-// uint8_t phase6_of_idac2_cur = 0;\r
+ uint8_t phase5_led_en = 1;\r
+ uint8_t phase5_dsp_mov_avg_num = 0;\r
+ uint8_t phase5_dsp_iir_lp_coeff = 0;\r
+\r
+ uint8_t phase6_inner_avg = 0;\r
+ uint8_t phase6_tia_res = 0;\r
+ uint8_t phase6_tia_cap = 4;\r
+ uint8_t phase6_led_drv1_cha_sel = LED2_LDR_SEL;\r
+ uint8_t phase6_led_drv2_cha_sel = LED2_LDR_SEL;\r
+ uint8_t phase6_pd_sel = LED2_PD_SEL;\r
+ uint8_t phase6_als_offset_idac = 0;\r
+ uint8_t phase6_led_offset_idac = 0;\r
+ uint8_t phase6_ldr1_cur = 0;\r
+ uint8_t phase6_ldr2_cur = 0;\r
uint8_t phase6_ad_inr_ctrl = 3;\r
uint8_t phase6_ad_of_idac_ctrl = 0;\r
-// uint8_t phase6_afe_offset = 0;\r
- uint8_t phase6_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase6_led_en = 1;\r
+ uint8_t phase6_dsp_mov_avg_num = 0;\r
+ uint8_t phase6_dsp_iir_lp_coeff = 0;\r
+\r
+ uint8_t phase7_inner_avg = 0;\r
+ uint8_t phase7_tia_res = 1;\r
+ uint8_t phase7_tia_cap = 4;\r
+ uint8_t phase7_led_drv1_cha_sel = 0;\r
uint8_t phase7_led_drv2_cha_sel = 0;\r
- uint8_t phase7_pd_sel = SPO2_PD; //0x0C /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase7_ldr2_cur = 0;\r
-// uint8_t phase7_of_idac1_cur = 0;\r
-// uint8_t phase7_of_idac2_cur = 0;\r
+ uint8_t phase7_pd_sel = LED3_PD_SEL;\r
+ uint8_t phase7_als_offset_idac = 0;\r
+ uint8_t phase7_led_offset_idac = 0;\r
+ uint8_t phase7_ldr1_cur = 0;\r
+ uint8_t phase7_ldr2_cur = 0;\r
uint8_t phase7_ad_inr_ctrl = 3;\r
uint8_t phase7_ad_of_idac_ctrl = 0;\r
-// uint8_t phase7_afe_offset = 0;\r
- uint8_t phase7_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase8_led_drv1_cha_sel = IR_LED_SLE; //0x40 //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase8_led_drv2_cha_sel = 0;\r
- uint8_t phase8_pd_sel = SPO2_PD; //0x0C /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase8_ldr1_cur = 32; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase8_ldr2_cur = 0;\r
-// uint8_t phase8_of_idac1_cur = 0;\r
-// uint8_t phase8_of_idac2_cur = 0;\r
+ uint8_t phase7_led_en = 1;\r
+ uint8_t phase7_dsp_mov_avg_num = 0;\r
+ uint8_t phase7_dsp_iir_lp_coeff = 0;\r
+\r
+ uint8_t phase8_inner_avg = 0;\r
+ uint8_t phase8_tia_res = 1;\r
+ uint8_t phase8_tia_cap = 4;\r
+ uint8_t phase8_led_drv1_cha_sel = LED3_LDR_SEL;\r
+ uint8_t phase8_led_drv2_cha_sel = LED3_LDR_SEL;\r
+ uint8_t phase8_pd_sel = LED3_PD_SEL;\r
+ uint8_t phase8_als_offset_idac = 0;\r
+ uint8_t phase8_led_offset_idac = 0;\r
+ uint8_t phase8_ldr1_cur = 20;\r
+ uint8_t phase8_ldr2_cur = 0;\r
uint8_t phase8_ad_inr_ctrl = 3;\r
uint8_t phase8_ad_of_idac_ctrl = 0;\r
-// uint8_t phase8_afe_offset = 0;\r
- uint8_t phase8_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t init_wait_delay = 5 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ;\r
- 4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ \r
- \r
- uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ;\r
- 4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */\r
- \r
- uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/\r
- \r
- uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ \r
- \r
- uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ \r
- \r
- uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ;\r
- 4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */\r
- \r
- hx3695_delay_ms(10); \r
- \r
- hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6\r
- hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8>\r
- hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> \r
- \r
- hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); \r
- hx3695_write_reg(0X2d, phase7_8_internal); \r
- hx3695_write_reg(0X2e, 0x33);// gpio ctrl \r
+ uint8_t phase8_led_en = 1;\r
+ uint8_t phase8_dsp_mov_avg_num = 0;\r
+ uint8_t phase8_dsp_iir_lp_coeff = 0;\r
+\r
+ uint8_t init_wait_delay = 5;\r
+ uint8_t afe_reset = 3;\r
+ uint8_t afe_rst_cnvt = 1;\r
+ uint8_t led_en_idac_pre = 2;\r
+ uint8_t led_en_idac = 1;\r
+ uint8_t led_on_time = 3;\r
+\r
+ hx3695_write_reg(0x02,0x00);\r
+ hx3695_delay_ms(10);\r
+\r
+ hx3695_write_reg(0X2a, (uint8_t)prf_clk_num);\r
+ hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8));\r
+ hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16));\r
+\r
+ hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac));\r
+ hx3695_write_reg(0X2d, phase7_8_internal);\r
+ hx3695_write_reg(0X2e, 0x33);\r
hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay));\r
- hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
+ hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
\r
-\r
- hx3695_write_reg(0X31, (led_on_time<<4| 0x00));\r
- hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置；\r
- hx3695_write_reg(0X34, 0x00);// 中断特殊配置；\r
- hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置；\r
- hx3695_write_reg(0X38, 0x00);\r
- \r
- hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); \r
- hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); \r
- hx3695_write_reg(0X3c, (phase5_inner_avg | (phase6_inner_avg<<4))); \r
- hx3695_write_reg(0X3d, (phase7_inner_avg | (phase8_inner_avg<<4))); \r
- hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); \r
+ hx3695_write_reg(0X31, led_on_time<<4);\r
+ hx3695_write_reg(0X33, 0x83);\r
+ hx3695_write_reg(0X34, 0x00);\r
+ hx3695_write_reg(0X36, 0x00);\r
+ hx3695_write_reg(0X38, 0x00);\r
+\r
+ hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4)));\r
+ hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4)));\r
+ hx3695_write_reg(0X3c, (phase5_inner_avg | (phase6_inner_avg<<4)));\r
+ hx3695_write_reg(0X3d, (phase7_inner_avg | (phase8_inner_avg<<4)));\r
+ hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg);\r
hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num );\r
hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num );\r
- \r
- hx3695_write_reg(0X43, phase1_mux_sel); \r
- hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); \r
- hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase1_als_offset_idac);\r
- hx3695_write_reg(0X48, phase1_led_offset_idac);\r
-\r
- hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4);\r
-\r
-// hx3695_write_reg(0X4e, thred_value);\r
-// hx3695_write_reg(0X4f, thred_value>>5);\r
- \r
- hx3695_write_reg(0X43, phase2_mux_sel); \r
- hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); \r
- hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase2_als_offset_idac);\r
- hx3695_write_reg(0X48, phase2_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4);\r
- \r
-//phase3 sel\r
-\r
- hx3695_write_reg(0X43, phase3_mux_sel); \r
- hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); \r
- hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase3_als_offset_idac);\r
- hx3695_write_reg(0X48, phase3_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4);\r
- \r
-//phase4 sel\r
-\r
- hx3695_write_reg(0X43, phase4_mux_sel); \r
- hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); \r
- hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase4_als_offset_idac);\r
- hx3695_write_reg(0X48, phase4_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4);\r
-\r
- hx3695_write_reg(0X43, phase5_mux_sel); \r
- hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); \r
- hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase5_als_offset_idac);\r
- hx3695_write_reg(0X48, phase5_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase6_mux_sel); \r
- hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); \r
- hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase6_als_offset_idac);\r
- hx3695_write_reg(0X48, phase6_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase6_led_offset_idac);\r
- hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase7_mux_sel); \r
- hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); \r
- hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase7_als_offset_idac);\r
- hx3695_write_reg(0X48, phase7_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase7_led_offset_idac);\r
- hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase8_mux_sel); \r
- hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); \r
- hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase8_als_offset_idac);\r
- hx3695_write_reg(0X48, phase8_led_offset_idac);\r
-// hx3695_write_reg(0X48, phas8_led_offset_idac);\r
- hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4);\r
- \r
-\r
-// analog circuit cfg \r
- hx3695_write_reg(0X60, 0x14); //\r
- hx3695_write_reg(0X61, 0xf0); \r
- hx3695_write_reg(0X62, 0x22); \r
- hx3695_write_reg(0X63, 0x15); \r
- \r
- hx3695_write_reg(0X64, 0x08); \r
- hx3695_write_reg(0X65, 0x88); //bug\r
- \r
- hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30\r
- hx3695_write_reg(0X67, 0x23); \r
- hx3695_write_reg(0X68, 0x46); \r
- hx3695_write_reg(0X69, 0x42); \r
- \r
- hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg\r
- hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable\r
- \r
- hx3695_write_reg(0X6a, 0X0f); \r
- hx3695_write_reg(0X6b, 0X22); \r
- hx3695_write_reg(0X6c, 0X00); \r
- hx3695_write_reg(0X6d, 0X37); \r
- hx3695_write_reg(0X6e, 0X82); \r
+ hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num );\r
+ hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num );\r
+\r
+ hx3695_write_reg(0X43, phase1_mux_sel);\r
+ hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res);\r
+ hx3695_write_reg(0X45, phase1_ldr1_cur);\r
+ hx3695_write_reg(0x70, phase1_ldr2_cur);\r
+ hx3695_write_reg(0X46, phase1_pd_sel<<4);\r
+ hx3695_write_reg(0X47, phase1_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase1_led_offset_idac);\r
+ hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl);\r
+ hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4);\r
+\r
+ hx3695_write_reg(0X43, phase2_mux_sel);\r
+ hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res);\r
+ hx3695_write_reg(0X45, phase2_ldr1_cur);\r
+ hx3695_write_reg(0x70, phase2_ldr2_cur);\r
+ hx3695_write_reg(0X46, phase2_pd_sel<<4);\r
+ hx3695_write_reg(0X47, phase2_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase2_led_offset_idac);\r
+ hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl);\r
+ hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4);\r
+\r
+ hx3695_write_reg(0X43, phase3_mux_sel);\r
+ hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res);\r
+ hx3695_write_reg(0X45, phase3_ldr1_cur);\r
+ hx3695_write_reg(0x70, phase3_ldr2_cur);\r
+ hx3695_write_reg(0X46, phase3_pd_sel<<4);\r
+ hx3695_write_reg(0X47, phase3_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase3_led_offset_idac);\r
+ hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl);\r
+ hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4);\r
+\r
+ hx3695_write_reg(0X43, phase4_mux_sel);\r
+ hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res);\r
+ hx3695_write_reg(0X45, phase4_ldr1_cur);\r
+ hx3695_write_reg(0x70, phase4_ldr2_cur);\r
+ hx3695_write_reg(0X46, phase4_pd_sel<<4);\r
+ hx3695_write_reg(0X47, phase4_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase4_led_offset_idac);\r
+ hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl);\r
+ hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4);\r
+\r
+ hx3695_write_reg(0X43, phase5_mux_sel);\r
+ hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res);\r
+ hx3695_write_reg(0X45, phase5_ldr1_cur);\r
+ hx3695_write_reg(0x70, phase5_ldr2_cur);\r
+ hx3695_write_reg(0X46, phase5_pd_sel<<4);\r
+ hx3695_write_reg(0X47, phase5_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase5_led_offset_idac);\r
+ hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl);\r
+ hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4);\r
+\r
+ hx3695_write_reg(0X43, phase6_mux_sel);\r
+ hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res);\r
+ hx3695_write_reg(0X45, phase6_ldr1_cur);\r
+ hx3695_write_reg(0x70, phase6_ldr2_cur);\r
+ hx3695_write_reg(0X46, phase6_pd_sel<<4);\r
+ hx3695_write_reg(0X47, phase6_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase6_led_offset_idac);\r
+ hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl);\r
+ hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4);\r
+\r
+ hx3695_write_reg(0X43, phase7_mux_sel);\r
+ hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res);\r
+ hx3695_write_reg(0X45, phase7_ldr1_cur);\r
+ hx3695_write_reg(0x70, phase7_ldr2_cur);\r
+ hx3695_write_reg(0X46, phase7_pd_sel<<4);\r
+ hx3695_write_reg(0X47, phase7_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase7_led_offset_idac);\r
+ hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl);\r
+ hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4);\r
+\r
+ hx3695_write_reg(0X43, phase8_mux_sel);\r
+ hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res);\r
+ hx3695_write_reg(0X45, phase8_ldr1_cur);\r
+ hx3695_write_reg(0x70, phase8_ldr2_cur);\r
+ hx3695_write_reg(0X46, phase8_pd_sel<<4);\r
+ hx3695_write_reg(0X47, phase8_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase8_led_offset_idac);\r
+ hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl);\r
+ hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4);\r
+\r
+ hx3695_write_reg(0X60, 0x14);\r
+ hx3695_write_reg(0X61, 0xf0);\r
+ hx3695_write_reg(0X62, 0x22);\r
+ hx3695_write_reg(0X63, 0x15);\r
+ hx3695_write_reg(0X64, 0x08);\r
+ hx3695_write_reg(0X65, 0x88);\r
+ hx3695_write_reg(0X66, 0x30);\r
+ hx3695_write_reg(0X67, 0x23);\r
+ hx3695_write_reg(0X68, 0x46);\r
+ hx3695_write_reg(0X69, 0x42);\r
+ hx3695_write_reg(0X39, 0xff);\r
+ hx3695_write_reg(0x73, 0xff);\r
+ hx3695_write_reg(0X6a, 0X0f);\r
+ hx3695_write_reg(0X6b, 0X22);\r
+ hx3695_write_reg(0X6c, 0X00);\r
+ hx3695_write_reg(0X6d, 0X37);\r
+ hx3695_write_reg(0X6e, 0X82);\r
hx3695_write_reg(0X6f, 0X00);\r
-/////////FIFO and adc conversion ready config////////\r
-/////////FIFO and adc conversion ready config////////\r
-#if defined(PPG_INT_MODE)\r
- hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\ bits<7> fifo enble\r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int\r
-#elif defined(INT_MODE) //FIFO_ALL_MOST_FULL)\r
- hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
- hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark\r
- hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] \r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
\r
+#if defined(INT_MODE)\r
+ hx3695_write_reg(0X1b, 0x91);\r
+ hx3695_write_reg(0X1c, watermark);\r
+ hx3695_write_reg(0X33, 0x83);\r
+ hx3695_write_reg(0X21, 0x00);\r
+ hx3695_write_reg(0X38, 0x04);\r
#else\r
- hx3695_write_reg(0X1b, 0x92); \r
- \r
- hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int\r
- \r
+ hx3695_write_reg(0X1b, 0x91);\r
+ hx3695_write_reg(0X38, 0x01);\r
#endif\r
\r
- \r
- hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); \r
- hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); \r
+ hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) );\r
+ hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) );\r
hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) );\r
- hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); \r
-\r
-// hx3695_write_reg(0X5c, 0x02);//soft reset\r
- hx3695_delay_ms(5); \r
- hx3695_write_reg(0X5c, 0x00);//release\r
+ hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) );\r
+\r
+ hx3695_write_reg(0X5c, 0x02);\r
+ hx3695_delay_ms(1);\r
+ hx3695_write_reg(0X1b, 0x10);\r
+ hx3695_delay_ms(1);\r
+ hx3695_write_reg(0X1b, 0x91);\r
+ hx3695_write_reg(0X5c, 0x00);\r
read_fifo_first_flg = 1;\r
return ;\r
}\r
-#endif\r
\r
-#ifdef SPO2_ALG_LIB\r
-// 血氧模式下 初始化配置\r
-void hx3695_spo2_ppg_init(void) //20200615 ericy ppg fs=25hz, phase3 conversion ready interupt en\r
+void hx3695_set_fs(ppg_sensor_data_t *ppg_sensor_dat)\r
{\r
- uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
- uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */\r
- \r
- uint16_t fifo_watermark= 250 ;\r
- uint8_t adc_rst_post_num=0; /* 00=16,01=32,10=64,11=128*/ \r
- uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
- uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/\r
- uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/\r
- uint8_t phase7_8_internal = 0; /* phase7 and phase8 prf internal cfg */\r
- \r
-// uint16_t thred_value = 32500;\r
- \r
- uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */\r
- uint8_t phase5_enable = 1; /*phase5_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase6_enable = 1; /*phase6_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase7_enable = 1; /*phase7_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ \r
-\r
- uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- \r
- uint8_t phase1_mux_sel = 0; /* sel phase1*/\r
- uint8_t phase2_mux_sel = 1; /* sel phase2*/\r
- uint8_t phase3_mux_sel = 2; /* sel phase3*/\r
- uint8_t phase4_mux_sel = 3; /* sel phase4*/\r
- uint8_t phase5_mux_sel = 4; /* sel phase5*/\r
- uint8_t phase6_mux_sel = 5; /* sel phase6*/\r
- uint8_t phase7_mux_sel = 6; /* sel phase7*/\r
- uint8_t phase8_mux_sel = 7; /* sel phase8*/\r
- \r
+ uint32_t prf_clk_num = 32000/ppg_sensor_dat->fs;\r
\r
- uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase1_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */\r
- uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */\r
- uint8_t phase1_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase1_ldr2_cur = 0;\r
-// uint8_t phase1_of_idac1_cur = 0;\r
-// uint8_t phase1_of_idac2_cur = 0;\r
- uint8_t phase1_ad_inr_ctrl = 3;\r
- uint8_t phase1_ad_of_idac_ctrl = 0;\r
-// uint8_t afe_offset = 0;\r
- uint8_t phase1_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
-\r
-\r
- uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase2_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase2_led_drv1_cha_sel = GREEN_LED_SLE; //GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase2_led_drv2_cha_sel = 0x00;\r
- uint8_t phase2_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase2_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase2_ldr2_cur = 0;\r
-// uint8_t phase2_of_idac1_cur = 0;\r
-// uint8_t phase2_of_idac2_cur = 0;\r
- uint8_t phase2_ad_inr_ctrl = 3;\r
- uint8_t phase2_ad_of_idac_ctrl = 0;\r
-// uint8_t phase2_afe_offset = 0;\r
- uint8_t phase2_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
+ hx3695_write_reg(0X2a, (uint8_t)prf_clk_num);\r
+ hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8));\r
+ hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16));\r
\r
- \r
- uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase3_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase3_led_drv1_cha_sel = 0; //RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase3_led_drv2_cha_sel = 0;\r
- uint8_t phase3_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase3_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase3_ldr2_cur = 0;\r
-// uint8_t phase3_of_idac1_cur = 0;\r
-// uint8_t phase3_of_idac2_cur = 0;\r
- uint8_t phase3_ad_inr_ctrl = 3;\r
- uint8_t phase3_ad_of_idac_ctrl = 0;\r
-// uint8_t phase3_afe_offset = 0;\r
- uint8_t phase3_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
+ hx3695_write_reg(0X5c, 0x02);\r
+ hx3695_delay_ms(1);\r
+ hx3695_write_reg(0X5c, 0x00);\r
+}\r
\r
- \r
- uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase4_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase4_led_drv1_cha_sel = RED_LED_SLE; //0x20 //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase4_led_drv2_cha_sel = 0;\r
- uint8_t phase4_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase4_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase4_ldr2_cur = 0;\r
-// uint8_t phase4_of_idac1_cur = 0;\r
-// uint8_t phase4_of_idac2_cur = 0;\r
- uint8_t phase4_ad_inr_ctrl = 3;\r
- uint8_t phase4_ad_of_idac_ctrl = 0;\r
-// uint8_t phase4_afe_offset = 0;\r
- uint8_t phase4_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase5_led_drv1_cha_sel = 0x00; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase5_led_drv2_cha_sel = 0;\r
- uint8_t phase5_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase5_ldr2_cur = 0;\r
-// uint8_t phase5_of_idac1_cur = 0;\r
-// uint8_t phase5_of_idac2_cur = 0;\r
- uint8_t phase5_ad_inr_ctrl = 3;\r
- uint8_t phase5_ad_of_idac_ctrl = 0;\r
-// uint8_t phase5_afe_offset = 0;\r
- uint8_t phase5_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase6_led_drv1_cha_sel = IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase6_led_drv2_cha_sel = 0;\r
- uint8_t phase6_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase6_ldr2_cur = 0;\r
-// uint8_t phase6_of_idac1_cur = 0;\r
-// uint8_t phase6_of_idac2_cur = 0;\r
- uint8_t phase6_ad_inr_ctrl = 3;\r
- uint8_t phase6_ad_of_idac_ctrl = 0;\r
-// uint8_t phase6_afe_offset = 0;\r
- uint8_t phase6_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase7_led_drv2_cha_sel = 0;\r
- uint8_t phase7_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase7_ldr2_cur = 0;\r
-// uint8_t phase7_of_idac1_cur = 0;\r
-// uint8_t phase7_of_idac2_cur = 0;\r
- uint8_t phase7_ad_inr_ctrl = 3;\r
- uint8_t phase7_ad_of_idac_ctrl = 0;\r
-// uint8_t phase7_afe_offset = 0;\r
- uint8_t phase7_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase8_led_drv1_cha_sel = IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase8_led_drv2_cha_sel = 0;\r
- uint8_t phase8_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase8_ldr1_cur = 32; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase8_ldr2_cur = 0;\r
-// uint8_t phase8_of_idac1_cur = 0;\r
-// uint8_t phase8_of_idac2_cur = 0;\r
- uint8_t phase8_ad_inr_ctrl = 3;\r
- uint8_t phase8_ad_of_idac_ctrl = 0;\r
-// uint8_t phase8_afe_offset = 0;\r
- uint8_t phase8_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ;\r
- 4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ \r
- \r
- uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ;\r
- 4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */\r
- \r
- uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/\r
- \r
- uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ \r
- \r
- uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ \r
- \r
- uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ;\r
- 4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */\r
- \r
- hx3695_delay_ms(10); \r
- \r
- hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6\r
- hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8>\r
- hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> \r
- \r
- hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); \r
- hx3695_write_reg(0X2d, phase7_8_internal); \r
- hx3695_write_reg(0X2e, 0x33);// gpio ctrl \r
- hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay));\r
- hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
- hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
-\r
-\r
- hx3695_write_reg(0X31, (led_on_time<<4| 0x00));\r
- hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置；\r
- hx3695_write_reg(0X34, 0x00);// 中断特殊配置；\r
- hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置；\r
- hx3695_write_reg(0X38, 0x00);\r
- \r
- hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); \r
- hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); \r
- hx3695_write_reg(0X3c, (phase5_inner_avg | (phase6_inner_avg<<4))); \r
- hx3695_write_reg(0X3d, (phase7_inner_avg | (phase8_inner_avg<<4))); \r
- hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); \r
- hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num );\r
- \r
- hx3695_write_reg(0X43, phase1_mux_sel); \r
- hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); \r
- hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase1_als_offset_idac);\r
- hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4);\r
-\r
- \r
- hx3695_write_reg(0X43, phase2_mux_sel); \r
- hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); \r
- hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase2_als_offset_idac);\r
- hx3695_write_reg(0X48, phase2_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4);\r
- \r
-//phase3 sel\r
-\r
- hx3695_write_reg(0X43, phase3_mux_sel); \r
- hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); \r
- hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase3_als_offset_idac);\r
- hx3695_write_reg(0X48, phase3_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4);\r
- \r
-//phase4 sel\r
-\r
- hx3695_write_reg(0X43, phase4_mux_sel); \r
- hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); \r
- hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase4_als_offset_idac);\r
- hx3695_write_reg(0X48, phase4_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4);\r
-\r
- hx3695_write_reg(0X43, phase5_mux_sel); \r
- hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); \r
- hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase5_als_offset_idac);\r
- hx3695_write_reg(0X48, phase5_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase6_mux_sel); \r
- hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); \r
- hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase6_als_offset_idac);\r
- hx3695_write_reg(0X48, phase6_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase6_led_offset_idac);\r
- hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase7_mux_sel); \r
- hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); \r
- hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase7_als_offset_idac);\r
- hx3695_write_reg(0X48, phase7_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase7_led_offset_idac);\r
- hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase8_mux_sel); \r
- hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); \r
- hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase8_als_offset_idac);\r
- hx3695_write_reg(0X48, phase8_led_offset_idac);\r
-// hx3695_write_reg(0X48, phas8_led_offset_idac);\r
- hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4);\r
- \r
-\r
-// analog circuit cfg \r
- hx3695_write_reg(0X60, 0x14); //\r
- hx3695_write_reg(0X61, 0xf0); \r
- hx3695_write_reg(0X62, 0x22); \r
- hx3695_write_reg(0X63, 0x15); \r
- \r
- hx3695_write_reg(0X64, 0x08); \r
- hx3695_write_reg(0X65, 0x88); //bug\r
- \r
- hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30\r
- hx3695_write_reg(0X67, 0x23); \r
- hx3695_write_reg(0X68, 0x46); \r
- hx3695_write_reg(0X69, 0x42); \r
- \r
- hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg\r
- hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable\r
- \r
- hx3695_write_reg(0X6a, 0X0f); \r
- hx3695_write_reg(0X6b, 0X22); \r
- hx3695_write_reg(0X6c, 0X00); \r
- hx3695_write_reg(0X6d, 0X37); \r
- hx3695_write_reg(0X6e, 0X82); \r
- hx3695_write_reg(0X6f, 0X00);\r
-/////////FIFO and adc conversion ready config////////\r
-/////////FIFO and adc conversion ready config////////\r
-#if defined(PPG_INT_MODE)\r
- hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\ bits<7> fifo enble\r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X38, 0x08); // int sel,00=close almost full int,04=enable almost full int\r
-#elif defined(INT_MODE) //(FIFO_ALL_MOST_FULL)\r
- hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
- hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark\r
- hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] \r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
-\r
-#else\r
- hx3695_write_reg(0X1b, 0x91);\r
- hx3695_write_reg(0X36, 0x00); \r
- \r
- hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int\r
-\r
-#endif\r
-\r
- \r
- hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); \r
- hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); \r
- hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) );\r
- hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); \r
-\r
- hx3695_write_reg(0X5c, 0x02);//soft reset\r
- hx3695_delay_ms(5); \r
- hx3695_write_reg(0X5c, 0x00);//release\r
-// uint8_t fifo_data_temp[3] = {0};\r
-// hx3695_brust_read_reg(0x22, fifo_data_temp, 3); \r
- read_fifo_first_flg = 1;\r
- return ;\r
-\r
-}\r
-#endif\r
-\r
-#ifdef HRV_ALG_LIB\r
-// HRV模式下 初始化配置\r
-void hx3695_hrv_ppg_init(void) //20200615 ericy ppg fs=25hz, phase3 conversion ready interupt en\r
-{\r
- uint16_t sample_rate = 125; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
- uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */\r
- \r
- uint8_t adc_rst_post_num=0; /* 00=16,01=32,10=64,11=128*/ \r
- uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
- uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/\r
- uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/\r
- uint8_t phase7_8_internal = 0; /* phase7 and phase8 prf internal cfg */\r
- \r
- uint16_t fifo_watermark= 164 ;\r
- uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */\r
- uint8_t phase5_enable = 0; /*phase5_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase6_enable = 0; /*phase6_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase7_enable = 0; /*phase7_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase8_enable = 0; /*phase8_enable , 1 mean enable ; 0 mean disable */ \r
-\r
- uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- \r
- uint8_t phase1_mux_sel = 0; /* sel phase1*/\r
- uint8_t phase2_mux_sel = 1; /* sel phase2*/\r
- uint8_t phase3_mux_sel = 2; /* sel phase3*/\r
- uint8_t phase4_mux_sel = 3; /* sel phase4*/\r
- uint8_t phase5_mux_sel = 4; /* sel phase5*/\r
- uint8_t phase6_mux_sel = 5; /* sel phase6*/\r
- uint8_t phase7_mux_sel = 6; /* sel phase7*/\r
- uint8_t phase8_mux_sel = 7; /* sel phase8*/\r
- \r
-\r
- uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase1_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase1_led_drv1_cha_sel = 0X10; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */\r
- uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */\r
- uint8_t phase1_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase1_ldr2_cur = 0;\r
-// uint8_t phase1_of_idac1_cur = 0;\r
-// uint8_t phase1_of_idac2_cur = 0;\r
- uint8_t phase1_ad_inr_ctrl = 3;\r
- uint8_t phase1_ad_of_idac_ctrl = 0;\r
-// uint8_t afe_offset = 0;\r
- uint8_t phase1_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
-\r
-\r
- uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase2_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase2_led_drv1_cha_sel = 0; //GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase2_led_drv2_cha_sel = 0;\r
- uint8_t phase2_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase2_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase2_ldr2_cur = 0;\r
-// uint8_t phase2_of_idac1_cur = 0;\r
-// uint8_t phase2_of_idac2_cur = 0;\r
- uint8_t phase2_ad_inr_ctrl = 3;\r
- uint8_t phase2_ad_of_idac_ctrl = 0;\r
-// uint8_t phase2_afe_offset = 0;\r
- uint8_t phase2_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- \r
- uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase3_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase3_led_drv1_cha_sel = 0x08; //0x40 //RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase3_led_drv2_cha_sel = 0;\r
- uint8_t phase3_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase3_ldr1_cur = 15; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase3_ldr2_cur = 0;\r
-// uint8_t phase3_of_idac1_cur = 0;\r
-// uint8_t phase3_of_idac2_cur = 0;\r
- uint8_t phase3_ad_inr_ctrl = 3;\r
- uint8_t phase3_ad_of_idac_ctrl = 0;\r
-// uint8_t phase3_afe_offset = 0;\r
- uint8_t phase3_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- \r
- uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase4_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase4_led_drv1_cha_sel = 0; //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase4_led_drv2_cha_sel = 0;\r
- uint8_t phase4_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase4_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase4_ldr2_cur = 0;\r
-// uint8_t phase4_of_idac1_cur = 0;\r
-// uint8_t phase4_of_idac2_cur = 0;\r
- uint8_t phase4_ad_inr_ctrl = 3;\r
- uint8_t phase4_ad_of_idac_ctrl = 0;\r
-// uint8_t phase4_afe_offset = 0;\r
- uint8_t phase4_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase5_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase5_led_drv2_cha_sel = 0;\r
- uint8_t phase5_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase5_ldr2_cur = 0;\r
-// uint8_t phase5_of_idac1_cur = 0;\r
-// uint8_t phase5_of_idac2_cur = 0;\r
- uint8_t phase5_ad_inr_ctrl = 3;\r
- uint8_t phase5_ad_of_idac_ctrl = 0;\r
-// uint8_t phase5_afe_offset = 0;\r
- uint8_t phase5_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase6_led_drv2_cha_sel = 0;\r
- uint8_t phase6_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase6_ldr2_cur = 0;\r
-// uint8_t phase6_of_idac1_cur = 0;\r
-// uint8_t phase6_of_idac2_cur = 0;\r
- uint8_t phase6_ad_inr_ctrl = 3;\r
- uint8_t phase6_ad_of_idac_ctrl = 0;\r
-// uint8_t phase6_afe_offset = 0;\r
- uint8_t phase6_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase7_led_drv2_cha_sel = 0;\r
- uint8_t phase7_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase7_ldr2_cur = 0;\r
-// uint8_t phase7_of_idac1_cur = 0;\r
-// uint8_t phase7_of_idac2_cur = 0;\r
- uint8_t phase7_ad_inr_ctrl = 3;\r
- uint8_t phase7_ad_of_idac_ctrl = 0;\r
-// uint8_t phase7_afe_offset = 0;\r
- uint8_t phase7_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase8_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase8_led_drv2_cha_sel = 0;\r
- uint8_t phase8_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase8_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase8_ldr2_cur = 0;\r
-// uint8_t phase8_of_idac1_cur = 0;\r
-// uint8_t phase8_of_idac2_cur = 0;\r
- uint8_t phase8_ad_inr_ctrl = 3;\r
- uint8_t phase8_ad_of_idac_ctrl = 0;\r
-// uint8_t phase8_afe_offset = 0;\r
- uint8_t phase8_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ;\r
- 4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ \r
- \r
- uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ;\r
- 4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */\r
- \r
- uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/\r
- \r
- uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ \r
- \r
- uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ \r
- \r
- uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ;\r
- 4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */\r
- \r
- hx3695_delay_ms(10); \r
- \r
- hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6\r
- hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8>\r
- hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> \r
- \r
- hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); \r
- hx3695_write_reg(0X2d, phase7_8_internal); \r
- hx3695_write_reg(0X2e, 0x33);// gpio ctrl \r
- hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay));\r
- hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
- hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
-\r
-\r
- hx3695_write_reg(0X31, (led_on_time<<4| 0x00));\r
- hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置；\r
- hx3695_write_reg(0X34, 0x00);// 中断特殊配置；\r
- hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置；\r
- hx3695_write_reg(0X38, 0x00);\r
- \r
- hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); \r
- hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); \r
- hx3695_write_reg(0X3c, (phase5_inner_avg | (phase6_inner_avg<<4))); \r
- hx3695_write_reg(0X3d, (phase7_inner_avg | (phase8_inner_avg<<4))); \r
- hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); \r
- hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num );\r
- \r
- hx3695_write_reg(0X43, phase1_mux_sel); \r
- hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); \r
- hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase1_als_offset_idac);\r
- hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4);\r
-\r
- \r
- hx3695_write_reg(0X43, phase2_mux_sel); \r
- hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); \r
- hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase2_als_offset_idac);\r
- hx3695_write_reg(0X48, phase2_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4);\r
- \r
-//phase3 sel\r
-\r
- hx3695_write_reg(0X43, phase3_mux_sel); \r
- hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); \r
- hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase3_als_offset_idac);\r
- hx3695_write_reg(0X48, phase3_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4);\r
- \r
-//phase4 sel\r
-\r
- hx3695_write_reg(0X43, phase4_mux_sel); \r
- hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); \r
- hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase4_als_offset_idac);\r
- hx3695_write_reg(0X48, phase4_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4);\r
-\r
- hx3695_write_reg(0X43, phase5_mux_sel); \r
- hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); \r
- hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase5_als_offset_idac);\r
- hx3695_write_reg(0X48, phase5_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase6_mux_sel); \r
- hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); \r
- hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase6_als_offset_idac);\r
- hx3695_write_reg(0X48, phase6_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase6_led_offset_idac);\r
- hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase7_mux_sel); \r
- hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); \r
- hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase7_als_offset_idac);\r
- hx3695_write_reg(0X48, phase7_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase7_led_offset_idac);\r
- hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase8_mux_sel); \r
- hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); \r
- hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase8_als_offset_idac);\r
- hx3695_write_reg(0X48, phase8_led_offset_idac);\r
-// hx3695_write_reg(0X48, phas8_led_offset_idac);\r
- hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4);\r
- \r
-\r
-// analog circuit cfg \r
- hx3695_write_reg(0X60, 0x14); //\r
- hx3695_write_reg(0X61, 0xf0); \r
- hx3695_write_reg(0X62, 0x22); \r
- hx3695_write_reg(0X63, 0x15); \r
- \r
- hx3695_write_reg(0X64, 0x08); \r
- hx3695_write_reg(0X65, 0x88); //bug\r
- \r
- hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30\r
- hx3695_write_reg(0X67, 0x23); \r
- hx3695_write_reg(0X68, 0x46); \r
- hx3695_write_reg(0X69, 0x42); \r
- \r
- hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg\r
- hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable\r
- \r
- hx3695_write_reg(0X6a, 0X0f); \r
- hx3695_write_reg(0X6b, 0X22); \r
- hx3695_write_reg(0X6c, 0X00); \r
- hx3695_write_reg(0X6d, 0X37); \r
- hx3695_write_reg(0X6e, 0X82); \r
- hx3695_write_reg(0X6f, 0X00);\r
-/////////FIFO and adc conversion ready config////////\r
-/////////FIFO and adc conversion ready config////////\r
-#if defined(PPG_INT_MODE)\r
- hx3695_write_reg(0X1b, 0x00);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X38, 0x08); // int sel,00=close almost full int,04=enable almost full int\r
-#elif defined(INT_MODE) //(FIFO_ALL_MOST_FULL)\r
- hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
- hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark\r
- hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] \r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
-\r
-#else\r
- hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble \r
- hx3695_write_reg(0X36, 0x00); \r
- \r
- hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int\r
-\r
-#endif\r
-\r
- \r
- hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); \r
- hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); \r
- hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) );\r
- hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); \r
-\r
- hx3695_write_reg(0X5c, 0x02);//soft reset\r
- hx3695_delay_ms(5); \r
- hx3695_write_reg(0X5c, 0x00);//release\r
-// uint8_t fifo_data_temp[3] = {0};\r
-// hx3695_brust_read_reg(0x22, fifo_data_temp, 3); \r
- read_fifo_first_flg = 1;\r
- return ;\r
-}\r
-#endif\r
-\r
-#ifdef CHECK_TOUCH_LIB\r
-void hx3695_check_touch_init(void) //\r
-{ \r
- uint16_t sample_rate = 5; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
- uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */\r
- \r
- uint16_t fifo_watermark= 250 ;\r
- uint8_t adc_rst_post_num= 0; /* 00=16,01=32,10=64,11=128*/ \r
- uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
- uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/\r
- uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/\r
- uint8_t phase7_8_internal = 0; //0x18; /* phase7 and phase8 prf internal cfg */\r
- \r
-// uint16_t thred_value = 32500;\r
- \r
- uint8_t phase1_enable = 0; /*phase1_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase2_enable = 0; /*phase2_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase3_enable = 0; /*phase3_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase4_enable = 0; /*phase4_enable , 1 mean enable ; 0 mean disable */\r
- uint8_t phase5_enable = 0; /*phase5_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase6_enable = 0; /*phase6_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase7_enable = 1; /*phase7_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ \r
-\r
- uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- \r
- uint8_t phase1_mux_sel = 0; /* sel phase1*/\r
- uint8_t phase2_mux_sel = 1; /* sel phase2*/\r
- uint8_t phase3_mux_sel = 2; /* sel phase3*/\r
- uint8_t phase4_mux_sel = 3; /* sel phase4*/\r
- uint8_t phase5_mux_sel = 4; /* sel phase5*/\r
- uint8_t phase6_mux_sel = 5; /* sel phase6*/\r
- uint8_t phase7_mux_sel = 6; /* sel phase7*/\r
- uint8_t phase8_mux_sel = 7; /* sel phase8*/\r
- \r
-\r
- uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase1_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */\r
- uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */\r
- uint8_t phase1_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase1_ldr2_cur = 0;\r
-// uint8_t phase1_of_idac1_cur = 0;\r
-// uint8_t phase1_of_idac2_cur = 0;\r
- uint8_t phase1_ad_inr_ctrl = 3;\r
- uint8_t phase1_ad_of_idac_ctrl = 0;\r
-// uint8_t afe_offset = 0;\r
- uint8_t phase1_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
-\r
-\r
- uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase2_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase2_led_drv1_cha_sel = 0; //GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase2_led_drv2_cha_sel = 0;\r
- uint8_t phase2_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase2_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase2_ldr2_cur = 0;\r
-// uint8_t phase2_of_idac1_cur = 0;\r
-// uint8_t phase2_of_idac2_cur = 0;\r
- uint8_t phase2_ad_inr_ctrl = 3;\r
- uint8_t phase2_ad_of_idac_ctrl = 0;\r
-// uint8_t phase2_afe_offset = 0;\r
- uint8_t phase2_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- \r
- uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase3_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase3_led_drv1_cha_sel = 0; //RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase3_led_drv2_cha_sel = 0;\r
- uint8_t phase3_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase3_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase3_ldr2_cur = 0;\r
-// uint8_t phase3_of_idac1_cur = 0;\r
-// uint8_t phase3_of_idac2_cur = 0;\r
- uint8_t phase3_ad_inr_ctrl = 3;\r
- uint8_t phase3_ad_of_idac_ctrl = 0;\r
-// uint8_t phase3_afe_offset = 0;\r
- uint8_t phase3_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- \r
- uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase4_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase4_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase4_led_drv2_cha_sel = 0;\r
- uint8_t phase4_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase4_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase4_ldr2_cur = 0;\r
-// uint8_t phase4_of_idac1_cur = 0;\r
-// uint8_t phase4_of_idac2_cur = 0;\r
- uint8_t phase4_ad_inr_ctrl = 3;\r
- uint8_t phase4_ad_of_idac_ctrl = 0;\r
-// uint8_t phase4_afe_offset = 0;\r
- uint8_t phase4_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase5_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase5_led_drv2_cha_sel = 0;\r
- uint8_t phase5_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase5_ldr2_cur = 0;\r
-// uint8_t phase5_of_idac1_cur = 0;\r
-// uint8_t phase5_of_idac2_cur = 0;\r
- uint8_t phase5_ad_inr_ctrl = 3;\r
- uint8_t phase5_ad_of_idac_ctrl = 0;\r
-// uint8_t phase5_afe_offset = 0;\r
- uint8_t phase5_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase6_tia_cap = SPO2_PD; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase6_led_drv2_cha_sel = 0;\r
- uint8_t phase6_pd_sel = 4; /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase6_ldr2_cur = 0;\r
-// uint8_t phase6_of_idac1_cur = 0;\r
-// uint8_t phase6_of_idac2_cur = 0;\r
- uint8_t phase6_ad_inr_ctrl = 3;\r
- uint8_t phase6_ad_of_idac_ctrl = 0;\r
-// uint8_t phase6_afe_offset = 0;\r
- uint8_t phase6_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase7_led_drv2_cha_sel = 0;\r
- uint8_t phase7_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase7_ldr2_cur = 0;\r
-// uint8_t phase7_of_idac1_cur = 0;\r
-// uint8_t phase7_of_idac2_cur = 0;\r
- uint8_t phase7_ad_inr_ctrl = 3;\r
- uint8_t phase7_ad_of_idac_ctrl = 0;\r
-// uint8_t phase7_afe_offset = 0;\r
- uint8_t phase7_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase8_led_drv1_cha_sel = IR_LED_SLE;//0x40; //IR_LED_SLE /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase8_led_drv2_cha_sel = 0;\r
- uint8_t phase8_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase8_ldr1_cur = 32; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase8_ldr2_cur = 0;\r
-// uint8_t phase8_of_idac1_cur = 0;\r
-// uint8_t phase8_of_idac2_cur = 0;\r
- uint8_t phase8_ad_inr_ctrl = 3;\r
- uint8_t phase8_ad_of_idac_ctrl = 0;\r
-// uint8_t phase8_afe_offset = 0;\r
- uint8_t phase8_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ;\r
- 4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ \r
- \r
- uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ;\r
- 4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */\r
- \r
- uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/\r
- \r
- uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ \r
- \r
- uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ \r
- \r
- uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ;\r
- 4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */\r
- \r
- hx3695_delay_ms(10); \r
- \r
- hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6\r
- hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8>\r
- hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> \r
- \r
- hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); \r
- hx3695_write_reg(0X2d, phase7_8_internal); \r
- hx3695_write_reg(0X2e, 0x33);// gpio ctrl \r
- hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay));\r
- hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
- hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
-\r
-\r
- hx3695_write_reg(0X31, (led_on_time<<4| 0x00));\r
- hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置；\r
- hx3695_write_reg(0X34, 0x00);// 中断特殊配置；\r
- hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置；\r
- hx3695_write_reg(0X38, 0x00);\r
- \r
- hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); \r
- hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); \r
- hx3695_write_reg(0X3c, (phase5_inner_avg | (phase6_inner_avg<<4))); \r
- hx3695_write_reg(0X3d, (phase7_inner_avg | (phase8_inner_avg<<4))); \r
- hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); \r
- hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num );\r
- \r
- hx3695_write_reg(0X43, phase1_mux_sel); \r
- hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); \r
- hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase1_als_offset_idac);\r
- hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4);\r
-\r
- \r
- hx3695_write_reg(0X43, phase2_mux_sel); \r
- hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); \r
- hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase2_als_offset_idac);\r
- hx3695_write_reg(0X48, phase2_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4);\r
- \r
-//phase3 sel\r
-\r
- hx3695_write_reg(0X43, phase3_mux_sel); \r
- hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); \r
- hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase3_als_offset_idac);\r
- hx3695_write_reg(0X48, phase3_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4);\r
- \r
-//phase4 sel\r
-\r
- hx3695_write_reg(0X43, phase4_mux_sel); \r
- hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); \r
- hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase4_als_offset_idac);\r
- hx3695_write_reg(0X48, phase4_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4);\r
-\r
- hx3695_write_reg(0X43, phase5_mux_sel); \r
- hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); \r
- hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase5_als_offset_idac);\r
- hx3695_write_reg(0X48, phase5_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase6_mux_sel); \r
- hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); \r
- hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase6_als_offset_idac);\r
- hx3695_write_reg(0X48, phase6_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase6_led_offset_idac);\r
- hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase7_mux_sel); \r
- hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); \r
- hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase7_als_offset_idac);\r
- hx3695_write_reg(0X48, phase7_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase7_led_offset_idac);\r
- hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase8_mux_sel); \r
- hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); \r
- hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase8_als_offset_idac);\r
- hx3695_write_reg(0X48, phase8_led_offset_idac);\r
-// hx3695_write_reg(0X48, phas8_led_offset_idac);\r
- hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4);\r
- \r
-\r
-// analog circuit cfg \r
- hx3695_write_reg(0X60, 0x14); //\r
- hx3695_write_reg(0X61, 0xf0); \r
- hx3695_write_reg(0X62, 0x22); \r
- hx3695_write_reg(0X63, 0x15); \r
- \r
- hx3695_write_reg(0X64, 0x08); \r
- hx3695_write_reg(0X65, 0x88); //bug\r
- \r
- hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30\r
- hx3695_write_reg(0X67, 0x23); \r
- hx3695_write_reg(0X68, 0x46); \r
- hx3695_write_reg(0X69, 0x42); \r
- \r
- hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg\r
- hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable\r
- \r
- hx3695_write_reg(0X6a, 0X0f); \r
- hx3695_write_reg(0X6b, 0X22); \r
- hx3695_write_reg(0X6c, 0X00); \r
- hx3695_write_reg(0X6d, 0X37); \r
- hx3695_write_reg(0X6e, 0X82); \r
- hx3695_write_reg(0X6f, 0X00);\r
-/////////FIFO and adc conversion ready config////////\r
-/////////FIFO and adc conversion ready config////////\r
-#if defined(PPG_INT_MODE)\r
- hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int\r
-#elif defined(INT_MODE) //(FIFO_ALL_MOST_FULL)\r
- hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
- hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark\r
- hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] \r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
-\r
-#else\r
- hx3695_write_reg(0X1b, 0x92);\r
-\r
- hx3695_write_reg(0X36, 0x00); \r
- \r
- hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int\r
-\r
-#endif\r
-\r
- \r
- hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); \r
- hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); \r
- hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) );\r
- hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); \r
-\r
- hx3695_write_reg(0X5c, 0x02);//soft reset\r
- hx3695_delay_ms(5); \r
- hx3695_write_reg(0X5c, 0x00);//release\r
-// uint8_t fifo_data_temp[3] = {0};\r
-// hx3695_brust_read_reg(0x22, fifo_data_temp, 3); \r
- read_fifo_first_flg = 1;\r
- return ;\r
-}\r
-#endif\r
-\r
-// 初始化调用入口函数\r
-bool hx3695_init(WORK_MODE_T mode)\r
-{\r
- // hx3695_msg_callback_t func;\r
-\r
-\r
- //TYHX_LOG("this chip hx3695_init mode: %d !! \r\n", mode);\r
- \r
- hx3695_ppg_on();\r
-\r
- Efuse_judge(); //MC前后芯片判断\r
- // Efuse_Mode_Check();\r
- work_mode_flag = mode;\r
- hx3695_data_reset();\r
- hx3695_vin_check(3800);\r
- switch (work_mode_flag)\r
- {\r
- case HRS_MODE:\r
- //TYHX_LOG(" hx3695_init mode : HRS_MODE \n");\r
-#ifdef HRS_ALG_LIB\r
- tyhx_hrs_set_living(1, 15, 30);\r
- if(hx3695_hrs_enable()== SENSOR_OP_FAILED)\r
- {\r
- return false;\r
- }\r
-#endif\r
- break;\r
-\r
- case LIVING_MODE:\r
-#ifdef CHECK_LIVING_LIB\r
- if(hx3695_hrs_enable()== SENSOR_OP_FAILED)\r
- {\r
- return false;\r
- }\r
-#endif\r
- break;\r
-\r
- case SPO2_MODE:\r
-#ifdef SPO2_DATA_CALI\r
-// hx3695_spo2_data_cali_init();\r
-#endif\r
-\r
-#ifdef SPO2_ALG_LIB\r
- tyhx_spo2_para_usuallyadjust(SPO2_LOW_XCORR_THRE,SPO2_LOW_SNR_THRE,COUNT_BLOCK_NUM,SPO2_BASE_LINE_INIT,SPO2_SLOPE,SPO2_GSEN_POW_THRE);\r
- tyhx_spo2_para_barelychange(MEAN_NUM,SOP2_DEGLITCH_THRE,SPO2_REMOVE_JUMP_THRE, \\r
- SPO2_LOW_CLIP_END_TIME,SPO2_LOW_CLIP_DN,SPO2_NORMAL_CLIP_DN, \\r
- IR_AC_TOUCH_THRE,IR_FFT_POW_THRE,SPO2_CALI,SLOPE_PARA_MAX,SLOPE_PARA_MIN);\r
- tyhx_spo2_set_living(1, 7, 20);\r
- if(hx3695_spo2_enable()== SENSOR_OP_FAILED)\r
- {\r
- return false;\r
- }\r
-#endif\r
- break;\r
-\r
- case HRSPO2_MODE:\r
-#if defined(HRS_ALG_LIB) && defined (SPO2_ALG_LIB)\r
- tyhx_spo2_para_usuallyadjust(SPO2_LOW_XCORR_THRE,SPO2_LOW_SNR_THRE,COUNT_BLOCK_NUM,SPO2_BASE_LINE_INIT,SPO2_SLOPE,SPO2_GSEN_POW_THRE);\r
- tyhx_spo2_para_barelychange(MEAN_NUM,SOP2_DEGLITCH_THRE,SPO2_REMOVE_JUMP_THRE, \\r
- SPO2_LOW_CLIP_END_TIME,SPO2_LOW_CLIP_DN,SPO2_NORMAL_CLIP_DN, \\r
- IR_AC_TOUCH_THRE,IR_FFT_POW_THRE,SPO2_CALI,SLOPE_PARA_MAX,SLOPE_PARA_MIN);\r
- if(hx3695_spo2_enable()== SENSOR_OP_FAILED)\r
- {\r
- return false;\r
- }\r
-#endif\r
-\r
- case HRV_MODE:\r
-#ifdef HRV_ALG_LIB\r
- if(hx3695_hrv_enable()== SENSOR_OP_FAILED)\r
- {\r
- return false;\r
- }\r
-#endif\r
- break;\r
-\r
- case WEAR_MODE:\r
-#ifdef CHECK_TOUCH_LIB\r
- if(hx3695_check_touch_enable()== SENSOR_OP_FAILED)\r
- {\r
- return false;\r
- }\r
-#endif\r
- break;\r
-\r
- case FT_LEAK_LIGHT_MODE:\r
- if (!hx3695_chip_check())\r
- {\r
- AGC_LOG("hx3695 check id failed!\r\n");\r
- return false;\r
- }\r
- //TYHX_LOG(" hx3695_init mode : LEAK_LIGHT_MODE \n");\r
- hx3695_factroy_test(LEAK_LIGHT_TEST);\r
-\r
- // func = hx3695_get_send_msg_callback_func();\r
- // if(func != NULL)\r
- // {\r
- // func(HX3695_MSG_TYPE_LEAKLIGHT_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t));\r
- // }\r
- break;\r
-\r
- case FT_GRAY_CARD_MODE:\r
- if (!hx3695_chip_check())\r
- {\r
- AGC_LOG("hx3695 check id failed!\r\n");\r
- return false;\r
- }\r
- //TYHX_LOG(" hx3695_init mode : GRAY_CARD_MODE \n");\r
- hx3695_factroy_test(GRAY_CARD_TEST);\r
-\r
- // func = hx3695_get_send_msg_callback_func();\r
- // if(func != NULL)\r
- // {\r
- // func(HX3695_MSG_TYPE_GRAYCARD_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t));\r
- // }\r
- break;\r
-\r
- case FT_INT_TEST_MODE:\r
- hx3695_factroy_test(FT_INT_TEST);\r
- break;\r
-\r
- case FT_SINGLE_CHECK_MODE:\r
- if (!hx3695_chip_check())\r
- {\r
- AGC_LOG("hx3695 check id failed!\r\n");\r
- return false;\r
- }\r
- hx3695_factroy_test(SINGLE_CHECK_TEST);\r
- break;\r
-\r
- case FT_LED_OFF_MODE:\r
- //TYHX_LOG(" hx3695_init mode : FT_LED_OFF_MODE \n");\r
- hx3695_factroy_test(LED_OFF_TEST);\r
- break;\r
- \r
- case FT_WEAR_MODE:\r
- hx3695_factroy_test(WEAR_MODE_TEST);\r
- break;\r
- // case NEW_PPG_TEST_MODE:\r
- // hx3695_factroy_test(NEW_PPG_TEST);\r
- // break;\r
- case LAB_TEST_MODE:\r
-#ifdef LAB_TEST\r
- if(hx3695_lab_test_enable()== SENSOR_OP_FAILED)\r
- {\r
- return false;\r
- }\r
-#endif\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
- return true;\r
-}\r
-\r
-void hx3695_agc_Int_handle(void)\r
-{\r
- //TYHX_LOG(" hx3695_init mode : HRS_MODE \n");\r
- switch (work_mode_flag)\r
- {\r
- case HRS_MODE:\r
-#ifdef HRS_ALG_LIB\r
- PPG_hrs_agc();\r
-#endif\r
- break;\r
-\r
- case LIVING_MODE:\r
-#ifdef HRS_ALG_LIB\r
- PPG_hrs_agc();\r
-#endif\r
- break;\r
-\r
- case HRV_MODE:\r
-#ifdef HRV_ALG_LIB\r
- PPG_hrv_agc();\r
-#endif\r
- break;\r
-\r
- case SPO2_MODE:\r
-#ifdef SPO2_ALG_LIB\r
- PPG_spo2_agc();\r
-#endif\r
- break;\r
-\r
- case HRSPO2_MODE:\r
-#if defined(HRS_ALG_LIB) && defined (SPO2_ALG_LIB)\r
- PPG_spo2_agc();\r
-#endif\r
-\r
- case LAB_TEST_MODE:\r
-#ifdef LAB_TEST\r
- hx3695_lab_test_Int_handle();\r
-#endif\r
-\r
- default:\r
- break;\r
- }\r
-}\r
-\r
-void agc_timeout_handler(void * p_context)\r
-{\r
- hx3695_agc_Int_handle();\r
-\r
-#if defined(GSEN_40MS_TIMMER)\r
- hx3695_gesensor_Int_handle();\r
-#endif\r
-}\r
-\r
-static uint32_t ft_ppg_green = 0;\r
-static uint32_t ft_ppg_iir = 0;\r
-\r
-void hx3695_factory_test_process(uint8_t data[], uint8_t mode, uint8_t* ppg_src)\r
-{\r
- extern bool factory_test_flag;\r
- extern bool factory_test_sensor_on;\r
- extern bool factory_test_aging;\r
- \r
- if(factory_test_flag == false) return;\r
- if(factory_test_sensor_on == true ) return;\r
- \r
- static uint8_t ppg_data[15] = {0};\r
- uint32_t test = 0;\r
-// uint32_t green = 0;\r
-// uint32_t red = 0;\r
-// uint32_t iir = 0;\r
-\r
- if(data != NULL && ppg_src == NULL)\r
- {\r
- memcpy(ppg_data, data, 3);\r
- return;\r
- }\r
-// switch(mode)\r
-// {\r
-// case APP_FACTORY_TEST_HR_START:\r
-// ppg_data[3] = *(ppg_src + 3);\r
-// ppg_data[4] = *(ppg_src + 2);\r
-// ppg_data[5] = *(ppg_src + 1);\r
-// ppg_data[6] = *(ppg_src + 0);\r
- \r
-// ppg_data[7] = *(ppg_src + 7);\r
-// ppg_data[8] = *(ppg_src + 6);\r
-// ppg_data[9] = *(ppg_src + 5);\r
-// ppg_data[10] = *(ppg_src + 4);\r
-\r
-// ppg_data[11] = *(ppg_src + 11);\r
-// ppg_data[12] = *(ppg_src + 10);\r
-// ppg_data[13] = *(ppg_src + 9);\r
-// ppg_data[14] = *(ppg_src + 8);\r
- \r
-// factory_test_send_data(ppg_data, 15);\r
-// break;\r
-// case APP_FACTORY_TEST_SPO2_START:\r
-// ppg_data[3] = *(ppg_src + 3);\r
-// ppg_data[4] = *(ppg_src + 2);\r
-// ppg_data[5] = *(ppg_src + 1);\r
-// ppg_data[6] = *(ppg_src + 0);\r
- \r
-// ppg_data[7] = *(ppg_src + 7);\r
-// ppg_data[8] = *(ppg_src + 6);\r
-// ppg_data[9] = *(ppg_src + 5);\r
-// ppg_data[10] = *(ppg_src + 4);\r
-\r
-// ppg_data[11] = *(ppg_src + 11);\r
-// ppg_data[12] = *(ppg_src + 10);\r
-// ppg_data[13] = *(ppg_src + 9);\r
-// ppg_data[14] = *(ppg_src + 8); \r
-\r
-// factory_test_send_data(ppg_data, 15);\r
-// break;\r
-// case APP_FACTORY_TEST_LEAKING_START:\r
-// // memcpy((void *)&ppg_data[3], ppg_src, 12);\r
-\r
-// ppg_data[3] = *(ppg_src + 3);\r
-// ppg_data[4] = *(ppg_src + 2);\r
-// ppg_data[5] = *(ppg_src + 1);\r
-// ppg_data[6] = *(ppg_src + 0);\r
- \r
-// ppg_data[7] = *(ppg_src + 7);\r
-// ppg_data[8] = *(ppg_src + 6);\r
-// ppg_data[9] = *(ppg_src + 5);\r
-// ppg_data[10] = *(ppg_src + 4);\r
-\r
-// ppg_data[11] = *(ppg_src + 11);\r
-// ppg_data[12] = *(ppg_src + 10);\r
-// ppg_data[13] = *(ppg_src + 9);\r
-// ppg_data[14] = *(ppg_src + 8);\r
-\r
-\r
-// gui_send_message_by_data(MSG_FACTORY_TEST_UPDATE_HR, ppg_src, 12);\r
-// if(factory_test_aging) break;\r
-// factory_test_send_data(ppg_data, 15);\r
-// break;\r
-// case APP_FACTORY_TEST_GRAY_CARD:\r
-// {\r
-// // memcpy((void *)&ppg_data[3], ppg_src, 12);\r
-// ppg_data[3] = *(ppg_src + 3);\r
-// ppg_data[4] = *(ppg_src + 2);\r
-// ppg_data[5] = *(ppg_src + 1);\r
-// ppg_data[6] = *(ppg_src + 0);\r
- \r
-// ppg_data[7] = *(ppg_src + 7);\r
-// ppg_data[8] = *(ppg_src + 6);\r
-// ppg_data[9] = *(ppg_src + 5);\r
-// ppg_data[10] = *(ppg_src + 4);\r
-\r
-// ppg_data[11] = *(ppg_src + 11);\r
-// ppg_data[12] = *(ppg_src + 10);\r
-// ppg_data[13] = *(ppg_src + 9);\r
-// ppg_data[14] = *(ppg_src + 8);\r
- \r
-// gui_send_message_by_data(MSG_FACTORY_TEST_UPDATE_HR, ppg_src, 12);\r
-// if(factory_test_aging) break;\r
-// factory_test_send_data(ppg_data, 15);\r
-// } \r
-// break;\r
-// default:\r
-// break;\r
-// }\r
-}\r
-\r
-\r
-typedef struct { \r
- int32_t gr_data_final;\r
- int32_t red_data_final;\r
- int32_t ir_data_final;\r
-} ft_test_result_t;\r
-\r
-void wear_mode_timeout_handler(void * p_context)\r
-{\r
- if(work_mode_flag == WEAR_MODE)\r
- {\r
- #ifdef CHECK_TOUCH_LIB\r
- hx3695_wear_ppg_Int_handle(); \r
- #endif\r
- }\r
-}\r
-\r
-\r
-void heart_rate_meas_timeout_handler(void * p_context)\r
-{\r
- //TYHX_LOG(" heart_rate_meas_timeout_handler mode: %d \n", work_mode_flag);\r
- \r
- switch(work_mode_flag)\r
- {\r
- case HRS_MODE:\r
-#ifdef HRS_ALG_LIB\r
- hx3695_hrs_ppg_Int_handle();\r
-#endif\r
- break;\r
-\r
- case HRV_MODE:\r
-#ifdef HRV_ALG_LIB\r
- hx3695_hrv_ppg_Int_handle();\r
-#endif\r
- break;\r
-\r
- case SPO2_MODE:\r
-#ifdef SPO2_ALG_LIB\r
- hx3695_spo2_ppg_Int_handle();\r
-#endif\r
- break;\r
-\r
- case LIVING_MODE:\r
-#ifdef CHECK_LIVING_LIB\r
- hx3695_living_Int_handle();\r
-#endif\r
- break;\r
-\r
- case HRSPO2_MODE:\r
-#if defined(HRS_ALG_LIB) && defined (SPO2_ALG_LIB)\r
- hx3695_hrspo2_ppg_Int_handle();\r
-#endif\r
-\r
- case FT_LEAK_LIGHT_MODE:\r
- {\r
- hx3695_factroy_test(LEAK_LIGHT_TEST);\r
- break;\r
- }\r
- break;\r
- \r
- case FT_GRAY_CARD_MODE:\r
- {\r
- FT_RESULTS_t ft_result = hx3695_factroy_test(GRAY_CARD_TEST);\r
- uint8_t data[12] = {0};\r
- memcpy(data, (void *)&ft_result.gr_data_final, 12);\r
- \r
- // hx3695_factory_test_process(NULL, APP_FACTORY_TEST_GRAY_CARD, data);\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-}\r
-\r
-void hx3695_ppg_Int_handle(void)\r
-{\r
- hx3695_agc_Int_handle();\r
-#if defined(INT_MODE)\r
- switch(work_mode_flag)\r
- {\r
- case HRS_MODE:\r
-#ifdef HRS_ALG_LIB\r
- hx3695_hrs_ppg_Int_handle();\r
-#endif\r
- break;\r
-\r
- case SPO2_MODE:\r
-#ifdef SPO2_ALG_LIB\r
- hx3695_spo2_ppg_Int_handle();\r
-#endif\r
- break;\r
-\r
- case HRV_MODE:\r
-#ifdef HRV_ALG_LIB\r
- hx3695_hrv_ppg_Int_handle();\r
-#endif\r
- break;\r
-\r
- case WEAR_MODE:\r
-#ifdef CHECK_TOUCH_LIB\r
- hx3695_wear_ppg_Int_handle();\r
-#endif\r
- break;\r
-\r
- case LAB_TEST_MODE:\r
-#ifdef LAB_TEST\r
- hx3695_lab_test_Int_handle();\r
-#endif\r
-\r
- default:\r
- break;\r
- }\r
-#endif\r
-}\r
-\r
-#define HRS_WINDOW_SIZE 5\r
-static uint8_t hrs_num = 0;\r
-static int32_t sum_hrs = 0;\r
-static int32_t hrs_data[7] = {0};\r
-static uint8_t left = 0;\r
-static uint8_t right = 0;\r
-static uint8_t avg_hrs = 0;\r
-\r
-static void get_avg_hrs(uint8_t hrs)\r
-{\r
-\r
-\r
- if (hrs_num >= HRS_WINDOW_SIZE) {\r
- sum_hrs -= hrs_data[left];\r
- left = (left + 1) % HRS_WINDOW_SIZE;\r
- hrs_num--;\r
- }\r
-\r
- hrs_data[right] = hrs;\r
- sum_hrs += hrs;\r
- right = (right + 1) % HRS_WINDOW_SIZE;\r
- hrs_num++;\r
-\r
-\r
- if (hrs_num > 2) \r
- {\r
-\r
- uint8_t first_idx = left;\r
- int32_t min_hrs = hrs_data[first_idx];\r
- int32_t max_hrs = hrs_data[first_idx];\r
-\r
-\r
- for (uint8_t i = 0; i < hrs_num; i++) {\r
- uint8_t current_idx = (left + i) % HRS_WINDOW_SIZE;\r
- uint8_t current_hrs = hrs_data[current_idx];\r
-\r
- if (current_hrs < min_hrs) {\r
- min_hrs = current_hrs;\r
- }\r
- if (current_hrs > max_hrs) {\r
- max_hrs = current_hrs;\r
- }\r
- }\r
-\r
- uint8_t valid_count = hrs_num - 2;\r
- avg_hrs = (sum_hrs - max_hrs - min_hrs) / valid_count;\r
-\r
- // printf("max_hrs[%d],min_hrs[%d],avg_hrs[%d]\n",max_hrs,min_hrs,avg_hrs);\r
- }\r
-}\r
-\r
-\r
-uint8_t hx3695_get_hrs(void)\r
-{\r
- return avg_hrs;\r
-}\r
-\r
-uint8_t hx3695_get_spo2(void)\r
-{\r
- return spo2_result;\r
-}\r
-\r
-\r
-uint8_t hx3695_get_wear_status(void)\r
+void hx3695_set_watermark(ppg_sensor_data_t *ppg_sensor_dat)\r
{\r
- return wear_status;\r
+ uint8_t watermark = ppg_sensor_dat->watermark + ppg_sensor_dat->led_activated;\r
+ hx3695_write_reg(0X1c, watermark);\r
+ hx3695_write_reg(0X5c, 0x02);\r
+ hx3695_delay_ms(1);\r
+ hx3695_write_reg(0X1b, 0x10);\r
+ hx3695_delay_ms(1);\r
+ hx3695_write_reg(0X1b, 0x91);\r
+ hx3695_write_reg(0X5c, 0x00);\r
+ read_fifo_first_flg = 1;\r
}\r
\r
-void hx3695_set_hrs_ble_swtich(uint8_t cmd)\r
+void hx3695_led_control(ppg_sensor_data_t *ppg_sensor_dat, uint8_t index)\r
{\r
- hrs_ble_falg = cmd;\r
- // PRINT("hrs_ble_falg : %d \n",hrs_ble_falg);\r
+ if(ppg_sensor_dat->led_data[index].led_state == Activating)\r
+ {\r
+ hx3695_write_reg(0X26+index,0xbb);\r
+ ppg_sensor_dat->led_data[index].led_state = Activated;\r
+ }\r
+ else if(ppg_sensor_dat->led_data[index].led_state == InActivating)\r
+ {\r
+ hx3695_write_reg(0X26+index,0x33);\r
+ ppg_sensor_dat->led_data[index].led_state = InActivated;\r
+ }\r
}\r
\r
-uint8_t hx3695_get_hrs_ble_swtich(void)\r
+void hx3695_updata_sensor(ppg_sensor_data_t *ppg_sensor_dat)\r
{\r
- uint8_t cmd = hrs_ble_falg;\r
- return cmd;\r
+ uint8_t ii;\r
+ hx3695_set_fs(ppg_sensor_dat);\r
+ for(ii=0;ii<4;ii++)\r
+ {\r
+ hx3695_led_control(ppg_sensor_dat, ii);\r
+ }\r
+ hx3695_set_watermark(ppg_sensor_dat);\r
}\r
\r
-void hx3695_wearstatus_update(void)\r
+void hx3695_hrs_enable(ppg_sensor_data_t *ppg_sensor_dat)\r
{\r
- if(history_wear_status != wear_status)\r
- {\r
- history_wear_status = wear_status;\r
-#ifdef SUPPORT_CYWEE_SERVICE\r
- // do_cywee_service_check_msg(CYWEE_SERVICE_CMD_WEAR_STATUS_CHANGE,&wear_status);\r
- cywee_wear_status_update(&wear_status);\r
-#endif\r
- }\r
+ printf("hx3695_hrs_enable\r\n");\r
+ tyhx_hrs_alg_open();\r
+ ppg_sensor_data.mode = HRS_MODE;\r
+ hx3695_ppg_set_mode(PPG_INIT);\r
+ #ifdef DOUBLE_GREEN\r
+ ppg_sensor_dat->led_activated = 3;\r
+ ppg_sensor_dat->fs = 25;\r
+ ppg_sensor_dat->watermark = 30;\r
+ ppg_sensor_dat->led_data[0].led_state = Activating;\r
+ ppg_sensor_dat->led_data[1].led_state = Activating;\r
+ ppg_sensor_dat->led_data[2].led_state = InActivating;\r
+ ppg_sensor_dat->led_data[3].led_state = Activating;\r
+ ppg_sensor_dat->led_data[0].isneed_cal_start = true;\r
+ ppg_sensor_dat->led_data[1].isneed_cal_start = true;\r
+ ppg_sensor_dat->led_data[2].isneed_cal_start = false;\r
+ ppg_sensor_dat->led_data[3].isneed_cal_start = false;\r
+ #else\r
+ ppg_sensor_dat->led_activated = 2;\r
+ ppg_sensor_dat->fs = 25;\r
+ ppg_sensor_dat->watermark = 20;\r
+ ppg_sensor_dat->led_data[0].led_state = Activating;\r
+ ppg_sensor_dat->led_data[1].led_state = InActivating;\r
+ ppg_sensor_dat->led_data[2].led_state = InActivating;\r
+ ppg_sensor_dat->led_data[3].led_state = Activating;\r
+ ppg_sensor_dat->led_data[0].isneed_cal_start = true;\r
+ ppg_sensor_dat->led_data[1].isneed_cal_start = false;\r
+ ppg_sensor_dat->led_data[2].isneed_cal_start = false;\r
+ ppg_sensor_dat->led_data[3].isneed_cal_start = false;\r
+ #endif\r
+ hx3695_updata_sensor(ppg_sensor_dat);\r
}\r
- //脱腕上报未佩戴信息\r
-void hx3695_unwearstatus_update(void)\r
-{\r
- // hx3695_msg_callback_t func = hx3695_get_send_msg_callback_func();\r
- // if(func != NULL && !uapi_dev_runtime_get_train_status())\r
- // {\r
- // hrsresult.lastesthrs = 0;\r
- // hrsresult.wearstatus = 0;\r
- // //为了主界面脱腕灵敏；需要增加未佩戴\r
- // func(HX3695_MSG_TYPE_HRS_UPDATE, &hrsresult, sizeof(FT_CUSTOM_RESULTS_t));\r
- // func(HX3695_MSG_TYPE_WEARSTAT_UPDATE, &hrsresult,sizeof(FT_CUSTOM_RESULTS_t));\r
- // func(HX3695_MSG_TYPE_WEARSTAT_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t));\r
- // func(HX3695_MSG_TYPE_WEARSTAT_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t));\r
- // }\r
-\r
- if(uapi_dev_runtime_get_train_status())\r
- {\r
- wear_status = 0;\r
- hx3695_wearstatus_update();\r
- avg_hrs = 0;\r
-\r
- }\r
-} \r
-\r
-\r
-#ifdef HRS_ALG_LIB\r
-/*TYHX 心率模式下 读取PPG， 默认320ms*/\r
-hrs_sensor_data_t hrs_s_dat;\r
-//hx3695_results_t alg_results_pre;\r
-\r
-static uint8_t his_wear = 2;\r
-static uint8_t wear_cnt = 0;\r
-// static uint8_t acc_restart_flag = 0;\r
\r
-void hx3695_hrs_ppg_Int_handle(void)\r
+void hx3695_hrsdaily_enable(ppg_sensor_data_t *ppg_sensor_dat)\r
{\r
- uint8_t ii=0;\r
- hrs_results_t alg_results = {MSG_HRS_ALG_NOT_OPEN,0,0,0,0,0,0};\r
- hrs_wear_msg_code_t hrs_wear_status = MSG_HRS_NO_WEAR;\r
- int32_t *PPG_buf = &(hrs_s_dat.green_data[0]);\r
- int32_t *ir_buf = &(hrs_s_dat.ir_data[0]);\r
- uint8_t *count = &(hrs_s_dat.count);\r
- //int32_t *s_buf = &(ppg_s_data.s_buf[0]);\r
- int16_t gsen_fifo_x_send[32]= {0};\r
- int16_t gsen_fifo_y_send[32]= {0};\r
- int16_t gsen_fifo_z_send[32]= {0};\r
- \r
- HRS_CAL_SET_T cal;\r
- cal = get_hrs_agc_status();\r
-\r
-#ifdef HR_VECTOR\r
- for(ii=0; ii<8; ii++)\r
- {\r
- PPG_buf_vec[ii] = hrm_input_data[vec_send_cnt+ii];\r
- gsen_fifo_x_send[ii] = gsen_input_data_x[vec_send_cnt+ii];\r
- gsen_fifo_y_send[ii] = gsen_input_data_y[vec_send_cnt+ii];\r
- gsen_fifo_z_send[ii] = gsen_input_data_z[vec_send_cnt+ii];\r
- }\r
- vec_send_cnt = vec_send_cnt+8;\r
- *count = 8;\r
- tyhx_hrs_alg_send_data(PPG_buf_vec,*count, gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send);\r
-\r
-#else\r
-\r
- if(hx3695_hrs_read(&hrs_s_dat) == 0)\r
- {\r
- return;\r
- }\r
-\r
-#ifndef GSEN_40MS_TIMMER\r
- //readFifoByHrsModule();\r
-#endif\r
-// DEBUG_PRINTF("\r\nsend jlink cnt=%d\r\n",*count); \r
-/* gsensor 屏蔽 */\r
-// for(ii=0; ii<*count; ii++)\r
-// {\r
-// #if 0\r
-// gsen_fifo_x_send[ii] = gsen_fifo_x[32-*count+ii];\r
-// gsen_fifo_y_send[ii] = gsen_fifo_y[32-*count+ii];\r
-// gsen_fifo_z_send[ii] = gsen_fifo_z[32-*count+ii];\r
-\r
-// PRINT("hx3695 gr,ir,gsen:%d/%d %d %d %d %d %d %d\r\n" ,\r
-// 1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x[ii],gsen_fifo_y[ii],gsen_fifo_z[ii],cal.Group1_Cur);\r
-// #else\r
-// accel_data_struct_t accel_raw_data = {0};\r
-// queue_output(&accel_raw_data);\r
-// gsen_fifo_x_send[ii] = accel_raw_data.x;\r
-// gsen_fifo_y_send[ii] = accel_raw_data.y;\r
-// gsen_fifo_z_send[ii] = accel_raw_data.z;\r
-// // PRINT("hx3695 gr,ir,gsen:%d/%d %d %d %d %d %d %d\r\n" ,\r
-// // 1+ii,*count,PPG_buf[ii], ir_buf[0], gsen_fifo_x_send[ii], gsen_fifo_y_send[ii], gsen_fifo_z_send[ii], cal.Group1_Cur);\r
-// printf("FFF==> hr PPG_buf : %d, %d, PPG_buf: %d, ir_buf: %d \n", 1+ii, *count, PPG_buf[ii], ir_buf[0]);\r
- \r
-// #endif\r
-// }\r
-// ft_ppg_green = hrs_s_dat.green_data[0];\r
- // ft_test_result_t result = {0};\r
- // result.gr_data_final = hrs_s_dat.green_data[0];\r
- // result.ir_data_final = hrs_s_dat.ir_data[0];\r
- // hx3695_factory_test_process(NULL, APP_FACTORY_TEST_HR_START, &result);\r
- //PRINT("*count : %d \r\n",*count);\r
-\r
- //count7-9 为捕捉到的绿光值正常数据数量范围,不在此范围,心率数据不准,直接返回.\r
- // if(*count < 7 || *count > 9) \r
- // {\r
- // return;\r
- // }\r
- #ifdef SUPPORT_CYWEE_SERVICE\r
- memset(gsensordata,0.0f,sizeof(gsenson_t) * *count);\r
-\r
- cywee_get_gsensor_data(*count,gsensordata); \r
-\r
- for(ii=0; ii<*count; ii++)\r
- {\r
- // if(gsensordata[ii].x == 0.0f && gsensordata[ii].y == 0.0f && gsensordata[ii].z == 0.0f)\r
- // {\r
- // timeout++;\r
- // if(timeout > 20 && !acc_restart_flag) //避免重复开关gsensor\r
- // {\r
- // do_cywee_service_check_msg(CYWEE_SERVICE_CMD_RESTART_ACC,NULL);\r
- // acc_restart_flag = 1;\r
- // }\r
- // }\r
- // else\r
- // {\r
- // timeout = 0;\r
- // acc_restart_flag = 0;\r
- // }\r
-\r
- if(gsensordata[ii].x == 0 && gsensordata[ii].y == 0 && gsensordata[ii].z == 0)\r
- {\r
- gsen_fifo_x_send[ii] = gsen_fifo_x_send[ii - 1];\r
- gsen_fifo_y_send[ii] = gsen_fifo_y_send[ii - 1];\r
- gsen_fifo_z_send[ii] = gsen_fifo_z_send[ii - 1];\r
- }\r
- else\r
- {\r
- gsen_fifo_x_send[ii] = gsensordata[ii].x * 4096 / 10;\r
- gsen_fifo_y_send[ii] = gsensordata[ii].y * 4096 / 10;\r
- gsen_fifo_z_send[ii] = gsensordata[ii].z * 4096 / 10;\r
- }\r
- factory_data = PPG_buf[ii];\r
- // cywee_get_gsensor_data(8,gsensordata); \r
- // for(ii=0; ii<*count; ii++)\r
- // {\r
- // if(gsensordata[ii].x == 0.0f && gsensordata[ii].y == 0.0f && gsensordata[ii].z == 0.0f)\r
- // {\r
- // timeout++;\r
- // if(timeout > 20)\r
- // {\r
- // do_cywee_service_check_msg(CYWEE_SERVICE_CMD_RESTART_ACC,NULL);\r
- // }\r
- // }\r
- // else\r
- // {\r
- // timeout = 0;\r
- // }\r
- // // if(ii == 8)\r
- // // {\r
- // // gsen_fifo_x_send[ii] = gsen_fifo_x_send[ii - 1];\r
- // // gsen_fifo_y_send[ii] = gsen_fifo_y_send[ii - 1];\r
- // // gsen_fifo_z_send[ii] = gsen_fifo_z_send[ii - 1];\r
- // // }\r
- // // else\r
- // // {\r
- // if(ii < 9)\r
- // {\r
- // gsen_fifo_x_send[ii] = gsensordata[ii].x * 4096 / 10;\r
- // gsen_fifo_y_send[ii] = gsensordata[ii].y * 4096 / 10;\r
- // gsen_fifo_z_send[ii] = gsensordata[ii].z * 4096 / 10;\r
- // }\r
-\r
- // }\r
- // PRINT("hxdata:%d/%d %d %d %.3f %.3f %.3f %d\r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsensordata[ii].x,gsensordata[ii].y,gsensordata[ii].z,ppg_s_data.green_cur);\r
- //PRINT("hxdata:%d/%d %d %d %.3f %.3f %.3f %d\r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x_send[ii],gsen_fifo_y_send[ii],gsen_fifo_z_send[ii],ppg_s_data.green_cur);\r
- //PRINT("hxdata:%d/%d %d %d %d %d %d %d\r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x_send[ii],gsen_fifo_y_send[ii],gsen_fifo_z_send[ii],ppg_s_data.green_cur);\r
- //PRINT("hxdata:%d/%d %d %d %.3f %.3f %.3f %d\r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsensordata[ii].x,gsensordata[ii].y,gsensordata[ii].z,ppg_s_data.green_cur);\r
-\r
- }\r
-#endif\r
- hrs_wear_status = hx3695_hrs_get_wear_status();\r
- //PRINT("hrs_wear_status: %d !!\r\n", hrs_wear_status);\r
-\r
- if(hrs_wear_status == MSG_HRS_WEAR)\r
- {\r
- tyhx_hrs_alg_send_data(PPG_buf, *count, gsen_fifo_x_send, gsen_fifo_y_send, \r
- gsen_fifo_z_send, cal.Group1_Ledidac);\r
- }\r
-#endif\r
-\r
-\r
-/*屏蔽*/\r
-// for(ii=0; ii<*count; ii++)\r
-// {\r
-// #if 0\r
-// gsen_fifo_x_send[ii] = gsen_fifo_x[32-*count+ii];\r
-// gsen_fifo_y_send[ii] = gsen_fifo_y[32-*count+ii];\r
-// gsen_fifo_z_send[ii] = gsen_fifo_z[32-*count+ii];\r
- \r
-// PRINT("hx3695 gr,ir,gsen:%d/%d %d %d %d %d %d %d\r\n" ,\r
-// 1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x[ii],gsen_fifo_y[ii],gsen_fifo_z[ii],cal.Group1_Cur);\r
-// #else\r
-// // accel_data_struct_t accel_raw_data = {0};\r
-// // queue_output(&accel_raw_data);\r
-// // gsen_fifo_x_send[ii] = accel_raw_data.x;\r
-// // gsen_fifo_y_send[ii] = accel_raw_data.y;\r
-// // gsen_fifo_z_send[ii] = accel_raw_data.z;\r
-// // PRINT("hx3695 gr,ir,gsen:%d/%d %d %d %d %d %d %d hr==%d\r\n" ,\r
-// // 1+ii,*count,PPG_buf[ii], ir_buf[0], gsen_fifo_x_send[ii], gsen_fifo_y_send[ii], gsen_fifo_z_send[ii], cal.Group1_Cur,alg_results.hr_result);\r
-// #endif\r
-// }\r
- \r
- uint8_t curr_wear = 1;\r
- //uint8_t last_wear = cwm_get_wear_status();\r
-\r
- alg_results = tyhx_hrs_alg_get_results();\r
- hrsresult.lastesthrs = alg_results.hr_result;\r
- hrsresult.hr_living = alg_results.living_status;\r
- hrsresult.hr_living_qu = alg_results.hr_result_qual;\r
- hrsresult.hr_living_std = alg_results.hr_result_std;\r
- hrsresult.wearstatus = hrs_wear_status;\r
-\r
- if(hrsresult.wearstatus == MSG_HRS_WEAR)\r
- {\r
- wear_status = 1;\r
- if(hrsresult.lastesthrs > 30 && hrsresult.lastesthrs < 220)\r
- get_avg_hrs(hrsresult.lastesthrs);\r
- }\r
- else if(hrsresult.wearstatus == MSG_HRS_NO_WEAR || hrsresult.hr_living == MSG_LIVING_FAIL)\r
- {\r
- hrsresult.wearstatus = MSG_HRS_NO_WEAR;\r
- hrsresult.lastesthrs = 0;\r
- wear_status = 0;\r
- }\r
-\r
+ printf("hx3695_hrsdaily_enable\r\n");\r
+ tyhx_hrs_alg_open();\r
+ ppg_sensor_data.mode = HRSDAILY_MODE;\r
+ hx3695_ppg_set_mode(PPG_INIT);\r
\r
- // hx3695_msg_callback_t func = hx3695_get_send_msg_callback_func();\r
- \r
- // if(func != NULL)\r
- // {\r
- // if(his_wear == hrsresult.wearstatus)\r
- // {\r
- // wear_cnt++;\r
- // if(wear_cnt >= 2 && !his_wear) //未佩戴超过2次 上报未佩戴信息\r
- // {\r
- // func(HX3695_MSG_TYPE_WEARSTAT_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t));\r
- // wear_cnt = 0;\r
- // }\r
- // }\r
- // else\r
- // {\r
- // his_wear = hrsresult.wearstatus;\r
- // wear_cnt = 0;\r
- // }\r
- // }\r
- //PRINT("hrsresult.wearstatus : %d , his_wear : %d , wear_cnt : %d \n",hrsresult.wearstatus,his_wear,wear_cnt);\r
- // PRINT("hrsresult.wearstatus : %d , wear_status : %d , hr_living : %d \n",hrsresult.wearstatus,wear_status,hrsresult.hr_living);\r
- // if(hrs_wear_status == MSG_HRS_WEAR && hrsresult.hr_living == MSG_LIVING_TRUE)\r
- // {\r
- // if(hrsresult.lastesthrs > 30 && hrsresult.lastesthrs < 220)\r
- // get_avg_hrs(hrsresult.lastesthrs);\r
-\r
- // hrsresult.wearstatus = MSG_HRS_WEAR;\r
- // }\r
- // else\r
- // {\r
- // hrsresult.wearstatus = MSG_HRS_NO_WEAR;\r
- // hrsresult.lastesthrs = 0;\r
- // }\r
-\r
- // PRINT("hrs : %d , wear_status : %d \n",hrsresult.lastesthrs,wear_status);\r
- avg_hrs = hrsresult.lastesthrs;\r
-\r
- msg_count++;\r
- if(msg_count >= 3)\r
- {\r
-\r
-#ifdef SUPPORT_PPG_BLE_SERVICE\r
- if(uapi_dev_runtime_get_hrs_ble_status())\r
- {\r
- ble_ppgtest_server_send_input_report(&avg_hrs,1);\r
- }\r
-#endif\r
-\r
- msg_count = 0;\r
- // if(func != NULL)\r
- // {\r
- // //PRINT("hrsresult.lastesthrs : %d \n",hrsresult.lastesthrs);\r
- // func(HX3695_MSG_TYPE_HRS_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t));\r
- // if(uapi_get_cywee_static_state())\r
- // {\r
- // func(HX3695_MSG_TYPE_STATIC_HRS_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t));\r
- // }\r
- // }\r
-\r
- if(uapi_dev_runtime_get_train_status())\r
- {\r
- hx3695_wearstatus_update();\r
- // avg_hrs = hrsresult.lastesthrs;\r
- // do_cywee_service_check_msg(CYWEE_SERVICE_CMD_HRS_CHANGE,&cywee_data);\r
- }\r
- }\r
-\r
- // PRINT("hrsresult.wearstatus: %d, hr_living: %d, hr_result:%d \r\n",hrsresult.wearstatus,hrsresult.hr_living,hrsresult.lastesthrs);\r
-\r
- // PRINT("hx3695 data_cnt: %d, hr_living: %d, hr_living_qu: %d, hr_living_std: %d, hr_result:%d \r\n",alg_results.data_cnt, hrsresult.hr_living, hrsresult.hr_living_qu, hrsresult.hr_living_std, hrsresult.lastesthrs);\r
-\r
- if(hrs_wear_status == MSG_HRS_WEAR && hrsresult.hr_living == MSG_LIVING_TRUE)\r
- {\r
-// app_hr_reset_stop_timer();\r
- if(alg_results.hr_result)\r
- {\r
- \r
- //app_hr_cal_hr_values(alg_results.hr_result);\r
- //PRINT("app_hr_cal_hr_values tick:%d hr:%d", xTaskGetTickCount(), alg_results.hr_result);\r
- //cwm_hr_input(alg_results.hr_result);\r
- //hr_sensor_notify_factory_test();\r
- }\r
- hr_no_living_dur = 0;\r
- curr_wear = 1;\r
- }\r
- else if(hrs_wear_status == MSG_HRS_WEAR && hrsresult.hr_living != MSG_LIVING_TRUE)\r
- {\r
- if (++hr_no_living_dur > 12 * 1000 / tyhx_long_timer_tick)\r
- {\r
- //hr_stop_detect();\r
- //PRINT("MSG_HRS_WEAR:%d liv:%d", hrs_wear_status, hrsresult.hr_living);\r
- hr_no_living_dur = 0;\r
- curr_wear = 0;\r
- }\r
- }\r
- else if(hrs_wear_status == MSG_HRS_NO_WEAR || hrsresult.hr_living == MSG_LIVING_FAIL)\r
- {\r
- //hr_stop_detect();\r
- //PRINT("MSG_HRS_NO_WEAR:%d liv:%d", hrs_wear_status, hrsresult.hr_living);\r
- hr_no_living_dur = 0;\r
- curr_wear = 0;\r
- }\r
- \r
- //cwm_off_body_detect(curr_wear);\r
-\r
- #if defined(GSENSOR_LOG_NOTIFY) && GSENSOR_LOG_NOTIFY == 1 || defined(HRS_BLE_APP)\r
- \r
- if (last_wear!=curr_wear)\r
- {\r
- gui_send_message_by_data(MSG_HR_WEAR_STATUS_UPDATE, &curr_wear, 1);\r
- }\r
- #endif\r
-\r
-#ifdef BP_CUSTDOWN_ALG_LIB\r
- bp_results_t bp_alg_results;\r
- bp_alg_results = tyhx_alg_get_bp_results();\r
-#endif\r
-\r
-////////////////////////////////////////BLE+DISPLAY/////////////////////////////////\r
-\r
-\r
-#ifdef HRS_BLE_APP\r
- {\r
- rawdata_vector_t rawdata;\r
- for(ii=0; ii<*count; ii++)\r
- {\r
- rawdata.vector_flag = HRS_VECTOR_FLAG;\r
- rawdata.data_cnt = alg_results.data_cnt-*count+ii;\r
- rawdata.hr_result = alg_results.hr_result;\r
- rawdata.red_raw_data = PPG_buf[ii];\r
- rawdata.ir_raw_data = ir_buf[ii];\r
- rawdata.gsensor_x = gsen_fifo_x_send[ii];\r
- rawdata.gsensor_y = gsen_fifo_y_send[ii];\r
- rawdata.gsensor_z = gsen_fifo_z_send[ii];\r
- rawdata.red_cur = cal.Group1_Cur;\r
- rawdata.ir_cur = cal.Group1_Ledidac;\r
-// PRINT("@@@@@@@@@ HRS_BLE_APP gsen:%d %d %d\r\n", rawdata.gsensor_x, rawdata.gsensor_y, rawdata.gsensor_z);\r
- ble_rawdata_vector_push(rawdata);\r
- }\r
- }\r
- ble_rawdata_send_handler();\r
-#endif\r
-\r
- if(hrs_ble_falg)\r
- {\r
- uint8_t encoded_hrm[PPG_DATA_LEN_MAX] = {0};//PPG_DATA_LEN_MAX>17会导致APP连接提示定义设备与所选类型不匹配\r
- uint8_t red_bit = 0;\r
- uint8_t ir_bit = 0;\r
- uint8_t green_bit = 0;\r
- HRS_CAL_SET_T cal= get_hrs_agc_status();\r
-\r
- for(ii=0; ii<*count; ii++)\r
- {\r
- if(PPG_buf[ii]<0)\r
- {\r
- red_bit = 0x80;\r
- PPG_buf[ii] = -PPG_buf[ii];\r
- }\r
- if(ir_buf[ii]<0)\r
- {\r
- ir_bit = 0x80;\r
- ir_buf[ii] = -ir_buf[ii];\r
- }\r
-\r
- encoded_hrm[0] = 0x55;//心率标志位，一定要设置正确\r
- encoded_hrm[1] = (uint8_t)(alg_results.data_cnt - *count + ii) % 256;//原始data_cnt会一直自加，但是这里只有一个字节，0-255循环\r
- encoded_hrm[2] = (uint8_t)(alg_results.hr_result & 0xFF);//心率值\r
-\r
- encoded_hrm[3] = (uint8_t)((PPG_buf[ii] & 0xFF0000) >> 16) | red_bit; //绿灯原始数据\r
- encoded_hrm[4] = (uint8_t)((PPG_buf[ii] & 0xFF00) >> 8); //绿灯原始数据\r
- encoded_hrm[5] = (uint8_t)(PPG_buf[ii] & 0xFF); //绿灯原始数据\r
-\r
- encoded_hrm[6] = (uint8_t)((ir_buf[ii] & 0xFF0000) >> 16) | ir_bit; //ir原始数据\r
- encoded_hrm[7] = (uint8_t)((ir_buf[ii] & 0xFF00) >> 8); //ir原始数据\r
- encoded_hrm[8] = (uint8_t)(ir_buf[ii] & 0xFF); //ir原始数据\r
-\r
- encoded_hrm[9] = (uint8_t)((gsen_fifo_x_send[ii]&0xFF00)>>8);//模拟x，1234换成填入自己的x数据\r
- encoded_hrm[10] = (uint8_t)(gsen_fifo_x_send[ii]&0xFF);\r
- encoded_hrm[11] = (uint8_t)((gsen_fifo_y_send[ii]&0xFF00)>>8);//模拟y，-1234换成填入自己的y数据\r
- encoded_hrm[12] = (uint8_t)(gsen_fifo_y_send[ii]&0xFF);\r
- encoded_hrm[13] = (uint8_t)((gsen_fifo_z_send[ii]&0xFF00)>>8);//模拟z,3987换成填入自己的z数据\r
- encoded_hrm[14] = (uint8_t)(gsen_fifo_z_send[ii]&0xFF); \r
- \r
- encoded_hrm[15] = ppg_s_data.green_cur;//绿灯电流\r
- encoded_hrm[16] = ppg_s_data.ir_cur;//红外电流\r
-\r
-#ifdef SUPPORT_PPG_BLE_SERVICE\r
- if(cm_custom_ble_service_on_flag())\r
- ble_ppgtest_server_send_input_report(encoded_hrm,PPG_DATA_LEN_MAX);\r
-#endif\r
- // ble_op_att_send_data(ATT_CHARACTERISTIC_2a37_01_VALUE_HANDLE,encoded_hrm, \\r
- // sizeof(encoded_hrm)/sizeof(encoded_hrm[0]), ATT_OP_NOTIFY);//heartrate \r
- }\r
- }\r
-\r
-\r
-////////////////////////////////////////////////////////////////////////////////////\r
+ ppg_sensor_dat->led_activated = 2;\r
+ ppg_sensor_dat->fs = 25;\r
+ ppg_sensor_dat->watermark = 20;\r
+ ppg_sensor_dat->led_data[0].led_state = Activating;\r
+ ppg_sensor_dat->led_data[1].led_state = InActivating;\r
+ ppg_sensor_dat->led_data[2].led_state = InActivating;\r
+ ppg_sensor_dat->led_data[3].led_state = Activating;\r
+ ppg_sensor_dat->led_data[0].isneed_cal_start = true;\r
+ ppg_sensor_dat->led_data[1].isneed_cal_start = false;\r
+ ppg_sensor_dat->led_data[2].isneed_cal_start = false;\r
+ ppg_sensor_dat->led_data[3].isneed_cal_start = false;\r
+\r
+ hx3695_updata_sensor(ppg_sensor_dat);\r
+ DEBUG_PRINTF("hx3695_hrs_enable\n");\r
}\r
-#endif\r
\r
-#ifdef CHECK_LIVING_LIB\r
-hrs_sensor_data_t hrs_s_dat; \r
-\r
-void hx3695_living_Int_handle(void)\r
+void hx3695_spo2_enable(ppg_sensor_data_t *ppg_sensor_dat)\r
{\r
- uint8_t ii=0;\r
- hx3695_living_results_t living_alg_results = {MSG_LIVING_NO_WEAR,0,0,0};\r
- int32_t *PPG_buf = &(hrs_s_dat.green_data[0]);\r
- int32_t *ir_buf = &(hrs_s_dat.ir_data[0]);\r
- uint8_t *count = &(hrs_s_dat.count);\r
- hrs_wear_msg_code_t hrs_wear_status = MSG_HRS_NO_WEAR;\r
- int16_t gsen_fifo_x_send[32]= {0};\r
- int16_t gsen_fifo_y_send[32]= {0};\r
- int16_t gsen_fifo_z_send[32]= {0};\r
-\r
- if(hx3695_hrs_read(&hrs_s_dat) == 0)\r
- {\r
- return;\r
- }\r
- \r
-#ifndef GSEN_40MS_TIMMER\r
-// readFifoByHrsModule();\r
-#endif\r
- DEBUG_PRINTF("\r\nsend jlink cnt=%d\r\n",*count); \r
- \r
- \r
- for(ii=0; ii<*count; ii++)\r
- {\r
- gsen_fifo_x_send[ii] = gsen_fifo_x[32-*count+ii];\r
- gsen_fifo_y_send[ii] = gsen_fifo_y[32-*count+ii];\r
- gsen_fifo_z_send[ii] = gsen_fifo_z[32-*count+ii];\r
-\r
- DEBUG_PRINTF("ger:%d/%d %d %d %d %d %d %d\r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x[ii],gsen_fifo_y[ii],gsen_fifo_z[ii],ppg_s_data.green_cur);\r
- }\r
- hrs_wear_status = hx3695_hrs_get_wear_status();\r
- if(hrs_wear_status == MSG_HRS_WEAR)\r
- {\r
- hx3695_living_send_data(PPG_buf, *count, gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send);\r
- }\r
- living_alg_results = hx3695_living_get_results();\r
- DEBUG_PRINTF("res:%d %d %d %d\r\n",living_alg_results.data_cnt,living_alg_results.motion_status,living_alg_results.signal_quality,hrs_wear_status);\r
+ printf("hx3695_spo2_enable\r\n");\r
+ tyhx_spo2_alg_open();\r
+ ppg_sensor_data.mode = SPO2_MODE;\r
+ hx3695_ppg_set_mode(PPG_INIT);\r
+ ppg_sensor_dat->led_activated = 4;\r
+ ppg_sensor_dat->fs = 25;\r
+ ppg_sensor_dat->watermark = 40;\r
+ ppg_sensor_dat->led_data[0].led_state = Activating;\r
+ ppg_sensor_dat->led_data[1].led_state = Activating;\r
+ ppg_sensor_dat->led_data[2].led_state = Activating;\r
+ ppg_sensor_dat->led_data[3].led_state = Activating;\r
+ ppg_sensor_dat->led_data[0].isneed_cal_start = true;\r
+ ppg_sensor_dat->led_data[1].isneed_cal_start = true;\r
+ ppg_sensor_dat->led_data[2].isneed_cal_start = true;\r
+ ppg_sensor_dat->led_data[3].isneed_cal_start = false;\r
+ hx3695_updata_sensor(ppg_sensor_dat);\r
}\r
-#endif\r
-\r
-\r
-#ifdef SPO2_ALG_LIB\r
\r
-#ifdef SPO2_DATA_CALI\r
-void hx3695_spo2_data_cali_init(void)\r
+void hx3695_hrv_enable(ppg_sensor_data_t *ppg_sensor_dat)\r
{\r
- uint8_t ii;\r
- for(ii=0; ii<4; ii++)\r
- {\r
- red_data_fifo[ii] = 0;\r
- ir_data_fifo[ii] = 0;\r
- }\r
- red_dc_temp = 0;\r
- ir_dc_temp = 0;\r
- red_data_pre = 0;\r
- ir_data_pre = 0;\r
- red_jump_delta = 0;\r
- ir_jump_delta = 0;\r
- cali_data_cnt = 0;\r
+ printf("hx3695_hrv_enable\r\n");\r
+ tyhx_hrv_alg_open();\r
+ ppg_sensor_data.mode = HRV_MODE;\r
+ hx3695_ppg_set_mode(PPG_INIT);\r
+ ppg_sensor_dat->led_activated = 2;\r
+ ppg_sensor_dat->fs = 100;\r
+ ppg_sensor_dat->watermark = 50;\r
+ ppg_sensor_dat->led_data[0].led_state = Activating;\r
+ ppg_sensor_dat->led_data[1].led_state = InActivating;\r
+ ppg_sensor_dat->led_data[2].led_state = InActivating;\r
+ ppg_sensor_dat->led_data[3].led_state = Activating;\r
+ ppg_sensor_dat->led_data[0].isneed_cal_start = true;\r
+ ppg_sensor_dat->led_data[1].isneed_cal_start = false;\r
+ ppg_sensor_dat->led_data[2].isneed_cal_start = false;\r
+ ppg_sensor_dat->led_data[3].isneed_cal_start = false;\r
+ hx3695_updata_sensor(ppg_sensor_dat);\r
}\r
\r
-int32_t hx3695_red_data_cali(int32_t red_new_raw_data)\r
+void hx3695_wear_low_power(ppg_sensor_data_t *ppg_sensor_dat)\r
{\r
- uint8_t ii;\r
- int32_t red_data_final;\r
- int32_t red_data_cali;\r
- spo2_wear_msg_code_t touch_status;\r
- touch_status = hx3695_spo2_get_wear_status();\r
- if(touch_status == MSG_SPO2_NO_WEAR)\r
- {\r
- cali_data_cnt = 0;\r
- red_data_cali = red_new_raw_data;\r
- for(ii=0; ii<4; ii++)\r
- {\r
- red_data_fifo[ii] = 0;\r
- }\r
- red_dc_temp = 0;\r
- }\r
- else\r
- {\r
- for(ii=3; ii>0; ii--)\r
- {\r
- red_data_fifo[ii] = red_data_fifo[ii-1];\r
- }\r
- red_data_fifo[0] = red_new_raw_data;\r
- if(cali_data_cnt>=25)\r
- {\r
- if ((((red_data_fifo[1] - red_data_fifo[2]) > SOP2_DEGLITCH_THRE) && ((red_data_fifo[1] - red_new_raw_data) > SOP2_DEGLITCH_THRE)) || \\r
- (((red_data_fifo[1] - red_data_fifo[2]) < -SOP2_DEGLITCH_THRE) && ((red_data_fifo[1] - red_new_raw_data) < -SOP2_DEGLITCH_THRE)))\r
- {\r
- red_new_raw_data = red_data_fifo[2];\r
- red_data_fifo[1] = red_data_fifo[2];\r
- }\r
- else\r
- {\r
- red_new_raw_data = red_data_fifo[1];\r
- }\r
- if ((abs((red_new_raw_data - red_jump_delta) - red_data_pre) > SPO2_REMOVE_JUMP_THRE))\r
- {\r
- red_jump_delta = red_new_raw_data - red_data_pre;\r
- }\r
- red_data_cali = red_new_raw_data - red_jump_delta;\r
- red_data_pre = red_data_cali;\r
- }\r
- else\r
- {\r
- red_data_cali = red_data_fifo[1];\r
- red_data_pre = red_data_fifo[1];\r
- }\r
- }\r
- if(cali_data_cnt<=30)\r
- {\r
- red_dc_temp = red_data_cali;\r
- red_data_final = red_new_raw_data;\r
- }\r
- else\r
- {\r
- //red_dc_temp = (red_dc_temp*31 + red_data_cali)>>5;\r
- red_dc_temp = 0;\r
- red_data_final = red_data_cali - red_dc_temp + 2608*50*hx3695_spo2_agc_red_idac;\r
- }\r
- //DEBUG_PRINTF("%d %d %d %d %d %d\r\n", cali_data_cnt, red_new_raw_data, red_data_final, red_data_cali, red_dc_temp, hx3695_spo2_agc_red_idac);\r
- return red_data_final;\r
+ printf("hx3695_wear_low_power\r\n");\r
+ ppg_sensor_data.mode = WEAR_MODE;\r
+ hx3695_ppg_set_mode(PPG_INIT);\r
+ ppg_sensor_dat->led_activated = 1;\r
+ ppg_sensor_dat->fs = 5;\r
+ ppg_sensor_dat->watermark = 5;\r
+ ppg_sensor_dat->led_data[0].led_state = InActivating;\r
+ ppg_sensor_dat->led_data[1].led_state = InActivating;\r
+ ppg_sensor_dat->led_data[2].led_state = InActivating;\r
+ ppg_sensor_dat->led_data[3].led_state = Activating;\r
+ ppg_sensor_dat->led_data[0].isneed_cal_start = false;\r
+ ppg_sensor_dat->led_data[1].isneed_cal_start = false;\r
+ ppg_sensor_dat->led_data[2].isneed_cal_start = false;\r
+ ppg_sensor_dat->led_data[3].isneed_cal_start = false;\r
+ hx3695_updata_sensor(ppg_sensor_dat);\r
}\r
-int32_t hx3695_ir_data_cali(int32_t ir_new_raw_data)\r
+\r
+void hx3695_ppg_set_mode(uint8_t mode_cmd)\r
{\r
- uint8_t ii;\r
- int32_t ir_data_final;\r
- int32_t ir_data_cali;\r
- spo2_wear_msg_code_t touch_status;\r
- touch_status = hx3695_spo2_get_wear_status();\r
- if(touch_status == MSG_SPO2_NO_WEAR)\r
- {\r
- cali_data_cnt = 0;\r
- ir_data_cali = ir_new_raw_data;\r
- for(ii=0; ii<4; ii++)\r
- {\r
- ir_data_fifo[ii] = 0;\r
- }\r
- ir_dc_temp = 0;\r
- }\r
- else\r
+ DEBUG_PRINTF("hx3695_ppg_set_mode %d \r\n", mode_cmd);\r
+ switch (mode_cmd)\r
{\r
- for(ii=3; ii>0; ii--)\r
- {\r
- ir_data_fifo[ii] = ir_data_fifo[ii-1];\r
- }\r
- ir_data_fifo[0] = ir_new_raw_data;\r
- cali_data_cnt++;\r
- if(cali_data_cnt>=25)\r
- {\r
- if ((((ir_data_fifo[1] - ir_data_fifo[2]) > SOP2_DEGLITCH_THRE) && ((ir_data_fifo[1] - ir_new_raw_data) > SOP2_DEGLITCH_THRE)) || \\r
- (((ir_data_fifo[1] - ir_data_fifo[2]) < -SOP2_DEGLITCH_THRE) && ((ir_data_fifo[1] - ir_new_raw_data) < -SOP2_DEGLITCH_THRE)))\r
- {\r
- ir_new_raw_data = ir_data_fifo[2];\r
- ir_data_fifo[1] = ir_data_fifo[2];\r
- }\r
- else\r
+ case PPG_INIT:\r
+ hx3695_ppg_para_init(&ppg_sensor_data);\r
+ s_ppg_state = 1;\r
+ s_cal_state = 0;\r
+ if(work_mode_flag == HRS_MODE)\r
{\r
- ir_new_raw_data = ir_data_fifo[1];\r
+ #if defined(TIMMER_MODE)\r
+ hx3695_320ms_timer_cfg(true);\r
+ #else\r
+ hx3695_gpioint_cfg(true);\r
+ #endif\r
}\r
- if ((abs((ir_new_raw_data - ir_jump_delta) - ir_data_pre) > SPO2_REMOVE_JUMP_THRE))\r
- {\r
- ir_jump_delta = ir_new_raw_data - ir_data_pre;\r
- }\r
- ir_data_cali = ir_new_raw_data - ir_jump_delta;\r
- ir_data_pre = ir_data_cali;\r
- }\r
- else\r
- {\r
- ir_data_cali = ir_data_fifo[1];\r
- ir_data_pre = ir_data_fifo[1];\r
- }\r
- }\r
- if(cali_data_cnt<=30)\r
- {\r
- ir_dc_temp = ir_data_cali;\r
- ir_data_final = ir_new_raw_data;\r
- }\r
- else\r
- {\r
- //ir_dc_temp = (ir_dc_temp*31 + ir_data_cali)>>5;\r
- ir_dc_temp = 0;\r
- ir_data_final = ir_data_cali - ir_dc_temp + 2608*50*hx3695_spo2_agc_ir_idac;\r
+\r
+ DEBUG_PRINTF("ppg init mode\r\n");\r
+ break;\r
+\r
+ case PPG_OFF:\r
+ #if defined(TIMMER_MODE)\r
+ hx3695_320ms_timer_cfg(false);\r
+ hx3695_40ms_timer_cfg(false);\r
+ hx3695_5000ms_timer_cfg(false);\r
+ #elif defined(INT_MODE)\r
+ hx3695_gpioint_cfg(false);\r
+ #endif\r
+ hx3695_ppg_off();\r
+ s_ppg_state = 0;\r
+ s_cal_state = 0;\r
+ DEBUG_PRINTF("ppg off mode\r\n");\r
+ break;\r
+\r
+ case PPG_LED_OFF:\r
+ hx3695_wear_low_power(&ppg_sensor_data);\r
+ #if defined(TIMMER_MODE)\r
+ hx3695_5000ms_timer_cfg(true);\r
+ #endif\r
+ s_ppg_state = 1;\r
+ s_cal_state = 0;\r
+ DEBUG_PRINTF("ppg led off mode\r\n");\r
+ break;\r
+\r
+ case CAL_INIT:\r
+ hx3695_cal_init();\r
+ s_ppg_state = 0;\r
+ s_cal_state = 1;\r
+ #if defined(TIMMER_MODE)\r
+ hx3695_320ms_timer_cfg(false);\r
+ hx3695_40ms_timer_cfg(true);\r
+ #endif\r
+ DEBUG_PRINTF("cal init mode\r\n");\r
+ break;\r
+\r
+ case RECAL_INIT:\r
+ hx3695_recal_init();\r
+ s_ppg_state = 0;\r
+ s_cal_state = 1;\r
+ #if defined(TIMMER_MODE)\r
+ hx3695_320ms_timer_cfg(false);\r
+ hx3695_40ms_timer_cfg(true);\r
+ #endif\r
+ DEBUG_PRINTF("recal init mode\r\n");\r
+ break;\r
+\r
+ case CAL_OFF:\r
+ #if defined(TIMMER_MODE)\r
+ hx3695_320ms_timer_cfg(true);\r
+ hx3695_40ms_timer_cfg(false);\r
+ #endif\r
+ hx3695_cal_off();\r
+ s_ppg_state = 1;\r
+ s_cal_state = 0;\r
+ DEBUG_PRINTF("cal off mode\r\n");\r
+ break;\r
+\r
+ default:\r
+ break;\r
}\r
- //DEBUG_PRINTF("%d %d %d %d %d %d\r\n", cali_data_cnt, ir_new_raw_data, ir_data_final, ir_data_cali, ir_dc_temp, hx3695_spo2_agc_ir_idac);\r
- return ir_data_final;\r
}\r
-#endif //SPO2_DATA_CALI\r
\r
-//#ifdef SPO2_ALG_LIB\r
-spo2_sensor_data_t spo2_s_dat;\r
-\r
-/*TYHX 血氧模式下 读取PPG， 默认320ms*/\r
-void hx3695_spo2_ppg_Int_handle(void)\r
+bool hx3695_init(WORK_MODE_T mode)\r
{\r
- uint8_t ii=0;\r
- spo2_results_t spo2_alg_results = {MSG_SPO2_ALG_NOT_OPEN,0,0,0,0,0,0,1,0,0,0,0,0};\r
- spo2_wear_msg_code_t spo2_wear_status = MSG_SPO2_NO_WEAR;\r
- SPO2_CAL_SET_T cal = get_spo2_agc_status();\r
- int32_t *red_buf = &(spo2_s_dat.red_data[0]);\r
- int32_t *ir_buf = &(spo2_s_dat.ir_data1[0]);\r
- int32_t *green_buf = &(spo2_s_dat.green_data[0]);\r
- uint8_t *count = &(spo2_s_dat.count);\r
- int16_t gsen_fifo_x_send[32]= {0};\r
- int16_t gsen_fifo_y_send[32]= {0};\r
- int16_t gsen_fifo_z_send[32]= {0};\r
-#ifdef SPO2_DATA_CALI\r
- int32_t red_data_cali, ir_data_cali;\r
-#endif\r
-\r
-#ifdef SPO2_VECTOR\r
- for(ii=0; ii<8; ii++)\r
+ work_mode_flag = mode;\r
+ hx3695_software_reset();\r
+ hx3695_ppg_on();\r
+ if (hx3695_chip_check() != 0x65)\r
+ {\r
+ return false;\r
+ }\r
+ switch (work_mode_flag)\r
{\r
- red_buf_vec[ii] = vec_red_data[spo2_send_cnt+ii];\r
- ir_buf_vec[ii] = vec_ir_data[spo2_send_cnt+ii];\r
- green_buf_vec[ii] = vec_green_data[spo2_send_cnt+ii];\r
- }\r
- spo2_send_cnt = spo2_send_cnt+8;\r
- *count = 8;\r
- tyhx_spo2_alg_send_data(red_buf, ir_buf, green_buf, cal.R_LEDDAC, cal.IR_LEDDAC1, cal.R_LEDDAC, gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send, *count);\r
+ case HRS_MODE:\r
+ hx3695_hrs_enable(&ppg_sensor_data);\r
+ break;\r
+ \r
+ case HRSDAILY_MODE:\r
+ hx3695_hrsdaily_enable(&ppg_sensor_data);\r
+ break;\r
\r
-#else\r
- if(hx3695_spo2_read(&spo2_s_dat) == 0)\r
- {\r
- return;\r
- }\r
- \r
-#ifndef GSEN_40MS_TIMMER\r
-// readFifoByHrsModule();\r
-#endif\r
- //DEBUG_PRINTF("\r\n send1 jlink cnt=%d\r\n",*count); \r
- \r
- /*屏蔽*/\r
- //("*count[%d] \r\n",*count);\r
+ case LIVING_MODE:\r
\r
- //count7-9 为捕捉到的红光值正常数据数量范围,不在此范围,血氧数据不准,直接返回.\r
- if(*count < 7 || *count > 9)\r
- {\r
- return;\r
- }\r
- //cywee_get_gsensor_data(8,gsensordata);\r
- for(ii=0; ii<*count; ii++)\r
- {\r
+ break;\r
\r
- // if(ii == 8)\r
- // {\r
- // gsen_fifo_x_send[ii] = gsen_fifo_x_send[ii - 1];\r
- // gsen_fifo_y_send[ii] = gsen_fifo_y_send[ii - 1];\r
- // gsen_fifo_z_send[ii] = gsen_fifo_z_send[ii - 1];\r
- // }\r
- // else\r
- // {\r
- // gsen_fifo_x_send[ii] = gsensordata[ii].x * 2048;\r
- // gsen_fifo_y_send[ii] = gsensordata[ii].y * 2048;\r
- // gsen_fifo_z_send[ii] = gsensordata[ii].z * 2048;\r
- // }\r
- //("hxdata:%d/%d %d %d %d %d %d %d\r\n",\r
- //1+ii,*count,red_buf[ii],ir_buf[ii],green_buf[ii],gsen_fifo_x_send[ii],gsen_fifo_y_send[ii],gsen_fifo_z_send[ii]);\r
- //printf("FFF==>spo2 red_buf : %d, %d, %d, %d \n", 1+ii, *count, red_buf[ii], ir_buf[0]);\r
- factory_data = red_buf[ii];\r
- }\r
+ case SPO2_MODE:\r
+ hx3695_spo2_enable(&ppg_sensor_data);\r
+ tyhx_spo2_para_usuallyadjust(SPO2_LOW_XCORR_THRE, SPO2_LOW_SNR_THRE, COUNT_BLOCK_NUM, SPO2_BASE_LINE_INIT, SPO2_SLOPE, SPO2_GSEN_POW_THRE);\r
+ tyhx_spo2_para_barelychange(MEAN_NUM, SOP2_DEGLITCH_THRE, SPO2_REMOVE_JUMP_THRE, SPO2_LOW_CLIP_END_TIME, SPO2_LOW_CLIP_DN, SPO2_NORMAL_CLIP_DN,\r
+ IR_AC_TOUCH_THRE, IR_FFT_POW_THRE, SPO2_CALI, SLOPE_PARA_MAX, SLOPE_PARA_MIN);\r
\r
- // ft_ppg_iir = spo2_s_dat.red_data[0];\r
- // hx3695_factory_test_process(NULL, APP_FACTORY_TEST_SPO2_START, &ft_ppg_iir);\r
+ break;\r
\r
- ft_test_result_t result = {0};\r
- result.gr_data_final = spo2_s_dat.green_data[0];\r
- result.red_data_final = spo2_s_dat.red_data[0];\r
- result.ir_data_final = spo2_s_dat.ir_data1[0];\r
- //hx3695_factory_test_process(NULL, APP_FACTORY_TEST_SPO2_START, &result);\r
+ case HRV_MODE:\r
+ hx3695_hrv_enable(&ppg_sensor_data);\r
+ break;\r
\r
+ case WEAR_MODE:\r
+ hx3695_ppg_set_mode(PPG_LED_OFF);\r
+ break;\r
\r
- //("hx3695 current value: %d %d %d %d %d %d\r\n", cal.R_LED, cal.IR_LED1, cal.G_LED, cal.R_LEDDAC, cal.IR_LEDDAC1, cal.G_LEDDAC);\r
- spo2_wear_status = hx3695_spo2_get_wear_status();\r
- //PRINT("spo2_wear_status : %d\r\n",spo2_wear_status);\r
- if(spo2_wear_status == MSG_SPO2_WEAR)\r
- {\r
- tyhx_spo2_alg_send_data(red_buf, ir_buf, green_buf, cal.R_LEDDAC, cal.IR_LEDDAC1, cal.G_LEDDAC, \r
- gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send, *count);\r
- }\r
- \r
-#endif\r
+ case FT_LEAK_LIGHT_MODE:\r
+ if (hx3695_chip_check() != 0x65)\r
+ {\r
+ return false;\r
+ }\r
+ hx3695_factroy_test(LEAK_LIGHT_TEST);\r
+ return true;\r
+ break;\r
\r
- spo2_alg_results = tyhx_spo2_alg_get_results();\r
-//------------------------adjust-------------------\r
-// DEBUG_PRINTF("block_cnt: %d, data_cnt:%d, hr_result:%d,ir_quality:%d,motion:%d,poor_signal:%d,reliable_score_result:%d,screen_up:%d,spo2_result:%d\r\n",spo2_alg_results.block_cnt,spo2_alg_results.data_cnt,spo2_alg_results.hr_result,spo2_alg_results.ir_quality,spo2_alg_results.motion,spo2_alg_results.poor_signal,spo2_alg_results.reliable_score_result,spo2_alg_results.screen_up,spo2_alg_results.spo2_result);\r
+ case FT_GRAY_CARD_MODE:\r
+ if (hx3695_chip_check() != 0x65)\r
+ {\r
+ return false;\r
+ }\r
+ hx3695_factroy_test(GRAY_CARD_TEST);\r
+ return true;\r
+ break;\r
\r
- hrsresult.lastestspo2 = spo2_alg_results.spo2_result;\r
- hrsresult.lastesthrs = spo2_alg_results.hr_result;\r
- uint8_t curr_wear = 1;\r
+ case FT_INT_TEST_MODE:\r
+ //hx3695_factroy_test(FT_INT_TEST);\r
+ break;\r
\r
- if(spo2_wear_status == MSG_SPO2_WEAR)\r
- {\r
- wear_status = 1;\r
- }\r
- else if(spo2_wear_status == MSG_SPO2_NO_WEAR || spo2_alg_results.spo2_living_status == MSG_SPO2_LIVING_FAIL)\r
- {\r
- wear_status = 0;\r
- }\r
+ case AGING_CHECK_MODE:\r
+ hx3695_factroy_test(AGING_CHECK_TEST);\r
+ return true;\r
+ break;\r
\r
- // printf("spo2:%d wear:%d\n",spo2_alg_results.spo2_result,wear_status);\r
+ case FT_LED_OFF_MODE:\r
+ //hx3695_factroy_test(LED_OFF_TEST);\r
+ break;\r
\r
- //uint8_t last_wear = cwm_get_wear_status();\r
- if(spo2_wear_status == MSG_SPO2_WEAR && spo2_alg_results.spo2_living_status == MSG_SPO2_LIVING_TRUE)\r
- {\r
- //store_latest_spo2(hrsresult.lastestspo2);\r
- //app_hr_cal_hr_values(hrsresult.lastesthrs);\r
- //cwm_hr_input(hrsresult.lastesthrs);\r
- spo2_no_living_dur = 0;\r
- curr_wear = 1;\r
+ case FT_WEAR_MODE:\r
+ //hx3695_factroy_test(WEAR_MODE_TEST);\r
+ break;\r
+\r
+ default:\r
+ break;\r
}\r
- else if(spo2_wear_status == MSG_SPO2_WEAR && spo2_alg_results.spo2_living_status != MSG_SPO2_LIVING_TRUE)\r
+ hx3695_agc_Int_handle(&ppg_sensor_data);\r
+ return true;\r
+}\r
+\r
+void hx3695_agc_Int_handle(ppg_sensor_data_t *ppg_sensor_dat)\r
+{\r
+ uint8_t ii = 0;\r
+ if(s_ppg_state==1 && s_cal_state==0)\r
{\r
- if (++spo2_no_living_dur > 12 * 1000 / tyhx_long_timer_tick)\r
+ for(ii=0;ii<4;ii++)\r
{\r
- //gui_send_msg_by_evt(MSG_SPO2_MEASURE_CANCEL);\r
- //("MSG_SPO2_WEAR:%d liv:%d", spo2_wear_status, spo2_alg_results.spo2_living_status);\r
- spo2_no_living_dur = 0;\r
- curr_wear = 0;\r
+ if(ppg_sensor_dat->led_data[ii].isneed_cal_start == true)\r
+ {\r
+ hx3695_ppg_set_mode(CAL_INIT);\r
+ return;\r
+ }\r
}\r
}\r
- else if(spo2_wear_status == MSG_SPO2_NO_WEAR || spo2_alg_results.spo2_living_status == MSG_SPO2_LIVING_FAIL)\r
- {\r
- //gui_send_msg_by_evt(MSG_SPO2_MEASURE_CANCEL);\r
- //PRINT("MSG_SPO2_NO_WEAR:%d liv:%d", spo2_wear_status, spo2_alg_results.spo2_living_status);\r
- spo2_no_living_dur = 0;\r
- curr_wear = 0;\r
- }\r
- //cwm_off_body_detect(curr_wear);\r
- #if defined(GSENSOR_LOG_NOTIFY) && GSENSOR_LOG_NOTIFY == 1 || defined(HRS_BLE_APP)\r
- if (last_wear!=curr_wear)\r
- {\r
- gui_send_message_by_data(MSG_HR_WEAR_STATUS_UPDATE, &curr_wear, 1);\r
- }\r
- #endif\r
-/////////////////////////////////////////BLE+DISPLAY//////////////////////////////////////////\r
- spo2_alg_results = tyhx_spo2_alg_get_results();\r
-//------------------------adjust-------------------\r
- DEBUG_PRINTF("block_cnt: %d, data_cnt:%d, hr_result:%d,ir_quality:%d,motion:%d,poor_signal:%d,reliable_score_result:%d,screen_up:%d,spo2_result:%d\r\n",spo2_alg_results.block_cnt,spo2_alg_results.data_cnt,spo2_alg_results.hr_result,spo2_alg_results.ir_quality,spo2_alg_results.motion,spo2_alg_results.poor_signal,spo2_alg_results.reliable_score_result,spo2_alg_results.screen_up,spo2_alg_results.spo2_result);\r
- \r
- hrsresult.lastestspo2 = spo2_alg_results.spo2_result;\r
- spo2_result = hrsresult.lastestspo2;\r
-// if(hrsresult.lastestspo2)\r
- {\r
- // store_latest_spo2(hrsresult.lastestspo2);\r
- // app_hr_cal_hr_values(hrsresult.lastesthrs);\r
-// gui_send_message_by_data(MSG_SPO2_DATA, &hrsresult.lastestspo2, 1);\r
-// hr_sensor_notify_factory_test();\r
- }\r
- \r
- // hx3695_msg_callback_t func = hx3695_get_send_msg_callback_func();\r
- // if(func != NULL)\r
- // {\r
- // hrsresult.wearstatus = spo2_wear_status;\r
- // func(HX3695_MSG_TYPE_WEARSTAT_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t));\r
- // func(HX3695_MSG_TYPE_SPO2_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t));\r
- // }\r
+ hx3695_agc_process(ppg_sensor_dat);\r
+}\r
\r
+void agc_timeout_handler(void *p_context)\r
+{\r
+ // printf("agc_timeout_handler \n");\r
+ hx3695_agc_Int_handle(&ppg_sensor_data);\r
+}\r
\r
+void heart_rate_meas_timeout_handler(void *p_context)\r
+{\r
+ // printf("heart_rate_meas_timeout_handler \n");\r
+ hx3695_ppg_Int_handle(&ppg_sensor_data);\r
+ hx3695_agc_Int_handle(&ppg_sensor_data);\r
+}\r
\r
+void nrf_gpioint_handle(void)\r
+{\r
+ hx3695_ppg_Int_handle(&ppg_sensor_data);\r
+ hx3695_agc_Int_handle(&ppg_sensor_data);\r
+}\r
\r
-#ifdef HRS_BLE_APP\r
- {\r
- rawdata_vector_t rawdata;\r
- SPO2_CAL_SET_T cal= get_spo2_agc_status();\r
- for(ii=0; ii<*count; ii++)\r
- {\r
-#ifdef SPO2_DATA_CALI\r
- ir_data_cali = hx3695_ir_data_cali(ir_buf[ii]);\r
- red_data_cali = hx3695_red_data_cali(red_buf[ii]);\r
- rawdata.red_raw_data = red_data_cali>>2;\r
- rawdata.ir_raw_data = ir_data_cali>>2;\r
-#else\r
- rawdata.red_raw_data = red_buf[ii];\r
- rawdata.ir_raw_data = ir_buf[ii];\r
-#endif\r
- rawdata.vector_flag = SPO2_VECTOR_FLAG;\r
- rawdata.data_cnt = cal.G_LED;\r
- rawdata.hr_result = spo2_alg_results.spo2_result;\r
- rawdata.gsensor_x = (int16_t)(green_buf[ii]>>5);\r
- rawdata.gsensor_y = cal.R_LEDDAC;\r
- rawdata.gsensor_z = cal.IR_LEDDAC1;\r
- rawdata.red_cur = cal.R_LED;\r
- rawdata.ir_cur = cal.IR_LED1;\r
- ble_rawdata_vector_push(rawdata);\r
- }\r
- ble_rawdata_send_handler();\r
- }\r
-#endif\r
\r
-if(hrs_ble_falg)\r
+\r
+#define HRS_WINDOW_SIZE 5\r
+static uint8_t hrs_num = 0;\r
+static int32_t sum_hrs = 0;\r
+static int32_t hrs_data[7] = {0};\r
+static uint8_t left = 0;\r
+static uint8_t right = 0;\r
+static uint8_t avg_hrs = 0;\r
+\r
+static void get_avg_hrs(uint8_t hrs)\r
{\r
\r
- uint8_t encoded_hrm[PPG_DATA_LEN_MAX] = {0};//PPG_DATA_LEN_MAX>17会导致APP连接提示定义设备与所选类型不匹配\r
- uint8_t red_bit = 0;\r
- uint8_t ir_bit = 0;\r
- uint8_t green_bit = 0;\r
- //rawdata_vector_t rawdata;\r
- // SPO2_CAL_SET_T cal= get_spo2_agc_status();\r
\r
- for(ii=0; ii<*count; ii++)\r
- {\r
- if(red_buf[ii]<0)\r
- {\r
- red_bit = 0x80;\r
- red_buf[ii] = -red_buf[ii];\r
+ if (hrs_num >= HRS_WINDOW_SIZE) {\r
+ sum_hrs -= hrs_data[left];\r
+ left = (left + 1) % HRS_WINDOW_SIZE;\r
+ hrs_num--;\r
+ }\r
+\r
+ hrs_data[right] = hrs;\r
+ sum_hrs += hrs;\r
+ right = (right + 1) % HRS_WINDOW_SIZE;\r
+ hrs_num++;\r
+\r
+\r
+ if (hrs_num > 2) \r
+ {\r
+\r
+ uint8_t first_idx = left;\r
+ int32_t min_hrs = hrs_data[first_idx];\r
+ int32_t max_hrs = hrs_data[first_idx];\r
+\r
+\r
+ for (uint8_t i = 0; i < hrs_num; i++) {\r
+ uint8_t current_idx = (left + i) % HRS_WINDOW_SIZE;\r
+ uint8_t current_hrs = hrs_data[current_idx];\r
+\r
+ if (current_hrs < min_hrs) {\r
+ min_hrs = current_hrs;\r
}\r
- if(ir_buf[ii]<0)\r
- {\r
- ir_bit = 0x80;\r
- ir_buf[ii] = -ir_buf[ii];\r
+ if (current_hrs > max_hrs) {\r
+ max_hrs = current_hrs;\r
}\r
-\r
- encoded_hrm[0] = 0x66;//血氧标志位，一定要对\r
- encoded_hrm[1] = (uint8_t)(spo2_alg_results.data_cnt - *count + ii) % 256;\r
- encoded_hrm[2] = (uint8_t)(spo2_alg_results.spo2_result& 0xFF);\r
-\r
- encoded_hrm[3] = (uint8_t)((red_buf[ii] & 0xFF0000) >> 16) | red_bit; //红灯原始数据\r
- encoded_hrm[4] = (uint8_t)((red_buf[ii] & 0xFF00) >> 8);\r
- encoded_hrm[5] = (uint8_t)(red_buf[ii] & 0xFF);\r
-\r
- encoded_hrm[6] = (uint8_t)((ir_buf[ii] & 0xFF0000) >> 16) | ir_bit; //ir原始数据\r
- encoded_hrm[7] = (uint8_t)((ir_buf[ii] & 0xFF00) >> 8);\r
- encoded_hrm[8] = (uint8_t)(ir_buf[ii] & 0xFF);\r
-\r
- #ifdef SAR_ALG_LIB\r
- encoded_hrm[9] = (uint8_t)((gdiff[0]&0xFF00)>>8);//sar diff\r
- encoded_hrm[10] = (uint8_t)(gdiff[0]&0xFF);\r
- #else\r
- encoded_hrm[9] = (uint8_t)((gsen_fifo_x_send[ii]&0xFF00)>>8);//模拟x\r
- encoded_hrm[10] = (uint8_t)(gsen_fifo_x_send[ii]&0xFF);\r
- #endif\r
-\r
- encoded_hrm[11] = (uint8_t)((gsen_fifo_y_send[ii]&0xFF00)>>8);//模拟y\r
- encoded_hrm[12] = (uint8_t)(gsen_fifo_y_send[ii]&0xFF);\r
- encoded_hrm[13] = (uint8_t)((gsen_fifo_z_send[ii]&0xFF00)>>8);//模拟z\r
- encoded_hrm[14] = (uint8_t)(gsen_fifo_z_send[ii]&0xFF); \r
- \r
- encoded_hrm[15] = cal.R_LED;\r
- encoded_hrm[16] = cal.IR_LED1;\r
-#ifdef SUPPORT_PPG_BLE_SERVICE\r
- if(cm_custom_ble_service_on_flag())\r
- ble_ppgtest_server_send_input_report(encoded_hrm,PPG_DATA_LEN_MAX);\r
-#endif \r
}\r
- }\r
\r
+ uint8_t valid_count = hrs_num - 2;\r
+ avg_hrs = (sum_hrs - max_hrs - min_hrs) / valid_count;\r
\r
-/////////////////////////////////////////////////////////////////////////////////////////////////\r
+ // printf("max_hrs[%d],min_hrs[%d],avg_hrs[%d]\n",max_hrs,min_hrs,avg_hrs);\r
+ }\r
}\r
-#endif //SPO2_ALG_LIB\r
\r
+void hx3695_alg_send_data(ppg_sensor_data_t *ppg_sensor_dat, WORK_MODE_T mode, uint8_t data_count)\r
+{\r
+ uint16_t gcc_len = 16;\r
+ hrs_results_t hrs_result = {MSG_HRS_ALG_NOT_OPEN,MSG_LIVING_INITIAL,0,0,0,0,0,0,0,0,0,0,0,0};\r
+ spo2_results_t spo2_result = {MSG_SPO2_ALG_NOT_OPEN,MSG_SPO2_LIVING_INITIAL,0,0,0,0,0,0,0,0,0,0,0};\r
+ hrv_results_t hrv_alg_results= {MSG_HRV_ALG_NOT_OPEN,0,0,0,0,0,1,0,0,0,0};\r
+ switch(mode)\r
+ {\r
+ case HRS_MODE:\r
+ {\r
+// tyhx_acc_send_data(gsen_data_x_fifo, gsen_data_y_fifo, gsen_data_z_fifo, gcc_len, 50);\r
+// tyhx_hrs_alg_send_data(ppg_sensor_dat->led_data[0].data_val, ppg_sensor_dat->led_data[1].data_val, data_count, 100);\r
+#ifdef SUPPORT_CYWEE_SERVICE\r
+ memset(gsensordata,0.0f,sizeof(gsenson_t) * data_count);\r
\r
+ cywee_get_gsensor_data(data_count,gsensordata); \r
\r
-#if defined(HRS_ALG_LIB) && defined (SPO2_ALG_LIB)\r
-spo2_sensor_data_t hrspo2_s_data;\r
+ for(int ii=0; ii<data_count; ii++)\r
+ {\r
+ // if(gsensordata[ii].x == 0.0f && gsensordata[ii].y == 0.0f && gsensordata[ii].z == 0.0f)\r
+ // {\r
+ // timeout++;\r
+ // if(timeout > 20 && !acc_restart_flag) //避免重复开关gsensor\r
+ // {\r
+ // do_cywee_service_check_msg(CYWEE_SERVICE_CMD_RESTART_ACC,NULL);\r
+ // acc_restart_flag = 1;\r
+ // }\r
+ // }\r
+ // else\r
+ // {\r
+ // timeout = 0;\r
+ // acc_restart_flag = 0;\r
+ // }\r
+\r
+ if(gsensordata[ii].x == 0 && gsensordata[ii].y == 0 && gsensordata[ii].z == 0)\r
+ {\r
+ gsen_data_x_fifo[ii] = gsen_data_x_fifo[ii - 1];\r
+ gsen_data_y_fifo[ii] = gsen_data_y_fifo[ii - 1];\r
+ gsen_data_z_fifo[ii] = gsen_data_z_fifo[ii - 1];\r
+ }\r
+ else\r
+ {\r
+ gsen_data_x_fifo[ii] = gsensordata[ii].x * 4096 / 10;\r
+ gsen_data_y_fifo[ii] = gsensordata[ii].y * 4096 / 10;\r
+ gsen_data_z_fifo[ii] = gsensordata[ii].z * 4096 / 10;\r
+ }\r
+ // cywee_get_gsensor_data(8,gsensordata); \r
+ // for(ii=0; ii<*count; ii++)\r
+ // {\r
+ // if(gsensordata[ii].x == 0.0f && gsensordata[ii].y == 0.0f && gsensordata[ii].z == 0.0f)\r
+ // {\r
+ // timeout++;\r
+ // if(timeout > 20)\r
+ // {\r
+ // do_cywee_service_check_msg(CYWEE_SERVICE_CMD_RESTART_ACC,NULL);\r
+ // }\r
+ // }\r
+ // else\r
+ // {\r
+ // timeout = 0;\r
+ // }\r
+ // // if(ii == 8)\r
+ // // {\r
+ // // gsen_fifo_x_send[ii] = gsen_fifo_x_send[ii - 1];\r
+ // // gsen_fifo_y_send[ii] = gsen_fifo_y_send[ii - 1];\r
+ // // gsen_fifo_z_send[ii] = gsen_fifo_z_send[ii - 1];\r
+ // // }\r
+ // // else\r
+ // // {\r
+ // if(ii < 9)\r
+ // {\r
+ // gsen_fifo_x_send[ii] = gsensordata[ii].x * 4096 / 10;\r
+ // gsen_fifo_y_send[ii] = gsensordata[ii].y * 4096 / 10;\r
+ // gsen_fifo_z_send[ii] = gsensordata[ii].z * 4096 / 10;\r
+ // }\r
+\r
+ // }\r
+ // printf("gsensor: %d %.3f %.3f %.3f\r\n" ,data_count,gsensordata[ii].x,gsensordata[ii].y,gsensordata[ii].z);\r
+ //PRINT("hxdata:%d/%d %d %d %.3f %.3f %.3f %d\r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x_send[ii],gsen_fifo_y_send[ii],gsen_fifo_z_send[ii],ppg_s_data.green_cur);\r
+ //PRINT("hxdata:%d/%d %d %d %d %d %d %d\r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x_send[ii],gsen_fifo_y_send[ii],gsen_fifo_z_send[ii],ppg_s_data.green_cur);\r
+ //PRINT("hxdata:%d/%d %d %d %.3f %.3f %.3f %d\r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsensordata[ii].x,gsensordata[ii].y,gsensordata[ii].z,ppg_s_data.green_cur);\r
\r
-void hx3695_hrspo2_ppg_Int_handle(void)\r
-{\r
- uint8_t ii=0;\r
- spo2_results_t spo2_alg_results = {MSG_SPO2_ALG_NOT_OPEN,0,0,0,0,0,0,0,0,0,0,0,0};\r
- hrs_results_t alg_results = {MSG_HRS_ALG_NOT_OPEN,0,0,0,0,0,0};\r
- spo2_wear_msg_code_t spo2_wear_status = MSG_SPO2_NO_WEAR;\r
- SPO2_CAL_SET_T cal = get_spo2_agc_status();\r
- int32_t *red_buf = &(hrspo2_s_data.red_data[0]);\r
- int32_t *ir_buf = &(hrspo2_s_data.ir_data1[0]);\r
- int32_t *green_buf = &(hrspo2_s_data.red_data[0]); // &(hrspo2_s_data.green_data[0]);\r
- uint8_t *count = &(ppg_s_data.count);\r
- int16_t gsen_fifo_x_send[32]= {0};\r
- int16_t gsen_fifo_y_send[32]= {0};\r
- int16_t gsen_fifo_z_send[32]= {0};\r
-#ifdef SPO2_DATA_CALI\r
- int32_t red_data_cali, ir_data_cali;\r
+ }\r
#endif\r
+ factory_data = ppg_sensor_dat->led_data[0].data_val;\r
+ // printf("factory_data:%d\n", factory_data);\r
+ tyhx_hrs_alg_send_data(ppg_sensor_dat->led_data[0].data_val,data_count, gsen_data_x_fifo, gsen_data_y_fifo, gsen_data_z_fifo, ppg_sensor_dat->led_data[0].offset_idac);\r
+ //tyhx_hrs_alg_send_data(ppg_sensor_dat->led_data[0].data_val,data_count, gsen_data_x_fifo, gsen_data_y_fifo, gsen_data_z_fifo);\r
+ hrs_result = tyhx_hrs_alg_get_results();\r
+ DEBUG_PRINTF("HRS: %d %d\r\n",hrs_result.data_cnt, hrs_result.hr_result);\r
+ // printf("hr:%d\n", hrs_result.hr_result);\r
+ get_avg_hrs(hrs_result.hr_result);\r
+ break;\r
+ }\r
+ case SPO2_MODE:\r
+ {\r
+ tyhx_spo2_alg_send_data(ppg_sensor_dat->led_data[1].data_val, ppg_sensor_dat->led_data[2].data_val, ppg_sensor_dat->led_data[0].data_val, \\r
+ ppg_sensor_dat->led_data[1].offset_idac, ppg_sensor_dat->led_data[2].offset_idac,ppg_sensor_dat->led_data[0].offset_idac, \\r
+ gsen_data_x_fifo, gsen_data_y_fifo, gsen_data_z_fifo, data_count);\r
+ spo2_result = tyhx_spo2_alg_get_results();\r
+ DEBUG_PRINTF("SPO2: %d %d\r\n",spo2_result.data_cnt, spo2_result.spo2_result);\r
+ // printf("spo2:%d\n", spo2_result.spo2_result);\r
+ spo2_ret = spo2_result.spo2_result;\r
+ break;\r
+ }\r
+ case HRV_MODE:\r
+ {\r
+ hrv_alg_results = tyhx_hrv_alg_send_bufdata(ppg_sensor_dat->led_data[0].data_val,data_count, gsen_data_x_fifo, gsen_data_y_fifo, gsen_data_z_fifo);\r
+ DEBUG_PRINTF("data_cnt:%d hrv_result:%d motion:%d p_m:%d screen_up:%d signal_quality:%d \r\n", hrv_alg_results.data_cnt,hrv_alg_results.hrv_result,hrv_alg_results.motion,hrv_alg_results.p_m,hrv_alg_results.screen_up,hrv_alg_results.signal_quality);\r
+ // printf("hrv:%d\n",hrv_alg_results.hrv_result);\r
+ break;\r
+ }\r
+ default:\r
+ {\r
+ break;\r
+ }\r
+ }\r
+}\r
\r
- if(hx3695_spo2_read(&hrspo2_s_data) == 0)\r
- {\r
- return;\r
- }\r
- \r
-#ifndef GSEN_40MS_TIMMER\r
-//readFifoByHrsModule();\r
-#endif\r
- //DEBUG_PRINTF("\r\nsend jlink cnt=%d\r\n",*count); \r
- \r
- \r
- // for(ii=0; ii<*count; ii++)\r
- // {\r
- // gsen_fifo_x_send[ii] = gsen_fifo_x[32-*count+ii];\r
- // gsen_fifo_y_send[ii] = gsen_fifo_y[32-*count+ii];\r
- // gsen_fifo_z_send[ii] = gsen_fifo_z[32-*count+ii];\r
\r
- // }\r
- spo2_wear_status = hx3695_spo2_get_wear_status();\r
- if(spo2_wear_status == MSG_SPO2_WEAR)\r
+void hx3695_ppg_Int_handle(ppg_sensor_data_t *ppg_sensor_dat)\r
+{\r
+ uint16_t count = 0;\r
+ uint16_t ii = 0;\r
+ if(s_ppg_state == 0)\r
+ {\r
+ return;\r
+ }\r
+ count = hx3695_read_fifo_data(ppg_sensor_dat);\r
+ if(count > 0)\r
{\r
- tyhx_spo2_alg_send_data(red_buf, ir_buf, green_buf, cal.R_LEDDAC, cal.IR_LEDDAC1, cal.R_LEDDAC, gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send, *count);\r
- //tyhx_hrs_alg_send_data(green_buf,*count, gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send);\r
- //DEBUG_PRINTF("%d/%d %d %d %d %d %d %d\r\n" ,1+ii,*count,red_buf[ii],ir_buf[ii],green_buf[ii],gsen_fifo_x[ii],gsen_fifo_y[ii],gsen_fifo_z[ii]);\r
+ hx3695_check_wear(ppg_sensor_dat);\r
+ if(wear_status == MSG_WEAR)\r
+ {\r
+ hx3695_alg_send_data(ppg_sensor_dat,work_mode_flag,count);\r
+ }\r
}\r
- //DEBUG_PRINTF("%d %d %d %d %d %d\r\n", cal.R_LED, cal.IR_LED, cal.G_LED, cal.R_LEDDAC, cal.IR_LEDDAC, cal.G_LEDDAC);\r
\r
- spo2_alg_results = tyhx_spo2_alg_get_results();\r
- alg_results = tyhx_hrs_alg_get_results();\r
- //DEBUG_PRINTF("spo2_wear_status: %d, hr_result:%d, spo2_result:%d\r\n" ,spo2_wear_status, spo2_alg_results.hr_result,spo2_alg_results.spo2_result);\r
+ for(ii=0;ii<count;ii++)\r
+ {\r
+ DEBUG_PRINTF("%d/%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\r\n", ii+1, count, ppg_sensor_dat->led_data[0].data_val[ii], ppg_sensor_dat->led_data[1].data_val[ii],ppg_sensor_dat->led_data[2].data_val[ii], ppg_sensor_dat->led_data[3].data_val[ii], \\r
+ ppg_sensor_dat->led_data[0].led_current, ppg_sensor_dat->led_data[0].offset_idac, ppg_sensor_dat->led_data[1].led_current, ppg_sensor_dat->led_data[1].offset_idac,ppg_sensor_dat->led_data[2].led_current, ppg_sensor_dat->led_data[2].offset_idac);\r
+ }\r
+}\r
\r
-/////////////////////////////////////////BLE+DISPLAY//////////////////////////////////////////\r
+uint8_t hx3695_get_hrs(void)\r
+{\r
+ return avg_hrs;\r
+}\r
+\r
+uint8_t hx3695_get_spo2(void)\r
+{\r
+ return spo2_ret;\r
+}\r
\r
-#ifdef HRS_BLE_APP\r
- {\r
- rawdata_vector_t rawdata;\r
- SPO2_CAL_SET_T cal= get_spo2_agc_status();\r
- for(ii=0; ii<*count; ii++)\r
- {\r
-#ifdef SPO2_DATA_CALI\r
- ir_data_cali = hx3695_ir_data_cali(ir_buf[ii]);\r
- red_data_cali = hx3695_red_data_cali(red_buf[ii]);\r
- rawdata.red_raw_data = red_data_cali>>2;\r
- rawdata.ir_raw_data = ir_data_cali>>2;\r
-#else\r
- rawdata.red_raw_data = red_buf[ii];\r
- rawdata.ir_raw_data = ir_buf[ii];\r
-#endif\r
- rawdata.vector_flag = SPO2_VECTOR_FLAG;\r
- rawdata.data_cnt = cal.G_LEDDAC;\r
- rawdata.hr_result = spo2_alg_results.spo2_result;\r
- rawdata.gsensor_x = (int16_t)(green_buf[ii]>>5);\r
- rawdata.gsensor_y = cal.R_LEDDAC;\r
- rawdata.gsensor_z = cal.IR_LEDDAC1;\r
- rawdata.red_cur = cal.R_LED;\r
- rawdata.ir_cur = cal.IR_LED1;\r
- ble_rawdata_vector_push(rawdata);\r
- }\r
- ble_rawdata_send_handler();\r
- }\r
-#endif\r
\r
-/////////////////////////////////////////////////////////////////////////////////////////////////\r
+uint8_t hx3695_get_wear_status(void)\r
+{\r
+ return wear_status;\r
}\r
-#endif //defined(HRS_ALG_LIB) && defined (SPO2_ALG_LIB)\r
\r
-#ifdef HRV_ALG_LIB\r
-hrv_sensor_data_t hrv_s_dat;\r
-void hx3695_hrv_ppg_Int_handle(void)\r
+void hx3695_set_hrs_ble_swtich(uint8_t cmd)\r
{\r
- uint8_t ii=0;\r
- hrv_results_t hrv_alg_results= {MSG_HRV_ALG_NOT_OPEN,0,0,0,0,0,1,0,0};\r
- int32_t *PPG_buf = &(hrv_s_dat.green_data[0]);\r
- int32_t *ir_buf = &(hrv_s_dat.ir_data[0]);\r
- uint8_t *count = &(hrv_s_dat.count);\r
- hrv_wear_msg_code_t hrv_wear_status = MSG_HRV_NO_WEAR;\r
- int16_t gsen_fifo_x_send[64]= {0};\r
- int16_t gsen_fifo_y_send[64]= {0};\r
- int16_t gsen_fifo_z_send[64]= {0};\r
-\r
- // DEBUG_PRINTF("1111 \r\n" );\r
-#ifdef HRV_TESTVEC\r
- int32_t hrm_raw_data;\r
- hrm_raw_data = vec_data[vec_data_cnt];\r
- vec_data_cnt++;\r
- alg_hrv_results = hx3695_hrv_alg_send_data(hrm_raw_data, 0, 0);\r
-#else\r
- if(hx3695_hrv_read(&hrv_s_dat) == 0)\r
- {\r
- TYHX_LOG("read ppg_s data invalid\r\n");\r
- return;\r
- }\r
- \r
-#ifndef GSEN_40MS_TIMMER\r
-// readFifoByHrsModule();\r
-#endif\r
- DEBUG_PRINTF("\r\nsend jlink cnt=%d\r\n",*count); \r
- \r
- for(ii=0; ii<*count; ii++)\r
- {\r
- gsen_fifo_x_send[ii] = gsen_fifo_x[32-8+ii%8];\r
- gsen_fifo_y_send[ii] = gsen_fifo_y[32-8+ii%8];\r
- gsen_fifo_z_send[ii] = gsen_fifo_z[32-8+ii%8];\r
- // DEBUG_PRINTF("%d/%d %d %d %d %d %d \r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x_send[ii] ,gsen_fifo_y_send[ii] ,gsen_fifo_z_send[ii] );\r
+ hrs_ble_falg = cmd;\r
+ // PRINT("hrs_ble_falg : %d \n",hrs_ble_falg);\r
+}\r
\r
- }\r
- hrv_wear_status = hx3695_hrv_get_wear_status();\r
-// DEBUG_PRINTF("wear:%d \r\n" ,hrv_wear_status);\r
- if(hrv_wear_status==MSG_HRS_WEAR)\r
- {\r
- hrv_alg_results = tyhx_hrv_alg_send_bufdata(PPG_buf, *count, gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send);\r
- hrsresult.lastesthrv = hrv_alg_results.hrv_result;\r
- TYHX_LOG("get the hrv = %d\r\n",hrv_alg_results.hrv_result);\r
- }\r
- //--------------adjust----------------\r
-// hrv_alg_results.motion,hrv_alg_results.screen_up;\r
- //DEBUG_PRINTF("data_cnt:%d hrv_result:%d motion:%d p_m:%d screen_up:%d signal_quality:%d \r\n", hrv_alg_results.data_cnt,hrv_alg_results.hrv_result,hrv_alg_results.motion,hrv_alg_results.p_m,hrv_alg_results.screen_up,hrv_alg_results.signal_quality);\r
+uint8_t hx3695_get_hrs_ble_swtich(void)\r
+{\r
+ uint8_t cmd = hrs_ble_falg;\r
+ return cmd;\r
+}\r
+\r
+void hx3695_wearstatus_update(void)\r
+{\r
+ // if(history_wear_status != wear_result)\r
+ // {\r
+ // history_wear_status = wear_result;\r
+#ifdef SUPPORT_CYWEE_SERVICE\r
+ // do_cywee_service_check_msg(CYWEE_SERVICE_CMD_WEAR_STATUS_CHANGE,&wear_status);\r
+ cywee_wear_status_update(&wear_status);\r
#endif\r
+ // }\r
+}\r
+ //脱腕上报未佩戴信息\r
+void hx3695_unwearstatus_update(void)\r
+{\r
+ // hx3695_msg_callback_t func = hx3695_get_send_msg_callback_func();\r
+ // if(func != NULL && !uapi_dev_runtime_get_train_status())\r
+ // {\r
+ // hrsresult.lastesthrs = 0;\r
+ // hrsresult.wearstatus = 0;\r
+ // //为了主界面脱腕灵敏；需要增加未佩戴\r
+ // func(HX3695_MSG_TYPE_HRS_UPDATE, &hrsresult, sizeof(FT_CUSTOM_RESULTS_t));\r
+ // func(HX3695_MSG_TYPE_WEARSTAT_UPDATE, &hrsresult,sizeof(FT_CUSTOM_RESULTS_t));\r
+ // func(HX3695_MSG_TYPE_WEARSTAT_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t));\r
+ // func(HX3695_MSG_TYPE_WEARSTAT_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t));\r
+ // }\r
\r
-/////////////////////////////////////////BLE+DISPLAY//////////////////////////////////////////\r
+ if(uapi_dev_runtime_get_train_status())\r
+ {\r
+ wear_result = 0;\r
+ hx3695_wearstatus_update();\r
+ avg_hrs = 0;\r
\r
+ }\r
+} \r
\r
-#ifdef HRS_BLE_APP\r
+void wear_mode_timeout_handler(void * p_context)\r
+{\r
+ // printf("wear_mode_timeout_handler \n");\r
+ if(work_mode_flag == WEAR_MODE)\r
{\r
- rawdata_vector_t rawdata;\r
- HRS_CAL_SET_T cal= get_hrs_agc_status();\r
- for(ii=0; ii<*count; ii++)\r
- {\r
- rawdata.vector_flag = HRS_VECTOR_FLAG;\r
- rawdata.data_cnt = 0;\r
- rawdata.hr_result = hrv_alg_results.hrv_result;\r
- rawdata.red_raw_data = PPG_buf[ii];\r
- rawdata.ir_raw_data = 0;\r
- rawdata.gsensor_x = gsen_fifo_x_send[ii];\r
- rawdata.gsensor_y = gsen_fifo_y_send[ii];\r
- rawdata.gsensor_z = gsen_fifo_z_send[ii];\r
- rawdata.red_cur = cal.Group1_Cur;\r
- rawdata.ir_cur = 0;\r
- ble_rawdata_vector_push(rawdata);\r
- }\r
+ #ifdef CHECK_TOUCH_LIB\r
+ hx3695_ppg_Int_handle(&ppg_sensor_data);\r
+ #endif\r
}\r
+}\r
\r
- ble_rawdata_send_handler();\r
-#endif\r
+void hx3695_spo2_disable(void)\r
+{\r
+ hx3695_ppg_set_mode(PPG_OFF);\r
+ tyhx_spo2_alg_close();\r
\r
-//////////////////////////////////////////////////////////////////////////////////////////////\r
+ AGC_LOG("hx3695 disable!\r\n");\r
}\r
-#endif\r
\r
-#ifdef CHECK_TOUCH_LIB\r
-void hx3695_wear_ppg_Int_handle(void)\r
+void hx3695_hrs_disable(void)\r
{\r
-// PRINT("hx3695_wear_ppg_Int_handle wearstatus = %d\r\n", hrsresult.wearstatus);\r
- uint8_t *count = &(ppg_s_data.count);\r
- int32_t *ir_buf = &(ppg_s_data.ir_data[0]);\r
- hx3695_wear_msg_code_t hx3695_wear_status;\r
- \r
- hx3695_check_touch_read(&ppg_s_data);\r
- wear_status = hx3695_check_touch_send_data(ir_buf,*count);\r
- hx3695_wearstatus_update();\r
- extern uint8_t notouch_cnt;\r
- extern uint8_t touch_cnt;\r
- \r
-// PRINT("===> touch_cnt: %d, notouch_cnt: %d, wear status: %d, \r\n", touch_cnt, notouch_cnt, hx3695_wear_status);\r
-\r
- // PRINT("hx3695_wear_ppg_Int_handle wearstatus = %d\r\n", hrsresult.wearstatus);\r
- // PRINT("count : %d \r\n",*count);\r
- // for(int i=0;i<*count;i++)\r
- // {\r
- // PRINT("%d,%d,%d,%d,%d,%d\r\n",1+i,*count,ir_buf[i],ppg_s_data.s_buf[i*2],ppg_s_data.s_buf[i*2+1],hx3695_wear_status);\r
- // }\r
+ hx3695_ppg_set_mode(PPG_OFF);\r
+ tyhx_hrs_alg_close();\r
+ AGC_LOG("hx3695 disable!\r\n");\r
}\r
-#endif\r
\r
-#ifdef LAB_TEST\r
-void hx3695_lab_test_Int_handle(void)\r
+void hx3695_hrv_disable(void)\r
{\r
- NOISE_PS_T ps_noise;\r
- ps_noise = hx3695_lab_test_read_packet();\r
- DEBUG_PRINTF("%d %d %d %d\r\n", ps_noise.p1_noise, ps_noise.p2_noise, ps_noise.p3_noise, ps_noise.p4_noise);\r
+ hx3695_ppg_set_mode(PPG_OFF);\r
+ tyhx_hrv_alg_close();\r
+\r
+ AGC_LOG("hx3695 hrv disable!\r\n");\r
}\r
-#endif\r
\r
void hx3695_control(char *mode,uint8_t enable)\r
{\r
md = FT_LED_OFF_MODE;\r
} else if (strcmp(mode, "wear") == 0) {\r
md = WEAR_MODE;\r
- } else if (strcmp(mode, "single") == 0) {\r
- md = FT_SINGLE_CHECK_MODE;\r
- } \r
+ }\r
\r
\r
if (enable == 1 || md == FT_LED_OFF_MODE) {\r
hx3695_init(md);\r
} else {\r
- if(md == HRS_MODE|| md == FT_LEAK_LIGHT_MODE || md == FT_GRAY_CARD_MODE || md == WEAR_MODE || md == FT_SINGLE_CHECK_MODE)\r
+ if(md == HRS_MODE|| md == FT_LEAK_LIGHT_MODE || md == FT_GRAY_CARD_MODE || md == WEAR_MODE)\r
{\r
#ifdef HRS_ALG_LIB \r
hx3695_hrs_disable();\r
left = 0;\r
right = 0;\r
avg_hrs = 0;\r
- wear_cnt = 0;\r
+ // wear_cnt = 0;\r
#endif\r
}else if(md == HRV_MODE)\r
{\r
}\r
}\r
\r
+\r
int32_t hx3695_get_factory_data(void)\r
{\r
int32_t data = factory_data;\r
return data;\r
}\r
\r
-#endif //CHIP_HX3695\r
-\r
*/\r
#define HRS_ALG_LIB \r
#define SPO2_ALG_LIB\r
-//#define HRV_ALG_LIB\r
+ #define HRV_ALG_LIB\r
#define CHECK_TOUCH_LIB\r
-//#define CHECK_LIVING_LIB\r
-//#define BP_CUSTDOWN_ALG_LIB\r
+// #define CHECK_LIVING_LIB\r
+#define BP_CUSTDOWN_ALG_LIB\r
\r
//**************** read_data_mode ******************//\r
-#define TIMMER_MODE //timmer read fifo\r
-//#define INT_MODE //fifo_all_most_full\r
+ #define TIMMER_MODE //timmer read fifo\r
+//#define INT_MODE // this is fifo_all_most_full mode\r
\r
//****************** gsen_cgf *********************//\r
-//#define GSEN_40MS_TIMMER\r
-//#define NEW_GSEN_SCHME\r
+// #define GSEN_40MS_TIMMER\r
+// #define NEW_GSEN_SCHME\r
\r
+//#define TYHX_DEMO // for ty demo\r
+//#define DOUBLE_GREEN\r
//****************** other_cgf ********************//\r
+// #define EVB\r
#define DEMO_COMMON\r
-//#define HRS_BLE_APP\r
-//#define SPO2_DATA_CALI\r
+// #define HRS_BLE_APP\r
+// #define SPO2_DATA_CALI\r
\r
//***************** vecter_swi ********************//\r
-//#define SPO2_VECTOR\r
-//#define HR_VECTOR\r
-//#define HRV_TESTVEC\r
+// #define SPO2_VECTOR\r
+// #define HR_VECTOR\r
+// #define HRV_TESTVEC\r
\r
//**************** lab_test_mode ******************//\r
-//#define LAB_TEST \r
-//#define LAB_TEST_AGC \r
+// #define LAB_TEST\r
+// #define LAB_TEST_AGC\r
\r
//****************** print_swi ********************//\r
-#define HRS_DEBUG\r
+//#define HRS_DEBUG\r
//#define AGC_DEBUG\r
+//#define TYHX_DEBUG\r
\r
//**************************************************//\r
-#define PREFIX_PRINTF(_message,...) //printf(_message,##__VA_ARGS__)\r
-\r
-#define SEGGER_RTT_printf(_message, ...) //printf(_message,##__VA_ARGS__)\r
+// #ifdef TYHX_DEBUG\r
+// #define TYHX_LOG(...) SEGGER_RTT_printf(0,__VA_ARGS__)\r
+// #else\r
+// #define TYHX_LOG(...)\r
+// #endif\r
\r
#ifdef AGC_DEBUG\r
#define AGC_LOG(...) SEGGER_RTT_printf(0,__VA_ARGS__)\r
#else\r
-#define AGC_LOG(...) PREFIX_PRINTF("hx3695 agc=>"__VA_ARGS__)\r
+#define AGC_LOG(...)\r
#endif\r
\r
#ifdef HRS_DEBUG\r
#define DEBUG_PRINTF(...) SEGGER_RTT_printf(0,__VA_ARGS__)\r
#else\r
-#define DEBUG_PRINTF(...) PREFIX_PRINTF("hx3695 debug=>"__VA_ARGS__)\r
+#define DEBUG_PRINTF(...)\r
#endif\r
\r
-\r
#if defined(DEMO_COMMON)\r
- #define HRS4100_IIC_CLK 30\r
- #define HRS4100_IIC_SDA 0 \r
- #define LIS3DH_IIC_CLK 18\r
- #define LIS3DH_IIC_SDA 16\r
- #define EXT_INT_PIN 1\r
- #define GREEN_LED_SLE 0x50 //demo 0x10 evb 2\r
- #define RED_LED_SLE 0x80 //demo 0x20 evb 4 \r
- #define IR_LED_SLE 0x20 //demo 0x40 evb 1\r
- #define RED_AGC_OFFSET 64 //32\r
- #define IR_AGC_OFFSET 64 //32\r
- #define GREEN_AGC_OFFSET 20 //10\r
- #define HR_GREEN_AGC_OFFSET 48\r
- #define HR_GREEN1_AGC_OFFSET 48\r
- #define HR_GREEN2_AGC_OFFSET 48\r
- #define HR_GREEN3_AGC_OFFSET 48\r
- #define HRS_PD 0x0F // PD1:1 PD2:2 PD3:4 PD4:8\r
- #define SPO2_PD 0x02 // PD1:1 PD2:2 PD3:4 PD4:8\r
- \r
- #define BIG_SCREEN\r
- \r
-#elif defined(DEMO_MI)\r
- #define HRS4100_IIC_CLK 30\r
- #define HRS4100_IIC_SDA 0 \r
- #define LIS3DH_IIC_CLK 18\r
- #define LIS3DH_IIC_SDA 16\r
- #define EXT_INT_PIN 1\r
- #define GREEN_LED_SLE 1\r
- #define RED_LED_SLE 2\r
- #define IR_LED_SLE 4\r
- #define RED_AGC_OFFSET 50\r
- #define IR_AGC_OFFSET 50\r
- #define GREEN_AGC_OFFSET 4\r
- #define HR_GREEN_AGC_OFFSET 4\r
- #define BIG_SCREEN\r
- \r
-#elif defined(DEMO_NEW)\r
- #define HRS4100_IIC_CLK 30\r
- #define HRS4100_IIC_SDA 0 \r
- #define LIS3DH_IIC_CLK 18\r
- #define LIS3DH_IIC_SDA 16\r
- #define EXT_INT_PIN 1\r
- #define GREEN_LED_SLE 1\r
- #define RED_LED_SLE 2\r
- #define IR_LED_SLE 4\r
- #define RED_AGC_OFFSET 75\r
- #define IR_AGC_OFFSET 75\r
- #define GREEN_AGC_OFFSET 4\r
- #define HR_GREEN_AGC_OFFSET 8\r
- #define BIG_SCREEN\r
- \r
-#elif defined(EVB)\r
#define HRS4100_IIC_CLK 9\r
- #define HRS4100_IIC_SDA 10 \r
+ #define HRS4100_IIC_SDA 10\r
#define LIS3DH_IIC_CLK 13\r
#define LIS3DH_IIC_SDA 14\r
#define EXT_INT_PIN 11\r
- #define GREEN_LED_SLE 1\r
- #define RED_LED_SLE 2\r
- #define IR_LED_SLE 4\r
- #define RED_AGC_OFFSET 64\r
- #define IR_AGC_OFFSET 64\r
- #define GREEN_AGC_OFFSET 8\r
- #define HR_GREEN_AGC_OFFSET 10\r
- \r
-#else\r
- #define GREEN_LED_SLE 1\r
- #define RED_LED_SLE 4\r
- #define IR_LED_SLE 2\r
- #define RED_AGC_OFFSET 64\r
- #define IR_AGC_OFFSET 64\r
- #define GREEN_AGC_OFFSET 8\r
- \r
+\r
+ #define FIFO_DATA_LENGTH 200 //fifo_max = 256\r
+ #define PHASE_DATA_LENGTH 64 \r
+\r
+ #define LED0_LDR_SEL 0x50 //�̵�\r
+ #define LED1_LDR_SEL 0x80 // ���\r
+ #define LED2_LDR_SEL 0x20 // ����\r
+ #define LED3_LDR_SEL 0x20 // ����\r
+\r
+ #define LED0_PD_SEL 0x0F //ѡpd1\r
+ #define LED1_PD_SEL 0x02\r
+ #define LED2_PD_SEL 0x02\r
+ #define LED3_PD_SEL 0x02\r
+ \r
+ #ifdef DOUBLE_GREEN\r
+ #define LED1N_LDR_SEL 0x01\r
+ #define LED1N_PD_SEL 0x01\r
+ #endif\r
+ \r
+ #define CHECK_TOUCH_NUM 5 //��������ʱ,N��data\r
+ #define CHECK_WEAR_THRE 30000 \r
+ #define CHECK_UNWEAR_THRE 20000\r
+#elif defined(EVB)\r
+ #define HRS4100_IIC_CLK 9\r
+ #define HRS4100_IIC_SDA 10\r
+ #define LIS3DH_IIC_CLK 13\r
+ #define LIS3DH_IIC_SDA 14\r
+ #define EXT_INT_PIN 11\r
+\r
+ #define FIFO_DATA_LENGTH 200 //fifo_max = 256\r
+ #define PHASE_DATA_LENGTH 64 \r
+\r
+ #define LED0_LDR_SEL 0x10 //�̵�\r
+ #define LED1_LDR_SEL 0x08 // ���\r
+ #define LED2_LDR_SEL 0x80 // ����\r
+ #define LED3_LDR_SEL 0x80 // ����\r
+\r
+ #define LED0_PD_SEL 0x06 //ѡpd2��pd3\r
+ #define LED1_PD_SEL 0x06\r
+ #define LED2_PD_SEL 0x06\r
+ #define LED3_PD_SEL 0x02\r
+ #ifdef DOUBLE_GREEN\r
+ #define LED1N_LDR_SEL 0x03\r
+ #define LED1N_PD_SEL 0x02\r
+ #endif\r
+ #define CHECK_TOUCH_NUM 5 //��������ʱ,N��data\r
+ #define CHECK_WEAR_THRE 30000 \r
+ #define CHECK_UNWEAR_THRE 20000\r
#endif\r
\r
-typedef enum { \r
- PPG_INIT, \r
- PPG_OFF, \r
+typedef enum {\r
+ PPG_INIT,\r
+ PPG_OFF,\r
PPG_LED_OFF,\r
CAL_INIT,\r
CAL_OFF,\r
- RECAL_INIT \r
+ RECAL_INIT\r
} hx3695_mode_t;\r
\r
-typedef enum { \r
- SENSOR_OK, \r
- SENSOR_OP_FAILED, \r
-} SENSOR_ERROR_T;\r
-\r
-\r
-typedef enum { \r
- DATA_TYPE_PPG, \r
- DATA_TYPE_GSEN, \r
-} SENSOR_TYPE_T;\r
+typedef enum {\r
+ MSG_NO_WEAR,\r
+ MSG_WEAR,\r
+ MSG_NO_INIT\r
+} wear_msg_code_t;\r
\r
-typedef enum { \r
- HRS_MODE, // 0\r
- SPO2_MODE, // 1\r
- HRSPO2_MODE, // 2\r
- WEAR_MODE, //3\r
- HRV_MODE, // 4\r
- LIVING_MODE, // 5\r
- LAB_TEST_MODE, // 6\r
- FT_LEAK_LIGHT_MODE, // 7\r
- FT_GRAY_CARD_MODE, // 8\r
- FT_INT_TEST_MODE, // 9\r
- FT_SINGLE_CHECK_MODE,\r
+typedef enum {\r
+ HRS_MODE,\r
+ SPO2_MODE,\r
+ WEAR_MODE,\r
+ HRV_MODE,\r
+ HRSDAILY_MODE,\r
+ LIVING_MODE,\r
+ LAB_TEST_MODE,\r
+ FT_LEAK_LIGHT_MODE,\r
+ FT_GRAY_CARD_MODE,\r
+ FT_INT_TEST_MODE,\r
+ AGING_CHECK_MODE,\r
FT_LED_OFF_MODE,\r
FT_WEAR_MODE,\r
- NEW_PPG_TEST_MODE,\r
NULL_MODE,\r
} WORK_MODE_T;\r
\r
-\r
-//typedef struct {\r
-// uint8_t count;\r
-// int32_t green_data[64];\r
-// int32_t ir_data[64];\r
-// int32_t s_buf[64]; \r
-// uint32_t als;\r
-// uint32_t agc_green;\r
-//} hrs_sensor_data_t;\r
-\r
-\r
-typedef struct {\r
- uint8_t count;\r
- int32_t red_data[64];\r
- int32_t green_data[64];\r
- int32_t ir_data[64]; \r
- int32_t s_buf[64];\r
- uint8_t green_cur;\r
- uint8_t red_cur; \r
- uint8_t ir_cur;\r
- uint8_t green_offset;\r
- uint8_t red_offset; \r
- uint8_t ir_offset; \r
-}ppg_sensor_data_t;\r
-\r
-typedef enum {\r
- MSG_LIVING_INIT,\r
- MSG_LIVING_NO_WEAR,\r
- MSG_LIVING_WEAR\r
-} hx3695_living_wear_msg_code_t;\r
-\r
typedef enum {\r
- MSG_NO_WEAR,\r
- MSG_WEAR\r
-} hx3695_wear_msg_code_t;\r
+ InActivating,\r
+ InActivated,\r
+ Activating,\r
+ Activated,\r
+} led_state_t;\r
\r
typedef struct {\r
- hx3695_living_wear_msg_code_t wear_status;\r
- uint32_t data_cnt;\r
- uint8_t signal_quality;\r
- uint8_t motion_status;\r
-} hx3695_living_results_t;\r
+ int32_t data_val[PHASE_DATA_LENGTH];\r
+ uint8_t data_count;\r
+ uint16_t led_current;\r
+ uint8_t offset_idac;\r
+ uint8_t tia_rf;\r
+ led_state_t led_state;\r
+ bool isneed_cal_start;\r
+}led_data_t;\r
\r
typedef struct {\r
- int32_t p1_noise; \r
- int32_t p2_noise; \r
- int32_t p3_noise;\r
- int32_t p4_noise;\r
-}NOISE_PS_T;\r
-\r
+ WORK_MODE_T mode;\r
+ led_data_t led_data[4];\r
+ uint8_t s_buf[FIFO_DATA_LENGTH*3];\r
+ uint8_t led_activated;\r
+ uint8_t watermark;\r
+ uint8_t fs;\r
+}ppg_sensor_data_t;\r
\r
-extern uint8_t alg_ram[11*1024];\r
-//extern uint8_t alg_ram[10];\r
+extern uint8_t alg_ram[11 * 1024];\r
\r
void hx3695_delay_us(uint32_t us);\r
void hx3695_delay_ms(uint32_t ms);\r
-bool hx3695_write_reg(uint8_t addr, uint8_t data); \r
-uint8_t hx3695_read_reg(uint8_t addr); \r
-bool hx3695_brust_read_reg(uint8_t addr , uint8_t *buf, uint16_t length);\r
+bool hx3695_write_reg(uint8_t addr, uint8_t data);\r
+uint8_t hx3695_read_reg(uint8_t addr);\r
+void hx3695_brust_read_reg(uint8_t addr, uint8_t *buf, uint16_t length);\r
uint8_t hx3695_chip_check(void);\r
-void hx3695_get_id(uint8_t *ppg_id);\r
uint8_t hx3695_read_fifo_size(void);\r
-uint16_t hx3695_read_fifo_data(int32_t *s_buf, uint8_t size, uint8_t phase_num);\r
+uint16_t hx3695_read_fifo_data(ppg_sensor_data_t *ppg_sensor_data);\r
+uint16_t hx3695_led_data_analysis(ppg_sensor_data_t *ppg_sensor_dat, uint16_t fifo_read_length, uint8_t sig);\r
+void hx3695_get_led_para(ppg_sensor_data_t *ppg_sensor_dat);\r
+void hx3695_read_phase_data(int32_t *s_buf);\r
+void hx3695_read_led_data(int32_t *s_buf);\r
void hx3695_ppg_off(void);\r
-void hx3695_ppg_on(void); \r
+void hx3695_ppg_on(void);\r
+void hx3695_ppg_para_init(ppg_sensor_data_t *ppg_sensor_dat);\r
+void hx3695_wear_low_power(ppg_sensor_data_t *ppg_sensor_dat);\r
+void hx3695_set_fs(ppg_sensor_data_t *ppg_sensor_dat);\r
+void hx3695_set_watermark(ppg_sensor_data_t *ppg_sensor_dat);\r
+void hx3695_led_control(ppg_sensor_data_t *ppg_sensor_dat, uint8_t index);\r
+void hx3695_updata_sensor(ppg_sensor_data_t *ppg_sensor_dat);\r
+void hx3695_hrs_enable(ppg_sensor_data_t *ppg_sensor_dat);\r
+void hx3695_spo2_enable(ppg_sensor_data_t *ppg_sensor_dat);\r
+void hx3695_hrv_enable(ppg_sensor_data_t *ppg_sensor_dat);\r
+void hx3695_ppg_set_mode(uint8_t mode_cmd);\r
void hx3695_320ms_timer_cfg(bool en);\r
void hx3695_40ms_timer_cfg(bool en);\r
void hx3695_5000ms_timer_cfg(bool en);\r
void hx3695_gpioint_cfg(bool en);\r
bool hx3695_init(WORK_MODE_T mode);\r
-void hx3695_agc_Int_handle(void); \r
-void hx3695_gesensor_Int_handle(void);\r
-void hx3695_spo2_ppg_init(void);\r
-void hx3695_spo2_data_cali_init(void);\r
-void hx3695_spo2_ppg_Int_handle(void);\r
-void hx3695_check_touch_init(void);\r
-void hx3695_wear_ppg_Int_handle(void);\r
-void hx3695_hrs_ppg_init(void);\r
-void hx3695_hrs_ppg_Int_handle(void);\r
-void hx3695_hrv_ppg_init(void);\r
-void hx3695_hrv_ppg_Int_handle(void);\r
-void hx3695_living_Int_handle(void);\r
-void hx3695_hrspo2_ppg_Int_handle(void);\r
-\r
-\r
-void hx3695_ppg_Int_handle(void);\r
-uint32_t hx3695_timers_start(void);\r
-uint32_t hx3695_timers_stop(void);\r
-uint32_t hx3695_gpioint_init(void);\r
-\r
-uint32_t hx3695_gpioint_enable(void);\r
-uint32_t hx3695_gpioint_disable(void);\r
-uint32_t gsen_read_timers_start(void);\r
+void hx3695_agc_Int_handle(ppg_sensor_data_t *ppg_sensor_dat);\r
+void hx3695_ppg_Int_handle(ppg_sensor_data_t *ppg_sensor_dat);\r
+void heart_rate_meas_timeout_handler(void *p_context);\r
+void agc_timeout_handler(void *p_context);\r
+void hx3695_alg_send_data(ppg_sensor_data_t *ppg_sensor_dat, WORK_MODE_T mode, uint8_t data_count);\r
+uint32_t hx3695_320ms_timers_stop(void);\r
+uint32_t hx3695_320ms_timers_start(void);\r
uint32_t gsen_read_timers_stop(void);\r
-bool Efuse_judge(void);\r
-void hx3695_vin_check(uint16_t led_vin);\r
-void nrf_gpioint_handle(void);\r
-#ifdef LAB_TEST\r
-void hx3695_lab_test_init(void);\r
-void hx3695_test_alg_cfg(void);\r
-SENSOR_ERROR_T hx3695_lab_test_enable(void);\r
-void hx3695_lab_test_Int_handle(void);\r
-NOISE_PS_T hx3695_lab_test_read_packet(void);\r
-#endif\r
+uint32_t gsen_read_timers_start(void);\r
\r
-bool hx3695_living_send_data(int32_t *new_raw_data, uint8_t dat_len, int16_t *gsen_data_x, int16_t *gsen_data_y, int16_t *gsen_data_z);\r
-hx3695_living_results_t hx3695_living_get_results(void);\r
-void agc_timeout_handler(void * p_context);\r
-void heart_rate_meas_timeout_handler(void * p_context);\r
void wear_mode_timeout_handler(void * p_context);\r
-void Efuse_Mode_Check(void);\r
void hx3695_wearstatus_update(void);\r
void hx3695_unwearstatus_update(void);\r
void hx3695_set_hrs_ble_swtich(uint8_t cmd);\r
uint8_t hx3695_get_spo2(void);\r
uint8_t hx3695_get_wear_status(void);\r
int32_t hx3695_get_factory_data(void);\r
-\r
+void hx3695_control(char *mode,uint8_t enable);\r
#endif\r
--- /dev/null
+#include <stdio.h>\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include <stdlib.h>\r
+\r
+#include "hx3695.h"\r
+#include "hx3695_agc.h"\r
+#include "tyhx_spo2_alg.h"\r
+#include "tyhx_hrs_alg.h"\r
+\r
+extern uint8_t read_fifo_first_flg;\r
+extern uint8_t s_ppg_state;\r
+extern uint8_t s_cal_state;\r
+static int32_t agc_buf[8] = {0};\r
+static agc_set_t calReg;\r
+\r
+void hx3695_agc_reset(void)\r
+{\r
+ calReg.STATE = sCalStart;\r
+ calReg.FLAG = CAL_FLG_LED_DR|CAL_FLG_LED_DAC|CAL_FLG_AMB_DAC|CAL_FLG_RF;\r
+\r
+ calReg.LED0_IDAC = 0;\r
+ calReg.LED1_IDAC = 0;\r
+ calReg.LED2_IDAC = 0;\r
+ calReg.LED3_IDAC = 0;\r
+ calReg.AMB0_IDAC = 0;\r
+ calReg.AMB1_IDAC = 0;\r
+ calReg.AMB2_IDAC = 0;\r
+ calReg.AMB3_IDAC = 0;\r
+\r
+ calReg.LED0_RF = 0;\r
+ calReg.LED1_RF = 0;\r
+ calReg.LED2_RF = 0;\r
+ calReg.LED3_RF = 0;\r
+\r
+ calReg.LED0_CUR = 0;\r
+ calReg.LED1_CUR = 0;\r
+ calReg.LED2_CUR = 0;\r
+ calReg.LED3_CUR = 0;\r
+\r
+ calReg.CAL_DELAY_CNT = 0;\r
+}\r
+\r
+void Init_PPG_Calibration_Routine(agc_set_t *calR)\r
+{\r
+ calR->STATE = sCalStart;\r
+ calR->FLAG = CAL_FLG_LED_DR|CAL_FLG_LED_DAC|CAL_FLG_AMB_DAC|CAL_FLG_RF;\r
+\r
+ if(AGC_SWI_LED0)\r
+ {\r
+ calR->LED0_IDAC = 0;\r
+ calR->AMB0_IDAC = 0;\r
+ calR->LED0_RF = 0;\r
+ calR->LED0_CUR = AGC_CUR_INIT_LED0;\r
+ }\r
+ if(AGC_SWI_LED1)\r
+ {\r
+ calR->LED1_IDAC = 0;\r
+ calR->AMB1_IDAC = 0;\r
+ calR->LED1_RF = 0;\r
+ calR->LED1_CUR = AGC_CUR_INIT_LED1;\r
+ }\r
+ if(AGC_SWI_LED2)\r
+ {\r
+ calR->LED2_IDAC = 0;\r
+ calR->AMB2_IDAC = 0;\r
+ calR->LED2_RF = 0;\r
+ calR->LED2_CUR = AGC_CUR_INIT_LED2;\r
+ }\r
+ if(AGC_SWI_LED3)\r
+ {\r
+ calR->LED3_IDAC = 0;\r
+ calR->AMB3_IDAC = 0;\r
+ calR->LED3_RF = 0;\r
+ calR->LED3_CUR = AGC_CUR_INIT_LED3;\r
+ }\r
+}\r
+\r
+void Restart_PPG_Calibration_Routine(agc_set_t *calR)\r
+{\r
+ calR->FLAG = CAL_FLG_LED_DAC;\r
+ calR->STATE = sCalOffset1;\r
+}\r
+\r
+void PPG_Calibration_Routine(ppg_sensor_data_t *ppg_sensor_dat, agc_set_t *calR, int32_t amb0_val, int32_t led0_val, \\r
+ int32_t amb1_val, int32_t led1_val, int32_t amb2_val, int32_t led2_val, int32_t amb3_val, int32_t led3_val)\r
+{\r
+ int32_t led0_cur_temp = 0;\r
+ int32_t led1_cur_temp = 0;\r
+ int32_t led2_cur_temp = 0;\r
+ int32_t led3_cur_temp = 0;\r
+\r
+ switch(calR->STATE)\r
+ {\r
+ case sCalStart:\r
+ {\r
+ calR->STATE = sCalCur;\r
+ break;\r
+ }\r
+ case sCalCur:\r
+ {\r
+ if(AGC_SWI_LED0 && ppg_sensor_dat->led_data[0].isneed_cal_start==1)\r
+ {\r
+ ppg_sensor_dat->led_data[0].isneed_cal_start = 0;\r
+ if(amb0_val > 535000)\r
+ {\r
+ calR->AMB0_IDAC = (amb0_val - 535000)/1250;\r
+ }\r
+ else\r
+ {\r
+ calR->AMB0_IDAC = 0;\r
+ }\r
+ if(led0_val > (amb0_val+256))\r
+ {\r
+ calR->LED0_STEP = (led0_val - amb0_val) / AGC_CUR_INIT_LED0;\r
+ led0_cur_temp = 1250 * (AGC_IDAC_TARGET_LED0 + calR->AMB0_IDAC) / calR->LED0_STEP;\r
+\r
+ if(led0_cur_temp > AGC_CUR_MAX_LED0)\r
+ {\r
+ calR->LED0_CUR = AGC_CUR_MAX_LED0;\r
+ }\r
+ else\r
+ {\r
+ calR->LED0_CUR = led0_cur_temp;\r
+ }\r
+\r
+ if(calR->LED0_CUR != AGC_CUR_MAX_LED0)\r
+ {\r
+ calR->LED0_IDAC = (AGC_IDAC_TARGET_LED0*3)>>2;\r
+ }\r
+ else\r
+ {\r
+ calR->LED0_IDAC = AGC_IDAC_TARGET_LED0>>1;\r
+ }\r
+ }\r
+ calR->LED0_RF = AGC_RF_LED0;\r
+ }\r
+ #ifdef DOUBLE_GREEN\r
+ if(ppg_sensor_dat->mode == HRS_MODE)\r
+ {\r
+ if(AGC_SWI_LED1 && ppg_sensor_dat->led_data[1].isneed_cal_start==1)\r
+ {\r
+ ppg_sensor_dat->led_data[1].isneed_cal_start = 0;\r
+ if(amb1_val > 535000)\r
+ {\r
+ calR->AMB1_IDAC = (amb1_val - 535000)/1250;\r
+ }\r
+ else\r
+ {\r
+ calR->AMB1_IDAC = 0;\r
+ }\r
+ if(led1_val > (amb1_val+256))\r
+ {\r
+ calR->LED1_STEP = (led1_val - amb1_val) / AGC_CUR_INIT_LED1;\r
+ led1_cur_temp = 1250 * (AGC_IDAC_TARGET_LED1N + calR->AMB1_IDAC) / calR->LED1_STEP;\r
+\r
+ if(led1_cur_temp > AGC_CUR_MAX_LED1N)\r
+ {\r
+ calR->LED1_CUR = AGC_CUR_MAX_LED1N;\r
+ }\r
+ else\r
+ {\r
+ calR->LED1_CUR = led1_cur_temp;\r
+ }\r
+\r
+ if(calR->LED1_CUR != AGC_CUR_MAX_LED1N)\r
+ {\r
+ calR->LED1_IDAC = (AGC_IDAC_TARGET_LED1N*3)>>2;\r
+ }\r
+ else\r
+ {\r
+ calR->LED1_IDAC = AGC_IDAC_TARGET_LED1N>>1;\r
+ }\r
+ }\r
+ calR->LED1_RF = AGC_RF_LED1N;\r
+ }\r
+ }\r
+ else\r
+ #endif\r
+ {\r
+ if(AGC_SWI_LED1 && ppg_sensor_dat->led_data[1].isneed_cal_start==1)\r
+ {\r
+ ppg_sensor_dat->led_data[1].isneed_cal_start = 0;\r
+ if(amb1_val > 535000)\r
+ {\r
+ calR->AMB1_IDAC = (amb1_val - 535000)/1250;\r
+ }\r
+ else\r
+ {\r
+ calR->AMB1_IDAC = 0;\r
+ }\r
+ if(led1_val > (amb1_val+256))\r
+ {\r
+ calR->LED1_STEP = (led1_val - amb1_val) / AGC_CUR_INIT_LED1;\r
+ led1_cur_temp = 1250 * (AGC_IDAC_TARGET_LED1 + calR->AMB1_IDAC) / calR->LED1_STEP;\r
+\r
+ if(led1_cur_temp > AGC_CUR_MAX_LED1)\r
+ {\r
+ calR->LED1_CUR = AGC_CUR_MAX_LED1;\r
+ }\r
+ else\r
+ {\r
+ calR->LED1_CUR = led1_cur_temp;\r
+ }\r
+\r
+ if(calR->LED1_CUR != AGC_CUR_MAX_LED1)\r
+ {\r
+ calR->LED1_IDAC = (AGC_IDAC_TARGET_LED1*3)>>2;\r
+ }\r
+ else\r
+ {\r
+ calR->LED1_IDAC = AGC_IDAC_TARGET_LED1>>1;\r
+ }\r
+ }\r
+ calR->LED1_RF = AGC_RF_LED1;\r
+ }\r
+ }\r
+\r
+ if(AGC_SWI_LED2 && ppg_sensor_dat->led_data[2].isneed_cal_start==1)\r
+ {\r
+ ppg_sensor_dat->led_data[2].isneed_cal_start = 0;\r
+ if(amb2_val > 535000)\r
+ {\r
+ calR->AMB2_IDAC = (amb2_val - 535000)/1250;\r
+ }\r
+ else\r
+ {\r
+ calR->AMB2_IDAC = 0;\r
+ }\r
+ if(led2_val > (amb2_val+256))\r
+ {\r
+ calR->LED2_STEP = (led2_val - amb2_val) / AGC_CUR_INIT_LED2;\r
+ led2_cur_temp = 1250 * (AGC_IDAC_TARGET_LED2 + calR->AMB2_IDAC) / calR->LED2_STEP;\r
+\r
+ if(led2_cur_temp > AGC_CUR_MAX_LED2)\r
+ {\r
+ calR->LED2_CUR = AGC_CUR_MAX_LED2;\r
+ }\r
+ else\r
+ {\r
+ calR->LED2_CUR = led2_cur_temp;\r
+ }\r
+\r
+ if(calR->LED2_CUR != AGC_CUR_MAX_LED2)\r
+ {\r
+ calR->LED2_IDAC = (AGC_IDAC_TARGET_LED2*3)>>2;\r
+ }\r
+ else\r
+ {\r
+ calR->LED2_IDAC = AGC_IDAC_TARGET_LED2>>1;\r
+ }\r
+ }\r
+ calR->LED2_RF = AGC_RF_LED2;\r
+ }\r
+\r
+ if(AGC_SWI_LED3 && ppg_sensor_dat->led_data[3].isneed_cal_start==1)\r
+ {\r
+ ppg_sensor_dat->led_data[3].isneed_cal_start = 0;\r
+ if(amb3_val > 535000)\r
+ {\r
+ calR->AMB3_IDAC = (amb3_val - 535000)/1250;\r
+ }\r
+ else\r
+ {\r
+ calR->AMB3_IDAC = 0;\r
+ }\r
+ if(led3_val > (amb3_val+256))\r
+ {\r
+ calR->LED3_STEP = (led3_val - amb3_val) / AGC_CUR_INIT_LED3;\r
+ led3_cur_temp = 1250 * (AGC_IDAC_TARGET_LED3 + calR->AMB3_IDAC) / calR->LED3_STEP;\r
+\r
+ if(led3_cur_temp > AGC_CUR_MAX_LED3)\r
+ {\r
+ calR->LED3_CUR = AGC_CUR_MAX_LED3;\r
+ }\r
+ else\r
+ {\r
+ calR->LED3_CUR = led3_cur_temp;\r
+ }\r
+\r
+ if(calR->LED3_CUR != AGC_CUR_MAX_LED3)\r
+ {\r
+ calR->LED3_IDAC = (AGC_IDAC_TARGET_LED3*3)>>2;\r
+ }\r
+ else\r
+ {\r
+ calR->LED3_IDAC =AGC_IDAC_TARGET_LED3>>1;\r
+ }\r
+ }\r
+ calR->LED3_RF = AGC_RF_LED3;\r
+ }\r
+\r
+ calR->FLAG = CAL_FLG_LED_DR|CAL_FLG_LED_DAC|CAL_FLG_AMB_DAC|CAL_FLG_RF;\r
+ calR->STATE = sCalOffset1;\r
+ break;\r
+ }\r
+ case sCalOffset1:\r
+ {\r
+ if(AGC_SWI_LED0 && ppg_sensor_dat->led_data[0].led_state == Activated)\r
+ {\r
+ if(led0_val>850000 && calR->LED0_IDAC < 240)\r
+ {\r
+ calR->LED0_IDAC = calR->LED0_IDAC+10;\r
+ }\r
+ }\r
+ if(AGC_SWI_LED1 && ppg_sensor_dat->led_data[1].led_state == Activated)\r
+ {\r
+ if(led1_val>850000 && calR->LED1_IDAC < 240)\r
+ {\r
+ calR->LED1_IDAC = calR->LED1_IDAC+10;\r
+ }\r
+ }\r
+ if(AGC_SWI_LED2 && ppg_sensor_dat->led_data[2].led_state == Activated)\r
+ {\r
+ if(led2_val>850000 && calR->LED2_IDAC < 240)\r
+ {\r
+ calR->LED2_IDAC = calR->LED2_IDAC+10;\r
+ }\r
+ }\r
+ if(AGC_SWI_LED3 && ppg_sensor_dat->led_data[3].led_state == Activated)\r
+ {\r
+ if(led3_val>850000 && calR->LED3_IDAC < 240)\r
+ {\r
+ calR->LED3_IDAC = calR->LED3_IDAC+10;\r
+ }\r
+ }\r
+\r
+ if ((!AGC_SWI_LED0 || ppg_sensor_dat->led_data[0].led_state == InActivated || led0_val<=850000) \\r
+ &&(!AGC_SWI_LED1 || ppg_sensor_dat->led_data[1].led_state == InActivated || led1_val<=850000) \\r
+ &&(!AGC_SWI_LED2 || ppg_sensor_dat->led_data[2].led_state == InActivated || led2_val<=850000) \\r
+ &&(!AGC_SWI_LED3 || ppg_sensor_dat->led_data[3].led_state == InActivated || led3_val<=850000) )\r
+ {\r
+ calR->STATE = sCalOffset2;\r
+ }\r
+ else if(calR->LED0_IDAC >= 240 || calR->LED1_IDAC >= 240 || calR->LED2_IDAC >= 240 || calR->LED3_IDAC >= 240)\r
+ {\r
+ calR->STATE = sCalErr;\r
+ }\r
+ else\r
+ {\r
+ calR->STATE = sCalOffset1;\r
+ }\r
+ calR->FLAG = CAL_FLG_LED_DAC;\r
+ break;\r
+ }\r
+ case sCalOffset2:\r
+ {\r
+ if(AGC_SWI_LED0 && ppg_sensor_dat->led_data[0].led_state == Activated)\r
+ {\r
+ if(led0_val > 650000 && calR->LED0_IDAC < 240)\r
+ {\r
+ calR->LED0_IDAC = calR->LED0_IDAC+5;\r
+ }\r
+ else if(led0_val <450000 && calR->LED0_IDAC >= 5)\r
+ {\r
+ calR->LED0_IDAC = calR->LED0_IDAC-5;\r
+ }\r
+ else if(led0_val<450000 && calR->LED0_IDAC > 0)\r
+ {\r
+ calR->LED0_IDAC = calR->LED0_IDAC-1;\r
+ }\r
+ }\r
+ if(AGC_SWI_LED1 && ppg_sensor_dat->led_data[1].led_state == Activated)\r
+ {\r
+ if(led1_val > 650000 && calR->LED1_IDAC < 240)\r
+ {\r
+ calR->LED1_IDAC = calR->LED1_IDAC+5;\r
+ }\r
+ else if(led1_val <450000 && calR->LED1_IDAC >= 5)\r
+ {\r
+ calR->LED1_IDAC = calR->LED1_IDAC-5;\r
+ }\r
+ else if(led1_val<450000 && calR->LED1_IDAC > 0)\r
+ {\r
+ calR->LED1_IDAC = calR->LED1_IDAC-1;\r
+ }\r
+ }\r
+ if(AGC_SWI_LED2 && ppg_sensor_dat->led_data[2].led_state == Activated)\r
+ {\r
+ if(led2_val > 650000 && calR->LED2_IDAC < 240)\r
+ {\r
+ calR->LED2_IDAC = calR->LED2_IDAC+5;\r
+ }\r
+ else if(led2_val <450000 && calR->LED2_IDAC >= 5)\r
+ {\r
+ calR->LED2_IDAC = calR->LED2_IDAC-5;\r
+ }\r
+ else if(led2_val<450000 && calR->LED2_IDAC > 0)\r
+ {\r
+ calR->LED2_IDAC = calR->LED2_IDAC-1;\r
+ }\r
+ }\r
+ if(AGC_SWI_LED3 && ppg_sensor_dat->led_data[3].led_state == Activated)\r
+ {\r
+ if(led3_val > 650000 && calR->LED3_IDAC < 240)\r
+ {\r
+ calR->LED3_IDAC = calR->LED3_IDAC+5;\r
+ }\r
+ else if(led3_val <450000 && calR->LED3_IDAC >= 5)\r
+ {\r
+ calR->LED3_IDAC = calR->LED3_IDAC-5;\r
+ }\r
+ else if(led3_val<450000 && calR->LED3_IDAC > 0)\r
+ {\r
+ calR->LED3_IDAC = calR->LED3_IDAC-1;\r
+ }\r
+ }\r
+\r
+ if ((!AGC_SWI_LED0 || ppg_sensor_dat->led_data[0].led_state == InActivated || (led0_val>=450000 && led0_val<=650000))\\r
+ &&(!AGC_SWI_LED1 || ppg_sensor_dat->led_data[1].led_state == InActivated || (led1_val>=450000 && led1_val<=650000))\\r
+ &&(!AGC_SWI_LED2 || ppg_sensor_dat->led_data[2].led_state == InActivated || (led2_val>=450000 && led2_val<=650000))\\r
+ &&(!AGC_SWI_LED3 || ppg_sensor_dat->led_data[3].led_state == InActivated || (led3_val>=450000 && led3_val<=650000)))\r
+ {\r
+ calR->STATE = sCalFinish;\r
+ }\r
+ else if(calR->LED0_IDAC >= 240 || calR->LED1_IDAC >= 240 || calR->LED2_IDAC >= 240 || calR->LED3_IDAC >= 240)\r
+ {\r
+ calR->STATE = sCalErr;\r
+ }\r
+ else\r
+ {\r
+ calR->STATE = sCalOffset2;\r
+ }\r
+ calR->FLAG = CAL_FLG_LED_DAC;\r
+ break;\r
+ }\r
+ case sCalErr:\r
+ {\r
+ calR->STATE = sCalFinish;\r
+ break;\r
+ }\r
+ default:\r
+ {\r
+ break;\r
+ }\r
+\r
+ }\r
+ hx3695_agc_updata_reg(calR);\r
+ //DEBUG_PRINTF("AGC:cur=%d,%d,%d,%d, idac=%d,%d,%d,%d, step=%d,%d,%d,%d, state=%d \r\n",calR->LED0_CUR,calR->LED1_CUR,calR->LED2_CUR,calR->LED3_CUR,calR->LED0_IDAC,calR->LED1_IDAC,calR->LED2_IDAC,calR->LED3_IDAC,calR->LED0_STEP,calR->LED1_STEP,calR->LED2_STEP,calR->LED3_STEP,calR->STATE);\r
+}\r
+\r
+void hx3695_agc_process(ppg_sensor_data_t *ppg_sensor_dat)\r
+{\r
+ if (!s_cal_state && s_ppg_state)\r
+ {\r
+ hx3695_read_led_data(agc_buf);\r
+\r
+ if ((AGC_SWI_LED0 && ppg_sensor_dat->led_data[0].led_state==Activated && (agc_buf[0]<250000 || agc_buf[0]>850000))\\r
+ ||(AGC_SWI_LED1 && ppg_sensor_dat->led_data[1].led_state==Activated && (agc_buf[1]<250000 || agc_buf[1]>850000))\\r
+ ||(AGC_SWI_LED2 && ppg_sensor_dat->led_data[2].led_state==Activated && (agc_buf[2]<250000 || agc_buf[2]>850000))\\r
+ ||(AGC_SWI_LED3 && ppg_sensor_dat->led_data[3].led_state==Activated && (agc_buf[3]<250000 || agc_buf[3]>850000)))\r
+ {\r
+ calReg.CAL_DELAY_CNT++;\r
+ if(calReg.CAL_DELAY_CNT >= AGC_DELAY_COUNT_SET)\r
+ {\r
+ hx3695_ppg_set_mode(RECAL_INIT);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ calReg.CAL_DELAY_CNT = 0;\r
+ }\r
+ return;\r
+ }\r
+\r
+ hx3695_read_phase_data(agc_buf);\r
+\r
+ PPG_Calibration_Routine(ppg_sensor_dat,&calReg,agc_buf[0],agc_buf[1],agc_buf[2],agc_buf[3],agc_buf[4],agc_buf[5],agc_buf[6],agc_buf[7]);\r
+\r
+ if (calReg.STATE == sCalFinish)\r
+ {\r
+ hx3695_ppg_set_mode(CAL_OFF);\r
+ }\r
+}\r
+\r
+void hx3695_cal_init(void)\r
+{\r
+ hx3695_write_reg(0x1b,0x10);\r
+ hx3695_write_reg(0x38,0x01);\r
+ hx3695_write_reg(0x60,0x34);\r
+\r
+ hx3695_write_reg(0x5c,0x02);\r
+ hx3695_delay_ms(1);\r
+ hx3695_write_reg(0x5c,0x00);\r
+ hx3695_delay_ms(1);\r
+ \r
+ Init_PPG_Calibration_Routine(&calReg);\r
+ hx3695_agc_updata_reg(&calReg);\r
+}\r
+\r
+void hx3695_recal_init(void)\r
+{\r
+ hx3695_write_reg(0x1b,0x10);\r
+ hx3695_write_reg(0x38,0x01);\r
+ hx3695_write_reg(0x60,0x34);\r
+\r
+ hx3695_write_reg(0x5c,0x02);\r
+ hx3695_delay_ms(1);\r
+ hx3695_write_reg(0x5c,0x00);\r
+ hx3695_delay_ms(1);\r
+ \r
+ Restart_PPG_Calibration_Routine(&calReg);\r
+ hx3695_agc_updata_reg(&calReg);\r
+}\r
+\r
+void hx3695_cal_off(void)\r
+{\r
+ hx3695_write_reg(0x38,0x04);\r
+ hx3695_write_reg(0x60,0x14);\r
+\r
+ hx3695_write_reg(0x5c,0x02);\r
+ hx3695_delay_ms(1);\r
+ hx3695_write_reg(0x1b,0x91);\r
+ hx3695_write_reg(0x5c,0x00);\r
+ hx3695_delay_ms(1);\r
+ read_fifo_first_flg = 1;\r
+}\r
+\r
+void hx3695_agc_updata_reg(agc_set_t *calR)\r
+{\r
+ uint8_t phase1_mux_sel = 0;\r
+ uint8_t phase2_mux_sel = 1;\r
+ uint8_t phase3_mux_sel = 2;\r
+ uint8_t phase4_mux_sel = 3;\r
+ uint8_t phase5_mux_sel = 4;\r
+ uint8_t phase6_mux_sel = 5;\r
+ uint8_t phase7_mux_sel = 6;\r
+ uint8_t phase8_mux_sel = 7;\r
+\r
+ if (calR->FLAG & CAL_FLG_LED_DR)\r
+ {\r
+ if(AGC_SWI_LED0)\r
+ {\r
+ hx3695_write_reg(0X43, phase2_mux_sel);\r
+ hx3695_write_reg(0X45, calR->LED0_CUR/2);\r
+ hx3695_write_reg(0X70, calR->LED0_CUR/2);\r
+ }\r
+ if(AGC_SWI_LED1)\r
+ {\r
+ hx3695_write_reg(0X43, phase4_mux_sel);\r
+ hx3695_write_reg(0X45, calR->LED1_CUR/2);\r
+ hx3695_write_reg(0X70, calR->LED1_CUR/2);\r
+ }\r
+ if(AGC_SWI_LED2)\r
+ {\r
+ hx3695_write_reg(0X43, phase6_mux_sel);\r
+ hx3695_write_reg(0X45, calR->LED2_CUR);\r
+ }\r
+ if(AGC_SWI_LED3)\r
+ {\r
+ hx3695_write_reg(0X43, phase8_mux_sel);\r
+ hx3695_write_reg(0X45, calR->LED3_CUR);\r
+ }\r
+ }\r
+\r
+ if (calR->FLAG & CAL_FLG_LED_DAC)\r
+ {\r
+ if(AGC_SWI_LED0)\r
+ {\r
+ hx3695_write_reg(0X43, phase2_mux_sel);\r
+ hx3695_write_reg(0X48, calR->LED0_IDAC);\r
+ }\r
+ if(AGC_SWI_LED1)\r
+ {\r
+ hx3695_write_reg(0X43, phase4_mux_sel);\r
+ hx3695_write_reg(0X48, calR->LED1_IDAC);\r
+ }\r
+ if(AGC_SWI_LED2)\r
+ {\r
+ hx3695_write_reg(0X43, phase6_mux_sel);\r
+ hx3695_write_reg(0X48, calR->LED2_IDAC);\r
+ }\r
+ if(AGC_SWI_LED3)\r
+ {\r
+ hx3695_write_reg(0X43, phase8_mux_sel);\r
+ hx3695_write_reg(0X48, calR->LED3_IDAC);\r
+ }\r
+ }\r
+\r
+ if (calR->FLAG & CAL_FLG_AMB_DAC)\r
+ {\r
+ if(AGC_SWI_LED0)\r
+ {\r
+ hx3695_write_reg(0X43, phase1_mux_sel);\r
+ hx3695_write_reg(0X48, calR->AMB0_IDAC);\r
+ }\r
+ if(AGC_SWI_LED1)\r
+ {\r
+ hx3695_write_reg(0X43, phase3_mux_sel);\r
+ hx3695_write_reg(0X48, calR->AMB1_IDAC);\r
+ }\r
+ if(AGC_SWI_LED2)\r
+ {\r
+ hx3695_write_reg(0X43, phase5_mux_sel);\r
+ hx3695_write_reg(0X48, calR->AMB2_IDAC);\r
+ }\r
+ if(AGC_SWI_LED3)\r
+ {\r
+ hx3695_write_reg(0X43, phase7_mux_sel);\r
+ hx3695_write_reg(0X48, calR->AMB3_IDAC);\r
+ }\r
+ }\r
+\r
+ if (calR->FLAG & CAL_FLG_RF)\r
+ {\r
+ if(AGC_SWI_LED0)\r
+ {\r
+ hx3695_write_reg(0X43, phase1_mux_sel);\r
+ hx3695_write_reg(0X44, (0x40 | calR->LED0_RF));\r
+ hx3695_write_reg(0X43, phase2_mux_sel);\r
+ hx3695_write_reg(0X44, (0x40 | calR->LED0_RF));\r
+ }\r
+ if(AGC_SWI_LED1)\r
+ {\r
+ hx3695_write_reg(0X43, phase3_mux_sel);\r
+ hx3695_write_reg(0X44, (0x40 | calR->LED1_RF));\r
+ hx3695_write_reg(0X43, phase4_mux_sel);\r
+ hx3695_write_reg(0X44, (0x40 | calR->LED1_RF));\r
+ }\r
+ if(AGC_SWI_LED2)\r
+ {\r
+ hx3695_write_reg(0X43, phase5_mux_sel);\r
+ hx3695_write_reg(0X44, (0x40 | calR->LED2_RF));\r
+ hx3695_write_reg(0X43, phase6_mux_sel);\r
+ hx3695_write_reg(0X44, (0x40 | calR->LED2_RF));\r
+ }\r
+ if(AGC_SWI_LED3)\r
+ {\r
+ hx3695_write_reg(0X43, phase7_mux_sel);\r
+ hx3695_write_reg(0X44, (0x40 | calR->LED3_RF));\r
+ hx3695_write_reg(0X43, phase8_mux_sel);\r
+ hx3695_write_reg(0X44, (0x40 | calR->LED3_RF));\r
+ }\r
+ }\r
+}\r
--- /dev/null
+#ifndef _HX3695_SPO2_AGC_H_\r
+#define _HX3695_SPO2_AGC_H_\r
+#include <stdint.h>\r
+#include <stdbool.h>\r
+\r
+#define CAL_FLG_LED_DR 0x01\r
+#define CAL_FLG_LED_DAC 0x02\r
+#define CAL_FLG_AMB_DAC 0x04\r
+#define CAL_FLG_RF 0x08\r
+\r
+#define AGC_SWI_LED0 1 //LEDÊÇ·ñÐèÒªµ÷¹â\r
+#define AGC_SWI_LED1 1\r
+#define AGC_SWI_LED2 1\r
+#define AGC_SWI_LED3 0\r
+\r
+#define AGC_CUR_INIT_LED0 64 //LEDµ÷¹â³õʼµçÁ÷\r
+#define AGC_CUR_INIT_LED1 64\r
+#define AGC_CUR_INIT_LED2 64\r
+#define AGC_CUR_INIT_LED3 64\r
+\r
+#define AGC_CUR_MAX_LED0 450 //LEDµ÷¹â×î´óµçÁ÷\r
+#define AGC_CUR_MAX_LED1 255\r
+#define AGC_CUR_MAX_LED2 255\r
+#define AGC_CUR_MAX_LED3 255\r
+#define AGC_CUR_MAX_LED1N 450\r
+\r
+#define AGC_RF_LED0 3 //LEDµ÷¹âÔöÒæ,0=10k,1=20k,2=50k,3=100k,4=150k,5=200k,6=500k,7=1M\r
+#define AGC_RF_LED1 3\r
+#define AGC_RF_LED2 3\r
+#define AGC_RF_LED3 0\r
+#define AGC_RF_LED1N 5\r
+\r
+#define AGC_IDAC_TARGET_LED0 20 //µ÷¹âÄ¿±êoffset\r
+#define AGC_IDAC_TARGET_LED1 160\r
+#define AGC_IDAC_TARGET_LED2 160\r
+#define AGC_IDAC_TARGET_LED3 0\r
+#define AGC_IDAC_TARGET_LED1N 20\r
+\r
+#define AGC_DELAY_COUNT_SET 4 //µ÷¹âÑÓʱ,N¸ö¶¨Ê±Æ÷»òÖжÏ\r
+\r
+typedef enum {\r
+ sCalStart,\r
+ sCalCur,\r
+ sCalOffset1,\r
+ sCalOffset2,\r
+ sCalFinish,\r
+ sCalErr,\r
+} agc_state_t;\r
+\r
+typedef struct {\r
+ uint8_t FLAG;\r
+ uint16_t LED0_IDAC;\r
+ uint16_t LED1_IDAC;\r
+ uint16_t LED2_IDAC;\r
+ uint16_t LED3_IDAC;\r
+ uint16_t AMB0_IDAC;\r
+ uint16_t AMB1_IDAC;\r
+ uint16_t AMB2_IDAC;\r
+ uint16_t AMB3_IDAC;\r
+ uint16_t LED0_CUR;\r
+ uint16_t LED1_CUR;\r
+ uint16_t LED2_CUR;\r
+ uint16_t LED3_CUR;\r
+ uint8_t LED0_RF;\r
+ uint8_t LED1_RF;\r
+ uint8_t LED2_RF;\r
+ uint8_t LED3_RF;\r
+ uint32_t LED0_STEP;\r
+ uint32_t LED1_STEP;\r
+ uint32_t LED2_STEP;\r
+ uint32_t LED3_STEP;\r
+ uint8_t CAL_DELAY_CNT;\r
+ agc_state_t STATE;\r
+} agc_set_t;\r
+\r
+void hx3695_agc_reset(void);\r
+void Init_PPG_Calibration_Routine(agc_set_t *calR);\r
+void Restart_PPG_Calibration_Routine(agc_set_t *calR);\r
+void PPG_Calibration_Routine(ppg_sensor_data_t *ppg_sensor_data, agc_set_t *calR, int32_t amb0_val, int32_t led0_val, \\r
+ int32_t amb1_val, int32_t led1_val, int32_t amb2_val, int32_t led2_val, int32_t amb3_val, int32_t led3_val);\r
+void hx3695_agc_process(ppg_sensor_data_t *ppg_sensor);\r
+void hx3695_cal_init(void);\r
+void hx3695_recal_init(void);\r
+void hx3695_cal_off(void);\r
+void hx3695_agc_updata_reg(agc_set_t *calR);\r
+\r
+#endif\r
#include "hx3695.h"\r
#include "hx3695_factory_test.h"\r
\r
+int32_t phase_result[10][8];\r
+\r
static uint32_t factory_green = 0;\r
static uint32_t factory_red = 0;\r
static uint32_t factory_ir = 0;\r
\r
-void hx3695_factory_wear_mode_config(void)\r
+void hx3695_factory_ft_card_test_config(void)//�ҿ�15mm�߶Ȳ�������\r
{\r
- uint16_t sample_rate = 10; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
+ uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */\r
\r
- uint8_t adc_rst_post_num=0; /* 00=16,01=32,10=64,11=128*/ \r
- uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
+ uint16_t fifo_watermark= 250 ;\r
+ uint8_t adc_rst_post_num= 0; /* 00=16,01=32,10=64,11=128*/ \r
+ uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/\r
uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/\r
- uint8_t phase7_8_internal = 0; /* phase7 and phase8 prf internal cfg */\r
- \r
+ uint8_t phase7_8_internal = 0; //0x18; /* phase7 and phase8 prf internal cfg */\r
+ \r
+// uint16_t thred_value = 32500;\r
+ \r
uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase3_enable = 0; /*phase3_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase4_enable = 0; /*phase4_enable , 1 mean enable ; 0 mean disable */\r
- uint8_t phase5_enable = 0; /*phase5_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase6_enable = 0; /*phase6_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase7_enable = 0; /*phase7_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase8_enable = 0; /*phase8_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */\r
+ uint8_t phase5_enable = 1; /*phase5_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase6_enable = 1; /*phase6_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase7_enable = 1; /*phase7_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ \r
\r
uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
\r
- uint8_t phase1_mux_sel = 0; /* sel phase1*/\r
- uint8_t phase2_mux_sel = 1; /* sel phase2*/\r
- uint8_t phase3_mux_sel = 2; /* sel phase3*/\r
- uint8_t phase4_mux_sel = 3; /* sel phase4*/\r
- uint8_t phase5_mux_sel = 4; /* sel phase5*/\r
- uint8_t phase6_mux_sel = 5; /* sel phase6*/\r
- uint8_t phase7_mux_sel = 6; /* sel phase7*/\r
- uint8_t phase8_mux_sel = 7; /* sel phase8*/\r
+ uint8_t phase1_mux_sel = 0; /* sel phase1*/\r
+ uint8_t phase2_mux_sel = 1; /* sel phase2*/\r
+ uint8_t phase3_mux_sel = 2; /* sel phase3*/\r
+ uint8_t phase4_mux_sel = 3; /* sel phase4*/\r
+ uint8_t phase5_mux_sel = 4; /* sel phase5*/\r
+ uint8_t phase6_mux_sel = 5; /* sel phase6*/\r
+ uint8_t phase7_mux_sel = 6; /* sel phase7*/\r
+ uint8_t phase8_mux_sel = 7; /* sel phase8*/\r
\r
-\r
- uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase1_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase1_led_drv1_cha_sel = 0x10; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */\r
+ uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ uint8_t phase1_tia_res = PS_GRAD_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */\r
uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */\r
- uint8_t phase1_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase1_pd_sel = ALS_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase1_ldr1_cur = 64; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase1_ldr2_cur = 0;\r
-// uint8_t phase1_of_idac1_cur = 0;\r
-// uint8_t phase1_of_idac2_cur = 0;\r
+ uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase1_ldr2_cur = 0;\r
uint8_t phase1_ad_inr_ctrl = 3;\r
uint8_t phase1_ad_of_idac_ctrl = 0;\r
-// uint8_t afe_offset = 0;\r
uint8_t phase1_led_en = 1; /* phase1 led enable*/\r
\r
- uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
-\r
-\r
- uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase2_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase2_led_drv1_cha_sel = 0; //GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase2_led_drv2_cha_sel = 0;\r
- uint8_t phase2_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ uint8_t phase2_tia_res = PS_GRAD_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase2_led_drv1_cha_sel = LDR0_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase2_led_drv2_cha_sel = 0x00;\r
+ uint8_t phase2_pd_sel = LDR0_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase2_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase2_ldr2_cur = 0;\r
-// uint8_t phase2_of_idac1_cur = 0;\r
-// uint8_t phase2_of_idac2_cur = 0;\r
+ uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase2_ldr1_cur = DRV1_GRAD_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase2_ldr2_cur = DRV2_GRAD_CUR;\r
uint8_t phase2_ad_inr_ctrl = 3;\r
uint8_t phase2_ad_of_idac_ctrl = 0;\r
-// uint8_t phase2_afe_offset = 0;\r
- uint8_t phase2_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase2_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
\r
uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase3_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase3_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase3_tia_res = PS_GRAD_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase3_led_drv1_cha_sel = LDR1_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase3_led_drv2_cha_sel = 0;\r
- uint8_t phase3_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase3_pd_sel = LDR1_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase3_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase3_ldr2_cur = 0;\r
-// uint8_t phase3_of_idac1_cur = 0;\r
-// uint8_t phase3_of_idac2_cur = 0;\r
+ uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase3_ldr1_cur = DRV1_GRAD_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase3_ldr2_cur = DRV2_GRAD_CUR;\r
uint8_t phase3_ad_inr_ctrl = 3;\r
uint8_t phase3_ad_of_idac_ctrl = 0;\r
// uint8_t phase3_afe_offset = 0;\r
uint8_t phase3_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
\r
uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase4_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase4_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase4_tia_res = PS_GRAD_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase4_led_drv1_cha_sel = LDR2_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase4_led_drv2_cha_sel = 0;\r
- uint8_t phase4_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase4_pd_sel = LDR2_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase4_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase4_ldr2_cur = 0;\r
-// uint8_t phase4_of_idac1_cur = 0;\r
-// uint8_t phase4_of_idac2_cur = 0;\r
+ uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase4_ldr1_cur = DRV1_GRAD_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase4_ldr2_cur = DRV2_GRAD_CUR;\r
uint8_t phase4_ad_inr_ctrl = 3;\r
uint8_t phase4_ad_of_idac_ctrl = 0;\r
// uint8_t phase4_afe_offset = 0;\r
- uint8_t phase4_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase4_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase5_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase5_tia_res = PS_GRAD_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase5_led_drv1_cha_sel = LDR3_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase5_led_drv2_cha_sel = 0;\r
- uint8_t phase5_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase5_pd_sel = LDR3_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase5_ldr2_cur = 0;\r
-// uint8_t phase5_of_idac1_cur = 0;\r
-// uint8_t phase5_of_idac2_cur = 0;\r
+ uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase5_ldr1_cur = DRV1_GRAD_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase5_ldr2_cur = DRV2_GRAD_CUR;\r
uint8_t phase5_ad_inr_ctrl = 3;\r
uint8_t phase5_ad_of_idac_ctrl = 0;\r
// uint8_t phase5_afe_offset = 0;\r
- uint8_t phase5_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase5_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase6_tia_res = PS_GRAD_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase6_led_drv1_cha_sel = LDR4_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase6_led_drv2_cha_sel = 0;\r
- uint8_t phase6_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase6_pd_sel = LDR4_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase6_ldr2_cur = 0;\r
-// uint8_t phase6_of_idac1_cur = 0;\r
-// uint8_t phase6_of_idac2_cur = 0;\r
+ uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase6_ldr1_cur = DRV1_GRAD_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase6_ldr2_cur = DRV2_GRAD_CUR;\r
uint8_t phase6_ad_inr_ctrl = 3;\r
uint8_t phase6_ad_of_idac_ctrl = 0;\r
// uint8_t phase6_afe_offset = 0;\r
- uint8_t phase6_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase6_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase7_tia_res = PS_GRAD_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase7_led_drv1_cha_sel = LDR5_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase7_led_drv2_cha_sel = 0;\r
- uint8_t phase7_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase7_pd_sel = LDR5_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase7_ldr2_cur = 0;\r
-// uint8_t phase7_of_idac1_cur = 0;\r
-// uint8_t phase7_of_idac2_cur = 0;\r
+ uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase7_ldr1_cur = DRV1_GRAD_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase7_ldr2_cur = DRV2_GRAD_CUR;\r
uint8_t phase7_ad_inr_ctrl = 3;\r
uint8_t phase7_ad_of_idac_ctrl = 0;\r
// uint8_t phase7_afe_offset = 0;\r
- uint8_t phase7_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase7_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase8_led_drv1_cha_sel = 0; //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase8_tia_res = 1; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase8_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase8_led_drv2_cha_sel = 0;\r
- uint8_t phase8_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase8_pd_sel = 0; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase8_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase8_ldr2_cur = 0;\r
-// uint8_t phase8_of_idac1_cur = 0;\r
-// uint8_t phase8_of_idac2_cur = 0;\r
+ uint8_t phase8_ldr2_cur = 0;\r
uint8_t phase8_ad_inr_ctrl = 3;\r
uint8_t phase8_ad_of_idac_ctrl = 0;\r
// uint8_t phase8_afe_offset = 0;\r
- uint8_t phase8_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase8_led_en = 0; /* phase1 led enable*/ \r
+ uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
- uint8_t init_wait_delay = 5 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ;\r
+ uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ;\r
4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ \r
\r
uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ;\r
4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */\r
\r
- uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/\r
- \r
+ uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/\r
+\r
uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ \r
- \r
- uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ \r
- \r
+\r
+ uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ \r
+ \r
uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ;\r
4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */\r
\r
hx3695_delay_ms(10); \r
- \r
+ \r
hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6\r
hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8>\r
hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> \r
\r
hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); \r
- hx3695_write_reg(0X2d, phase7_8_internal); \r
- hx3695_write_reg(0X2e, 0x33);// gpio ctrl \r
+ hx3695_write_reg(0X2d, phase7_8_internal); \r
+ hx3695_write_reg(0X2e, 0x33);// gpio ctrl \r
hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay));\r
- hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
+ hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
\r
\r
hx3695_write_reg(0X31, (led_on_time<<4| 0x00));\r
- hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置；\r
- hx3695_write_reg(0X34, 0x00);// 中断特殊配置；\r
- hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置；\r
- hx3695_write_reg(0X38, 0x00);\r
+ hx3695_write_reg(0X33, 0x83);// �жϼ��Լ��������ã�\r
+ hx3695_write_reg(0X34, 0x00);// �ж��������ã�\r
+ hx3695_write_reg(0X36, 0x00);// phase data ready ��־���ã�\r
+ hx3695_write_reg(0X38, 0x00);\r
\r
hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); \r
hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); \r
hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); \r
hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num );\r
hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num );\r
- \r
- hx3695_write_reg(0X43, phase1_mux_sel); \r
- hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); \r
- hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase1_als_offset_idac);\r
- hx3695_write_reg(0X48, phase1_led_offset_idac);\r
-\r
+ hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num );\r
+ hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num );\r
+ \r
+ hx3695_write_reg(0X43, phase1_mux_sel); \r
+ hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); \r
+ hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase1_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase1_led_offset_idac);\r
hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4);\r
\r
-// hx3695_write_reg(0X4e, thred_value);\r
-// hx3695_write_reg(0X4f, thred_value>>5);\r
- \r
+ \r
hx3695_write_reg(0X43, phase2_mux_sel); \r
- hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); \r
- hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase2_als_offset_idac);\r
- hx3695_write_reg(0X48, phase2_led_offset_idac);\r
+ hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); \r
+ hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase2_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase2_led_offset_idac);\r
// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4);\r
\r
//phase3 sel\r
\r
hx3695_write_reg(0X43, phase3_mux_sel); \r
- hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); \r
- hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase3_als_offset_idac);\r
- hx3695_write_reg(0X48, phase3_led_offset_idac);\r
+ hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); \r
+ hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase3_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase3_led_offset_idac);\r
// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4);\r
\r
//phase4 sel\r
\r
hx3695_write_reg(0X43, phase4_mux_sel); \r
- hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); \r
- hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase4_als_offset_idac);\r
- hx3695_write_reg(0X48, phase4_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
+ hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); \r
+ hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase4_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase4_led_offset_idac);\r
hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4);\r
-\r
- hx3695_write_reg(0X43, phase5_mux_sel); \r
- hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); \r
- hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase5_pd_sel)); //<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase5_als_offset_idac);\r
- hx3695_write_reg(0X48, phase5_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
+ hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4);\r
+\r
+ hx3695_write_reg(0X43, phase5_mux_sel); \r
+ hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); \r
+ hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase5_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase5_led_offset_idac);\r
hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase6_mux_sel); \r
- hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); \r
- hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase6_als_offset_idac);\r
- hx3695_write_reg(0X48, phase6_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase6_led_offset_idac);\r
+ hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4);\r
+ \r
+ \r
+ hx3695_write_reg(0X43, phase6_mux_sel); \r
+ hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); \r
+ hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase6_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase6_led_offset_idac);\r
hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4);\r
\r
\r
- hx3695_write_reg(0X43, phase7_mux_sel); \r
- hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); \r
- hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase7_als_offset_idac);\r
- hx3695_write_reg(0X48, phase7_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase7_led_offset_idac);\r
+ hx3695_write_reg(0X43, phase7_mux_sel); \r
+ hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); \r
+ hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase7_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase7_led_offset_idac);\r
hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4);\r
\r
\r
- hx3695_write_reg(0X43, phase8_mux_sel); \r
- hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); \r
- hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase8_als_offset_idac);\r
- hx3695_write_reg(0X48, phase8_led_offset_idac);\r
-// hx3695_write_reg(0X48, phas8_led_offset_idac);\r
+ hx3695_write_reg(0X43, phase8_mux_sel); \r
+ hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); \r
+ hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase8_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase8_led_offset_idac);\r
hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4);\r
\r
\r
// analog circuit cfg \r
- hx3695_write_reg(0X60, 0x14); //\r
- hx3695_write_reg(0X61, 0xf0); \r
- hx3695_write_reg(0X62, 0x22); \r
- hx3695_write_reg(0X63, 0x15); \r
- \r
- hx3695_write_reg(0X64, 0x08); \r
- hx3695_write_reg(0X65, 0x88); //bug\r
- \r
- hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30\r
- hx3695_write_reg(0X67, 0x23); \r
- hx3695_write_reg(0X68, 0x46); \r
- hx3695_write_reg(0X69, 0x42); \r
- \r
- hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg\r
- hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable\r
+ hx3695_write_reg(0X60, 0x34); //\r
+ hx3695_write_reg(0X61, 0xf0); \r
+ hx3695_write_reg(0X62, 0x22); \r
+ hx3695_write_reg(0X63, 0x15); \r
+ \r
+ hx3695_write_reg(0X64, 0x08); \r
+ hx3695_write_reg(0X65, 0x88); //bug\r
+ \r
+ hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30\r
+ hx3695_write_reg(0X67, 0x23); \r
+ hx3695_write_reg(0X68, 0x46); \r
+ hx3695_write_reg(0X69, 0x42); \r
+ \r
+ hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg\r
+ hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable\r
\r
hx3695_write_reg(0X6a, 0X0f); \r
- hx3695_write_reg(0X6b, 0X22); \r
- hx3695_write_reg(0X6c, 0X00); \r
- hx3695_write_reg(0X6d, 0X37); \r
- hx3695_write_reg(0X6e, 0X82); \r
- hx3695_write_reg(0X6f, 0X08);\r
+ hx3695_write_reg(0X6b, 0X22); \r
+ hx3695_write_reg(0X6c, 0X00); \r
+ hx3695_write_reg(0X6d, 0X37); \r
+ hx3695_write_reg(0X6e, 0X82); \r
+ hx3695_write_reg(0X6f, 0X00);\r
/////////FIFO and adc conversion ready config////////\r
/////////FIFO and adc conversion ready config////////\r
-#if defined(PPG_INT_MODE)\r
- hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear\r
- hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int\r
-#elif defined(INT_MODE) //FIFO_ALL_MOST_FULL)\r
- hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
- hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark\r
- hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] \r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear\r
- hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
+#if defined(INT_MODE) //(FIFO_ALL_MOST_FULL)\r
+ hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
+ 0011=p4;0100=p5;0101=p6;0110=p7;\\r
+ bits<7> fifo enble\r
+ hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark\r
+ hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] \r
+ hx3695_write_reg(0X33, 0x83); // int width \r
+ hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
\r
#else\r
- hx3695_write_reg(0X1b, 0x92); // bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\r
- // 0011=p4;0100=p5;0101=p6;0110=p7;\r
- // bits<7> fifo enble \r
- hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int\r
- \r
+ hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;0011=p4;0100=p5;0101=p6;0110=p7;bits<7> fifo enble \r
+ hx3695_write_reg(0X36, 0x00); //intrupt \r
+ \r
+ hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int\r
+\r
#endif\r
\r
\r
// hx3695_write_reg(0X5c, 0x02);//soft reset\r
hx3695_delay_ms(5); \r
hx3695_write_reg(0X5c, 0x00);//release\r
-// read_fifo_first_flg = 1;\r
- return ;\r
- \r
- \r
- \r
+\r
+ return ; \r
}\r
\r
-void hx3695_factory_ft_card_test_config(void)//灰卡15mm高度测试配置\r
+\r
+\r
+void hx3695_factory_ft_leak_light_test_config(void)//©���������\r
{\r
- uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
+ uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */\r
- \r
-// uint16_t fifo_watermark= 250 ;\r
+\r
+ uint16_t fifo_watermark= 250 ;\r
uint8_t adc_rst_post_num= 0; /* 00=16,01=32,10=64,11=128*/ \r
- uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
+ uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/\r
uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/\r
- uint8_t phase7_8_internal = 0; //0x18; /* phase7 and phase8 prf internal cfg */\r
- \r
-// uint16_t thred_value = 32500;\r
+ uint8_t phase7_8_internal = 0; //0x18; /* phase7 and phase8 prf internal cfg */\r
+\r
\r
uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */\r
- uint8_t phase5_enable = 0; /*phase5_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase6_enable = 0; /*phase6_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase7_enable = 0; /*phase7_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase8_enable = 0; /*phase8_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase5_enable = 1; /*phase5_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase6_enable = 1; /*phase6_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase7_enable = 1; /*phase7_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ \r
\r
uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
\r
- uint8_t phase1_mux_sel = 0; /* sel phase1*/\r
- uint8_t phase2_mux_sel = 1; /* sel phase2*/\r
- uint8_t phase3_mux_sel = 2; /* sel phase3*/\r
- uint8_t phase4_mux_sel = 3; /* sel phase4*/\r
- uint8_t phase5_mux_sel = 4; /* sel phase5*/\r
- uint8_t phase6_mux_sel = 5; /* sel phase6*/\r
- uint8_t phase7_mux_sel = 6; /* sel phase7*/\r
- uint8_t phase8_mux_sel = 7; /* sel phase8*/\r
+ uint8_t phase1_mux_sel = 0; /* sel phase1*/\r
+ uint8_t phase2_mux_sel = 1; /* sel phase2*/\r
+ uint8_t phase3_mux_sel = 2; /* sel phase3*/\r
+ uint8_t phase4_mux_sel = 3; /* sel phase4*/\r
+ uint8_t phase5_mux_sel = 4; /* sel phase5*/\r
+ uint8_t phase6_mux_sel = 5; /* sel phase6*/\r
+ uint8_t phase7_mux_sel = 6; /* sel phase7*/\r
+ uint8_t phase8_mux_sel = 7; /* sel phase8*/\r
\r
\r
- uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase1_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ uint8_t phase1_tia_res = PS_LEAK_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */\r
uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */\r
- uint8_t phase1_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase1_pd_sel = ALS_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase1_ldr1_cur = 32; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase1_ldr2_cur = 0;\r
-// uint8_t phase1_of_idac1_cur = 0;\r
-// uint8_t phase1_of_idac2_cur = 0;\r
+ uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase1_ldr2_cur = 0;\r
uint8_t phase1_ad_inr_ctrl = 3;\r
uint8_t phase1_ad_of_idac_ctrl = 0;\r
-// uint8_t afe_offset = 0;\r
- uint8_t phase1_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase1_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
\r
\r
- uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase2_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase2_led_drv1_cha_sel = GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ uint8_t phase2_tia_res = PS_LEAK_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase2_led_drv1_cha_sel = LDR0_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase2_led_drv2_cha_sel = 0x00;\r
- uint8_t phase2_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase2_pd_sel = LDR0_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase2_ldr1_cur = 32; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase2_ldr2_cur = 0;\r
-// uint8_t phase2_of_idac1_cur = 0;\r
-// uint8_t phase2_of_idac2_cur = 0;\r
+ uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase2_ldr1_cur = DRV1_LEAK_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase2_ldr2_cur = DRV2_LEAK_CUR;\r
uint8_t phase2_ad_inr_ctrl = 3;\r
uint8_t phase2_ad_of_idac_ctrl = 0;\r
-// uint8_t phase2_afe_offset = 0;\r
- uint8_t phase2_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase2_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
\r
uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase3_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase3_led_drv1_cha_sel = RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase3_tia_res = PS_LEAK_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase3_led_drv1_cha_sel = LDR1_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase3_led_drv2_cha_sel = 0;\r
- uint8_t phase3_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase3_pd_sel = LDR1_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase3_ldr1_cur = 32; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase3_ldr2_cur = 0;\r
-// uint8_t phase3_of_idac1_cur = 0;\r
-// uint8_t phase3_of_idac2_cur = 0;\r
+ uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase3_ldr1_cur = DRV1_LEAK_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase3_ldr2_cur = DRV2_LEAK_CUR;\r
uint8_t phase3_ad_inr_ctrl = 3;\r
uint8_t phase3_ad_of_idac_ctrl = 0;\r
-// uint8_t phase3_afe_offset = 0;\r
- uint8_t phase3_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase3_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
\r
uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase4_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase4_led_drv1_cha_sel = IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase4_tia_res = PS_LEAK_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase4_led_drv1_cha_sel = LDR2_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase4_led_drv2_cha_sel = 0;\r
- uint8_t phase4_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase4_pd_sel = LDR2_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase4_ldr1_cur = 32; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase4_ldr2_cur = 0;\r
-// uint8_t phase4_of_idac1_cur = 0;\r
-// uint8_t phase4_of_idac2_cur = 0;\r
+ uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase4_ldr1_cur = DRV1_LEAK_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase4_ldr2_cur = DRV2_LEAK_CUR;\r
uint8_t phase4_ad_inr_ctrl = 3;\r
uint8_t phase4_ad_of_idac_ctrl = 0;\r
-// uint8_t phase4_afe_offset = 0;\r
- uint8_t phase4_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase4_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase5_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase5_tia_res = PS_LEAK_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase5_led_drv1_cha_sel = LDR3_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase5_led_drv2_cha_sel = 0;\r
- uint8_t phase5_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase5_pd_sel =LDR3_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase5_ldr2_cur = 0;\r
-// uint8_t phase5_of_idac1_cur = 0;\r
-// uint8_t phase5_of_idac2_cur = 0;\r
+ uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase5_ldr1_cur = DRV1_LEAK_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase5_ldr2_cur = DRV2_LEAK_CUR;\r
uint8_t phase5_ad_inr_ctrl = 3;\r
uint8_t phase5_ad_of_idac_ctrl = 0;\r
-// uint8_t phase5_afe_offset = 0;\r
- uint8_t phase5_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase5_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase6_tia_res = PS_LEAK_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase6_led_drv1_cha_sel = LDR4_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase6_led_drv2_cha_sel = 0;\r
- uint8_t phase6_pd_sel = 4; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase6_pd_sel = LDR4_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase6_ldr2_cur = 0;\r
-// uint8_t phase6_of_idac1_cur = 0;\r
-// uint8_t phase6_of_idac2_cur = 0;\r
+ uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase6_ldr1_cur = DRV1_LEAK_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase6_ldr2_cur = DRV2_LEAK_CUR;\r
uint8_t phase6_ad_inr_ctrl = 3;\r
uint8_t phase6_ad_of_idac_ctrl = 0;\r
-// uint8_t phase6_afe_offset = 0;\r
- uint8_t phase6_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase6_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase7_tia_res = PS_LEAK_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase7_led_drv1_cha_sel = LDR5_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase7_led_drv2_cha_sel = 0;\r
- uint8_t phase7_pd_sel = 0x00; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase7_pd_sel = LDR5_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase7_ldr2_cur = 0;\r
-// uint8_t phase7_of_idac1_cur = 0;\r
-// uint8_t phase7_of_idac2_cur = 0;\r
+ uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase7_ldr1_cur = DRV1_LEAK_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase7_ldr2_cur = DRV2_LEAK_CUR;\r
uint8_t phase7_ad_inr_ctrl = 3;\r
uint8_t phase7_ad_of_idac_ctrl = 0;\r
-// uint8_t phase7_afe_offset = 0;\r
- uint8_t phase7_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase7_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase8_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase8_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase8_led_drv2_cha_sel = 0;\r
- uint8_t phase8_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase8_pd_sel = 0; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase8_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase8_ldr2_cur = 0;\r
-// uint8_t phase8_of_idac1_cur = 0;\r
-// uint8_t phase8_of_idac2_cur = 0;\r
+ uint8_t phase8_ldr2_cur = 0;\r
uint8_t phase8_ad_inr_ctrl = 3;\r
uint8_t phase8_ad_of_idac_ctrl = 0;\r
-// uint8_t phase8_afe_offset = 0;\r
- uint8_t phase8_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase8_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ;\r
uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ;\r
4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */\r
\r
- uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/\r
- \r
+ uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/\r
+\r
uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ \r
- \r
- uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ \r
- \r
+\r
+ uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ \r
+ \r
uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ;\r
4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */\r
\r
hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> \r
\r
hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); \r
- hx3695_write_reg(0X2d, phase7_8_internal); \r
- hx3695_write_reg(0X2e, 0x33);// gpio ctrl \r
+ hx3695_write_reg(0X2d, phase7_8_internal); \r
+ hx3695_write_reg(0X2e, 0x33);// gpio ctrl \r
hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay));\r
- hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
+ hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
\r
\r
hx3695_write_reg(0X31, (led_on_time<<4| 0x00));\r
- hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置；\r
- hx3695_write_reg(0X34, 0x00);// 中断特殊配置；\r
- hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置；\r
- hx3695_write_reg(0X38, 0x00);\r
+ hx3695_write_reg(0X33, 0x83);// �жϼ��Լ��������ã�\r
+ hx3695_write_reg(0X34, 0x00);// �ж��������ã�\r
+ hx3695_write_reg(0X36, 0x00);// phase data ready ��־���ã�\r
+ hx3695_write_reg(0X38, 0x00);\r
\r
hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); \r
hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); \r
hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); \r
hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num );\r
hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num );\r
- \r
- hx3695_write_reg(0X43, phase1_mux_sel); \r
- hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); \r
- hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase1_als_offset_idac);\r
- hx3695_write_reg(0X48, phase1_led_offset_idac);\r
+ hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num );\r
+ hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num );\r
+ \r
+ hx3695_write_reg(0X43, phase1_mux_sel); \r
+ hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); \r
+ hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase1_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase1_led_offset_idac);\r
hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4);\r
\r
\r
hx3695_write_reg(0X43, phase2_mux_sel); \r
- hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); \r
- hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase2_als_offset_idac);\r
- hx3695_write_reg(0X48, phase2_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
+ hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); \r
+ hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase2_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase2_led_offset_idac);\r
hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4);\r
\r
//phase3 sel\r
\r
hx3695_write_reg(0X43, phase3_mux_sel); \r
- hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); \r
- hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase3_als_offset_idac);\r
- hx3695_write_reg(0X48, phase3_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
+ hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); \r
+ hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase3_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase3_led_offset_idac);\r
hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4);\r
\r
//phase4 sel\r
\r
hx3695_write_reg(0X43, phase4_mux_sel); \r
- hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); \r
- hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase4_als_offset_idac);\r
- hx3695_write_reg(0X48, phase4_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
+ hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); \r
+ hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase4_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase4_led_offset_idac);\r
hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4);\r
-\r
- hx3695_write_reg(0X43, phase5_mux_sel); \r
- hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); \r
- hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase5_als_offset_idac);\r
- hx3695_write_reg(0X48, phase5_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
+ hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4);\r
+\r
+ hx3695_write_reg(0X43, phase5_mux_sel); \r
+ hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); \r
+ hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase5_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase5_led_offset_idac);\r
hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase6_mux_sel); \r
- hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); \r
- hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase6_als_offset_idac);\r
- hx3695_write_reg(0X48, phase6_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase6_led_offset_idac);\r
+ hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4);\r
+ \r
+ \r
+ hx3695_write_reg(0X43, phase6_mux_sel); \r
+ hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); \r
+ hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase6_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase6_led_offset_idac);\r
hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4);\r
\r
\r
- hx3695_write_reg(0X43, phase7_mux_sel); \r
- hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); \r
- hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase7_als_offset_idac);\r
- hx3695_write_reg(0X48, phase7_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase7_led_offset_idac);\r
+ hx3695_write_reg(0X43, phase7_mux_sel); \r
+ hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); \r
+ hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase7_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase7_led_offset_idac);\r
hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4);\r
\r
\r
- hx3695_write_reg(0X43, phase8_mux_sel); \r
- hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); \r
- hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase8_als_offset_idac);\r
- hx3695_write_reg(0X48, phase8_led_offset_idac);\r
-// hx3695_write_reg(0X48, phas8_led_offset_idac);\r
+ hx3695_write_reg(0X43, phase8_mux_sel); \r
+ hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); \r
+ hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase8_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase8_led_offset_idac);\r
hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4);\r
\r
\r
// analog circuit cfg \r
- hx3695_write_reg(0X60, 0x14); //\r
- hx3695_write_reg(0X61, 0xf0); \r
- hx3695_write_reg(0X62, 0x22); \r
- hx3695_write_reg(0X63, 0x15); \r
- \r
- hx3695_write_reg(0X64, 0x08); \r
- hx3695_write_reg(0X65, 0x88); //bug\r
- \r
- hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30\r
- hx3695_write_reg(0X67, 0x23); \r
- hx3695_write_reg(0X68, 0x46); \r
- hx3695_write_reg(0X69, 0x42); \r
- \r
- hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg\r
- hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable\r
+ hx3695_write_reg(0X60, 0x34); //\r
+ hx3695_write_reg(0X61, 0xf0); \r
+ hx3695_write_reg(0X62, 0x22); \r
+ hx3695_write_reg(0X63, 0x15); \r
+ \r
+ hx3695_write_reg(0X64, 0x08); \r
+ hx3695_write_reg(0X65, 0x88); //bug\r
+ \r
+ hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30\r
+ hx3695_write_reg(0X67, 0x23); \r
+ hx3695_write_reg(0X68, 0x46); \r
+ hx3695_write_reg(0X69, 0x42); \r
+ \r
+ hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg\r
+ hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable\r
\r
hx3695_write_reg(0X6a, 0X0f); \r
- hx3695_write_reg(0X6b, 0X22); \r
- hx3695_write_reg(0X6c, 0X00); \r
- hx3695_write_reg(0X6d, 0X37); \r
- hx3695_write_reg(0X6e, 0X82); \r
- hx3695_write_reg(0X6f, 0X08);\r
+ hx3695_write_reg(0X6b, 0X22); \r
+ hx3695_write_reg(0X6c, 0X00); \r
+ hx3695_write_reg(0X6d, 0X37); \r
+ hx3695_write_reg(0X6e, 0X82); \r
+ hx3695_write_reg(0X6f, 0X00);\r
/////////FIFO and adc conversion ready config////////\r
/////////FIFO and adc conversion ready config////////\r
-#if defined(PPG_INT_MODE)\r
- hx3695_write_reg(0X1b, 0x00);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear\r
- hx3695_write_reg(0X38, 0x08); // int sel,00=close almost full int,04=enable almost full int\r
-#elif defined(INT_MODE) //(FIFO_ALL_MOST_FULL)\r
- hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
- hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark\r
- hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] \r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
+#if defined(INT_MODE) //(FIFO_ALL_MOST_FULL)\r
+ hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
+ 0011=p4;0100=p5;0101=p6;0110=p7;\\r
+ bits<7> fifo enble\r
+ hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark\r
+ hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] \r
+ hx3695_write_reg(0X33, 0x83); // int width \r
+ hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
\r
#else\r
- hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\r
- // 0011=p4;0100=p5;0101=p6;0110=p7;\r
- // bits<7> fifo enble \r
- hx3695_write_reg(0X36, 0x00); //intrupt \r
- \r
- hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int\r
+ hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;0011=p4;0100=p5;0101=p6;0110=p7;bits<7> fifo enble \r
+ hx3695_write_reg(0X36, 0x00); //intrupt \r
+ \r
+ hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int\r
\r
#endif\r
\r
\r
- hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); \r
- hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); \r
- hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) );\r
- hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); \r
+ hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); \r
+ hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); \r
+ hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) );\r
+ hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); \r
\r
// hx3695_write_reg(0X5c, 0x02);//soft reset\r
- hx3695_delay_ms(5); \r
- hx3695_write_reg(0X5c, 0x00);//release\r
+ hx3695_delay_ms(5); \r
+ hx3695_write_reg(0X5c, 0x00);//release\r
\r
- return ; \r
+ return ;\r
}\r
-\r
-void hx3695_factory_ft_single_check_config(void)//灰卡10mm高度测试配置\r
+void hx3695_factory_Gnoise_config(void) // �������\r
{\r
-\r
- uint16_t sample_rate = 200; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
+ uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */\r
- \r
- uint8_t adc_rst_post_num=0; /* 00=16,01=32,10=64,11=128*/ \r
- uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
+\r
+ uint16_t fifo_watermark= 250 ;\r
+ uint8_t adc_rst_post_num= 0; /* 00=16,01=32,10=64,11=128*/ \r
+ uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/\r
uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/\r
- uint8_t phase7_8_internal = 0; /* phase7 and phase8 prf internal cfg */\r
- \r
+ uint8_t phase7_8_internal = 0; //0x18; /* phase7 and phase8 prf internal cfg */\r
+ \r
uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */\r
- uint8_t phase5_enable = 0; /*phase5_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase6_enable = 0; /*phase6_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase7_enable = 0; /*phase7_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase8_enable = 0; /*phase8_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase5_enable = 1; /*phase5_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase6_enable = 1; /*phase6_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase7_enable = 1; /*phase7_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ \r
\r
uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
\r
- uint8_t phase1_mux_sel = 0; /* sel phase1*/\r
- uint8_t phase2_mux_sel = 1; /* sel phase2*/\r
- uint8_t phase3_mux_sel = 2; /* sel phase3*/\r
- uint8_t phase4_mux_sel = 3; /* sel phase4*/\r
- uint8_t phase5_mux_sel = 4; /* sel phase5*/\r
- uint8_t phase6_mux_sel = 5; /* sel phase6*/\r
- uint8_t phase7_mux_sel = 6; /* sel phase7*/\r
- uint8_t phase8_mux_sel = 7; /* sel phase8*/\r
+ uint8_t phase1_mux_sel = 0; /* sel phase1*/\r
+ uint8_t phase2_mux_sel = 1; /* sel phase2*/\r
+ uint8_t phase3_mux_sel = 2; /* sel phase3*/\r
+ uint8_t phase4_mux_sel = 3; /* sel phase4*/\r
+ uint8_t phase5_mux_sel = 4; /* sel phase5*/\r
+ uint8_t phase6_mux_sel = 5; /* sel phase6*/\r
+ uint8_t phase7_mux_sel = 6; /* sel phase7*/\r
+ uint8_t phase8_mux_sel = 7; /* sel phase8*/\r
\r
\r
- uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase1_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ uint8_t phase1_tia_res = PS_Gnoise_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */\r
uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */\r
- uint8_t phase1_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase1_pd_sel = ALS_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase1_ldr2_cur = 0;\r
-// uint8_t phase1_of_idac1_cur = 0;\r
-// uint8_t phase1_of_idac2_cur = 0;\r
+ uint8_t phase1_ldr2_cur = 0;\r
uint8_t phase1_ad_inr_ctrl = 3;\r
uint8_t phase1_ad_of_idac_ctrl = 0;\r
-// uint8_t afe_offset = 0;\r
- uint8_t phase1_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase1_led_en = 0; /* phase1 led enable*/ \r
+ uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
\r
-\r
- uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase2_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase2_led_drv1_cha_sel = GREEN_LED_SLE; //GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ uint8_t phase2_tia_res = 3; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase2_led_drv1_cha_sel = LDR0_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase2_led_drv2_cha_sel = 0x00;\r
- uint8_t phase2_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase2_pd_sel = LDR0_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase2_ldr1_cur = 16; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase2_ldr2_cur = 0;\r
-// uint8_t phase2_of_idac1_cur = 0;\r
-// uint8_t phase2_of_idac2_cur = 0;\r
+ uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase2_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase2_ldr2_cur = 0;\r
uint8_t phase2_ad_inr_ctrl = 3;\r
uint8_t phase2_ad_of_idac_ctrl = 0;\r
-// uint8_t phase2_afe_offset = 0;\r
- uint8_t phase2_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase2_led_en = 0; /* phase1 led enable*/ \r
+ uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
\r
uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase3_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase3_led_drv1_cha_sel = RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase3_tia_res = PS_Gnoise_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase3_led_drv1_cha_sel = LDR1_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase3_led_drv2_cha_sel = 0;\r
- uint8_t phase3_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase3_pd_sel = LDR1_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase3_ldr1_cur = 16; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase3_ldr2_cur = 0;\r
-// uint8_t phase3_of_idac1_cur = 0;\r
-// uint8_t phase3_of_idac2_cur = 0;\r
+ uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase3_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase3_ldr2_cur = 0;\r
uint8_t phase3_ad_inr_ctrl = 3;\r
uint8_t phase3_ad_of_idac_ctrl = 0;\r
-// uint8_t phase3_afe_offset = 0;\r
- uint8_t phase3_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase3_led_en = 0; /* phase1 led enable*/ \r
+ uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
\r
uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase4_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase4_led_drv1_cha_sel = IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase4_tia_res = PS_Gnoise_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase4_led_drv1_cha_sel = LDR2_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase4_led_drv2_cha_sel = 0;\r
- uint8_t phase4_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase4_pd_sel = LDR2_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase4_ldr1_cur = 16; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase4_ldr2_cur = 0;\r
-// uint8_t phase4_of_idac1_cur = 0;\r
-// uint8_t phase4_of_idac2_cur = 0;\r
+ uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase4_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase4_ldr2_cur = 0;\r
uint8_t phase4_ad_inr_ctrl = 3;\r
uint8_t phase4_ad_of_idac_ctrl = 0;\r
-// uint8_t phase4_afe_offset = 0;\r
- uint8_t phase4_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase4_led_en = 0; /* phase1 led enable*/ \r
+ uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase5_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase5_tia_res = PS_Gnoise_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase5_led_drv1_cha_sel = LDR3_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase5_led_drv2_cha_sel = 0;\r
- uint8_t phase5_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase5_pd_sel = LDR3_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase5_ldr2_cur = 0;\r
-// uint8_t phase5_of_idac1_cur = 0;\r
-// uint8_t phase5_of_idac2_cur = 0;\r
+ uint8_t phase5_ldr2_cur = 0;\r
uint8_t phase5_ad_inr_ctrl = 3;\r
uint8_t phase5_ad_of_idac_ctrl = 0;\r
-// uint8_t phase5_afe_offset = 0;\r
- uint8_t phase5_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase5_led_en = 0; /* phase1 led enable*/ \r
+ uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase6_tia_res = PS_Gnoise_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase6_led_drv1_cha_sel = LDR4_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase6_led_drv2_cha_sel = 0;\r
- uint8_t phase6_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase6_pd_sel = LDR4_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase6_ldr2_cur = 0;\r
-// uint8_t phase6_of_idac1_cur = 0;\r
-// uint8_t phase6_of_idac2_cur = 0;\r
+ uint8_t phase6_ldr2_cur = 0;\r
uint8_t phase6_ad_inr_ctrl = 3;\r
uint8_t phase6_ad_of_idac_ctrl = 0;\r
-// uint8_t phase6_afe_offset = 0;\r
- uint8_t phase6_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase6_led_en = 0; /* phase1 led enable*/ \r
+ uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase7_tia_res = PS_Gnoise_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase7_led_drv1_cha_sel = LDR5_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase7_led_drv2_cha_sel = 0;\r
- uint8_t phase7_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase7_pd_sel = LDR5_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase7_ldr2_cur = 0;\r
-// uint8_t phase7_of_idac1_cur = 0;\r
-// uint8_t phase7_of_idac2_cur = 0;\r
+ uint8_t phase7_ldr2_cur = 0;\r
uint8_t phase7_ad_inr_ctrl = 3;\r
uint8_t phase7_ad_of_idac_ctrl = 0;\r
-// uint8_t phase7_afe_offset = 0;\r
- uint8_t phase7_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase7_led_en = 0; /* phase1 led enable*/ \r
+ uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase8_led_drv1_cha_sel = 0; //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase8_tia_res = 3; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase8_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase8_led_drv2_cha_sel = 0;\r
- uint8_t phase8_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase8_pd_sel = 0; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase8_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase8_ldr2_cur = 0;\r
-// uint8_t phase8_of_idac1_cur = 0;\r
-// uint8_t phase8_of_idac2_cur = 0;\r
+ uint8_t phase8_ldr2_cur = 0;\r
uint8_t phase8_ad_inr_ctrl = 3;\r
uint8_t phase8_ad_of_idac_ctrl = 0;\r
-// uint8_t phase8_afe_offset = 0;\r
- uint8_t phase8_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase8_led_en = 0; /* phase1 led enable*/ \r
+ uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
- uint8_t init_wait_delay = 5 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ;\r
+ uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ;\r
4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ \r
\r
uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ;\r
4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */\r
\r
- uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/\r
- \r
+ uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/\r
+\r
uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ \r
- \r
- uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ \r
- \r
- uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ;\r
+\r
+ uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ \r
+ \r
+ uint8_t led_on_time = 3; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ;\r
4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */\r
\r
hx3695_delay_ms(10); \r
- \r
+ \r
hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6\r
hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8>\r
hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> \r
\r
hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); \r
- hx3695_write_reg(0X2d, phase7_8_internal); \r
- hx3695_write_reg(0X2e, 0x33);// gpio ctrl \r
+ hx3695_write_reg(0X2d, phase7_8_internal); \r
+ hx3695_write_reg(0X2e, 0x33);// gpio ctrl \r
hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay));\r
- hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
+ hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
\r
\r
hx3695_write_reg(0X31, (led_on_time<<4| 0x00));\r
- hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置；\r
- hx3695_write_reg(0X34, 0x00);// 中断特殊配置；\r
- hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置；\r
- hx3695_write_reg(0X38, 0x00);\r
+ hx3695_write_reg(0X33, 0x83);// �жϼ��Լ��������ã�\r
+ hx3695_write_reg(0X34, 0x00);// �ж��������ã�\r
+ hx3695_write_reg(0X36, 0x00);// phase data ready ��־���ã�\r
+ hx3695_write_reg(0X38, 0x00);\r
\r
hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); \r
hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); \r
hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); \r
hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num );\r
hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num );\r
- \r
- hx3695_write_reg(0X43, phase1_mux_sel); \r
- hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); \r
- hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase1_als_offset_idac);\r
- hx3695_write_reg(0X48, phase1_led_offset_idac);\r
-\r
+ hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num );\r
+ hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num );\r
+ \r
+ hx3695_write_reg(0X43, phase1_mux_sel); \r
+ hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); \r
+ hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase1_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase1_led_offset_idac);\r
hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4);\r
\r
-// hx3695_write_reg(0X4e, thred_value);\r
-// hx3695_write_reg(0X4f, thred_value>>5);\r
- \r
+ \r
hx3695_write_reg(0X43, phase2_mux_sel); \r
- hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); \r
- hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase2_als_offset_idac);\r
- hx3695_write_reg(0X48, phase2_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
+ hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); \r
+ hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase2_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase2_led_offset_idac);\r
hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4);\r
\r
//phase3 sel\r
\r
hx3695_write_reg(0X43, phase3_mux_sel); \r
- hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); \r
- hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase3_als_offset_idac);\r
- hx3695_write_reg(0X48, phase3_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
+ hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); \r
+ hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase3_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase3_led_offset_idac);\r
hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4);\r
\r
//phase4 sel\r
\r
hx3695_write_reg(0X43, phase4_mux_sel); \r
- hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); \r
- hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase4_als_offset_idac);\r
- hx3695_write_reg(0X48, phase4_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
+ hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); \r
+ hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase4_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase4_led_offset_idac);\r
hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4);\r
-\r
- hx3695_write_reg(0X43, phase5_mux_sel); \r
- hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); \r
- hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase5_pd_sel)); //<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase5_als_offset_idac);\r
- hx3695_write_reg(0X48, phase5_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
+ hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4);\r
+\r
+ hx3695_write_reg(0X43, phase5_mux_sel); \r
+ hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); \r
+ hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase5_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase5_led_offset_idac);\r
hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase6_mux_sel); \r
- hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); \r
- hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase6_als_offset_idac);\r
- hx3695_write_reg(0X48, phase6_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase6_led_offset_idac);\r
+ hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4);\r
+ \r
+ \r
+ hx3695_write_reg(0X43, phase6_mux_sel); \r
+ hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); \r
+ hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase6_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase6_led_offset_idac);\r
hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4);\r
\r
\r
- hx3695_write_reg(0X43, phase7_mux_sel); \r
- hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); \r
- hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase7_als_offset_idac);\r
- hx3695_write_reg(0X48, phase7_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase7_led_offset_idac);\r
+ hx3695_write_reg(0X43, phase7_mux_sel); \r
+ hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); \r
+ hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase7_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase7_led_offset_idac);\r
hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4);\r
\r
\r
- hx3695_write_reg(0X43, phase8_mux_sel); \r
- hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); \r
- hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase8_als_offset_idac);\r
- hx3695_write_reg(0X48, phase8_led_offset_idac);\r
-// hx3695_write_reg(0X48, phas8_led_offset_idac);\r
+ hx3695_write_reg(0X43, phase8_mux_sel); \r
+ hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); \r
+ hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase8_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase8_led_offset_idac);\r
hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4);\r
\r
\r
// analog circuit cfg \r
- hx3695_write_reg(0X60, 0x14); //\r
- hx3695_write_reg(0X61, 0xf0); \r
- hx3695_write_reg(0X62, 0x22); \r
- hx3695_write_reg(0X63, 0x15); \r
- \r
- hx3695_write_reg(0X64, 0x08); \r
- hx3695_write_reg(0X65, 0x88); //bug\r
- \r
- hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30\r
- hx3695_write_reg(0X67, 0x23); \r
- hx3695_write_reg(0X68, 0x46); \r
- hx3695_write_reg(0X69, 0x42); \r
- \r
- hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg\r
- hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable\r
+ hx3695_write_reg(0X60, 0x34); //\r
+ hx3695_write_reg(0X61, 0xf0); \r
+ hx3695_write_reg(0X62, 0x22); \r
+ hx3695_write_reg(0X63, 0x15); \r
+ \r
+ hx3695_write_reg(0X64, 0x08); \r
+ hx3695_write_reg(0X65, 0x88); //bug\r
+ \r
+ hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30\r
+ hx3695_write_reg(0X67, 0x23); \r
+ hx3695_write_reg(0X68, 0x46); \r
+ hx3695_write_reg(0X69, 0x42); \r
+ \r
+ hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg\r
+ hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable\r
\r
hx3695_write_reg(0X6a, 0X0f); \r
- hx3695_write_reg(0X6b, 0X22); \r
- hx3695_write_reg(0X6c, 0X00); \r
- hx3695_write_reg(0X6d, 0X37); \r
- hx3695_write_reg(0X6e, 0X82); \r
- hx3695_write_reg(0X6f, 0X08);\r
+ hx3695_write_reg(0X6b, 0X22); \r
+ hx3695_write_reg(0X6c, 0X00); \r
+ hx3695_write_reg(0X6d, 0X37); \r
+ hx3695_write_reg(0X6e, 0X82); \r
+ hx3695_write_reg(0X6f, 0X00);\r
/////////FIFO and adc conversion ready config////////\r
/////////FIFO and adc conversion ready config////////\r
-#if defined(PPG_INT_MODE)\r
- hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear\r
- hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int\r
-#elif defined(INT_MODE) //FIFO_ALL_MOST_FULL)\r
- hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
- hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark\r
- hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] \r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear\r
- hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
+#if defined(INT_MODE) //(FIFO_ALL_MOST_FULL)\r
+ hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;0011=p4;0100=p5;0101=p6;0110=p7;bits<7> fifo enble\r
+ hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark\r
+ hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] \r
+ hx3695_write_reg(0X33, 0x83); // int width \r
+ hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
\r
#else\r
- hx3695_write_reg(0X1b, 0x92); // bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\r
- // 0011=p4;0100=p5;0101=p6;0110=p7;\r
- // bits<7> fifo enble \r
- hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int\r
- \r
+ hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;0011=p4;0100=p5;0101=p6;0110=p7;bits<7> fifo enble \r
+ hx3695_write_reg(0X36, 0x00); //intrupt \r
+ \r
+ hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int\r
+\r
#endif\r
\r
\r
- hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); \r
- hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); \r
- hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) );\r
- hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); \r
+ hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); \r
+ hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); \r
+ hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) );\r
+ hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); \r
\r
// hx3695_write_reg(0X5c, 0x02);//soft reset\r
- hx3695_delay_ms(5); \r
- hx3695_write_reg(0X5c, 0x00);//release\r
+ hx3695_delay_ms(5); \r
+ hx3695_write_reg(0X5c, 0x00);//release\r
\r
return ;\r
}\r
-\r
-void hx3695_factory_ft_leak_light_test_config(void)//漏光测试配置\r
+void hx3695_LDR0_led_control(uint8_t phase2_led_en,uint8_t phase2_ldr1_cur)\r
{\r
- uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
- uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */\r
- \r
-\r
- uint8_t adc_rst_post_num= 0; /* 00=16,01=32,10=64,11=128*/ \r
- uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
- uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/\r
- uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/\r
- uint8_t phase7_8_internal = 0; //0x18; /* phase7 and phase8 prf internal cfg */\r
- \r
-// uint16_t thred_value = 32500;\r
- \r
- uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */\r
- uint8_t phase5_enable = 0; /*phase5_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase6_enable = 0; /*phase6_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase7_enable = 0; /*phase7_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase8_enable = 0; /*phase8_enable , 1 mean enable ; 0 mean disable */ \r
-\r
- uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- \r
- uint8_t phase1_mux_sel = 0; /* sel phase1*/\r
- uint8_t phase2_mux_sel = 1; /* sel phase2*/\r
- uint8_t phase3_mux_sel = 2; /* sel phase3*/\r
- uint8_t phase4_mux_sel = 3; /* sel phase4*/\r
- uint8_t phase5_mux_sel = 4; /* sel phase5*/\r
- uint8_t phase6_mux_sel = 5; /* sel phase6*/\r
- uint8_t phase7_mux_sel = 6; /* sel phase7*/\r
- uint8_t phase8_mux_sel = 7; /* sel phase8*/\r
- \r
-\r
- uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase1_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */\r
- uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */\r
- uint8_t phase1_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase1_ldr2_cur = 0;\r
-// uint8_t phase1_of_idac1_cur = 0;\r
-// uint8_t phase1_of_idac2_cur = 0;\r
- uint8_t phase1_ad_inr_ctrl = 3;\r
- uint8_t phase1_ad_of_idac_ctrl = 0;\r
-// uint8_t afe_offset = 0;\r
- uint8_t phase1_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
-\r
-\r
- uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase2_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase2_led_drv1_cha_sel = GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase2_mux_sel = 1; /* sel phase2*/\r
+ uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ uint8_t phase2_tia_res = PS_SINGLE_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase2_led_drv1_cha_sel = LDR0_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase2_led_drv2_cha_sel = 0x00;\r
- uint8_t phase2_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase2_pd_sel = LDR0_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase2_ldr1_cur = 64; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase2_ldr2_cur = 0;\r
-// uint8_t phase2_of_idac1_cur = 0;\r
-// uint8_t phase2_of_idac2_cur = 0;\r
+ uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+// uint8_t phase2_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase2_ldr2_cur = 0;\r
uint8_t phase2_ad_inr_ctrl = 3;\r
uint8_t phase2_ad_of_idac_ctrl = 0;\r
-// uint8_t phase2_afe_offset = 0;\r
- uint8_t phase2_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+// uint8_t phase2_led_en = 0; /* phase1 led enable*/ \r
+ uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
+ \r
+ \r
+ hx3695_write_reg(0X43, phase2_mux_sel); \r
+ hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); \r
+ hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase2_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase2_led_offset_idac);\r
+ hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); \r
+ hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X30, phase2_led_en<<1);\r
+ hx3695_write_reg(0X72, phase2_led_en<<1);\r
+}\r
\r
- \r
+void hx3695_LDR1_led_control(uint8_t phase3_led_en,uint8_t phase3_ldr1_cur)\r
+{\r
+ uint8_t phase3_mux_sel = 2; /* sel phase3*/\r
uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase3_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase3_led_drv1_cha_sel = RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase3_tia_res = PS_SINGLE_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase3_led_drv1_cha_sel = LDR1_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase3_led_drv2_cha_sel = 0;\r
- uint8_t phase3_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase3_pd_sel = LDR1_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase3_ldr1_cur = 64; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase3_ldr2_cur = 0;\r
-// uint8_t phase3_of_idac1_cur = 0;\r
-// uint8_t phase3_of_idac2_cur = 0;\r
+ uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+// uint8_t phase3_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase3_ldr2_cur = 0;\r
uint8_t phase3_ad_inr_ctrl = 3;\r
- uint8_t phase3_ad_of_idac_ctrl = 0;\r
-// uint8_t phase3_afe_offset = 0;\r
- uint8_t phase3_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase3_ad_of_idac_ctrl = 0; \r
+ uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
+ hx3695_write_reg(0X43, phase3_mux_sel); \r
+ hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); \r
+ hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase3_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase3_led_offset_idac);\r
+ hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); \r
+ hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X30, phase3_led_en<<2);\r
+ hx3695_write_reg(0X72, phase3_led_en<<2);\r
+}\r
\r
- \r
+void hx3695_LDR2_led_control(uint8_t phase4_led_en ,uint8_t phase4_ldr1_cur)\r
+{\r
+ uint8_t phase4_mux_sel = 3; /* sel phase4*/\r
uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase4_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase4_led_drv1_cha_sel = IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase4_tia_res = PS_SINGLE_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase4_led_drv1_cha_sel = LDR2_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase4_led_drv2_cha_sel = 0;\r
- uint8_t phase4_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase4_pd_sel = LDR2_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase4_ldr1_cur = 64; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase4_ldr2_cur = 0;\r
-// uint8_t phase4_of_idac1_cur = 0;\r
-// uint8_t phase4_of_idac2_cur = 0;\r
+ uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+// uint8_t phase4_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase4_ldr2_cur = 0;\r
uint8_t phase4_ad_inr_ctrl = 3;\r
uint8_t phase4_ad_of_idac_ctrl = 0;\r
-// uint8_t phase4_afe_offset = 0;\r
- uint8_t phase4_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+// uint8_t phase4_led_en = 0; /* phase1 led enable*/ \r
+ uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
+ hx3695_write_reg(0X43, phase4_mux_sel); \r
+ hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); \r
+ hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase4_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase4_led_offset_idac);\r
+ hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); \r
+ hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X30, phase4_led_en<<3);\r
+ hx3695_write_reg(0X72, phase4_led_en<<3);\r
+}\r
\r
+void hx3695_LDR3_led_control(uint8_t phase5_led_en,uint8_t phase5_ldr1_cur)\r
+{\r
+ uint8_t phase5_mux_sel = 4; /* sel phase5*/\r
uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase5_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase5_tia_res = PS_SINGLE_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase5_led_drv1_cha_sel = LDR3_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase5_led_drv2_cha_sel = 0;\r
- uint8_t phase5_pd_sel = 4; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase5_pd_sel = LDR3_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase5_ldr2_cur = 0;\r
-// uint8_t phase5_of_idac1_cur = 0;\r
-// uint8_t phase5_of_idac2_cur = 0;\r
+ uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+// uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase5_ldr2_cur = 0;\r
uint8_t phase5_ad_inr_ctrl = 3;\r
uint8_t phase5_ad_of_idac_ctrl = 0;\r
-// uint8_t phase5_afe_offset = 0;\r
- uint8_t phase5_led_en = 0; /* phase1 led enable*/\r
- \r
- uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ \r
+ uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
+ \r
+ hx3695_write_reg(0X43, phase5_mux_sel); \r
+ hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); \r
+ hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase5_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase5_led_offset_idac);\r
+ hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); \r
+ hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X30, phase5_led_en<<4);\r
+ hx3695_write_reg(0X72, phase5_led_en<<4); \r
+}\r
+void hx3695_LDR4_led_control(uint8_t phase6_led_en,uint8_t phase6_ldr1_cur)\r
+{\r
+ uint8_t phase6_mux_sel = 5; /* sel phase6*/\r
uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase6_tia_res = PS_SINGLE_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase6_led_drv1_cha_sel = LDR4_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase6_led_drv2_cha_sel = 0;\r
- uint8_t phase6_pd_sel = 4; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase6_pd_sel = LDR4_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase6_ldr2_cur = 0;\r
-// uint8_t phase6_of_idac1_cur = 0;\r
-// uint8_t phase6_of_idac2_cur = 0;\r
+ uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+// uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase6_ldr2_cur = 0;\r
uint8_t phase6_ad_inr_ctrl = 3;\r
- uint8_t phase6_ad_of_idac_ctrl = 0;\r
-// uint8_t phase6_afe_offset = 0;\r
- uint8_t phase6_led_en = 0; /* phase1 led enable*/\r
- \r
- uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase6_ad_of_idac_ctrl = 0; \r
+ uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
+ \r
+ hx3695_write_reg(0X43, phase6_mux_sel); \r
+ hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); \r
+ hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase6_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase6_led_offset_idac);\r
+ hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); \r
+ hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X30, phase6_led_en<<5); \r
+ hx3695_write_reg(0X72, phase6_led_en<<5); \r
+}\r
\r
- uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+void hx3695_LDR5_led_control(uint8_t phase7_led_en,uint8_t phase7_ldr1_cur)\r
+{\r
+ uint8_t phase7_mux_sel = 6; /* sel phase7*/\r
+ uint8_t phase7_tia_res = PS_SINGLE_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase7_led_drv1_cha_sel = LDR5_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase7_led_drv2_cha_sel = 0;\r
- uint8_t phase7_pd_sel = 0x00; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase7_pd_sel = LDR5_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase7_ldr2_cur = 0;\r
-// uint8_t phase7_of_idac1_cur = 0;\r
-// uint8_t phase7_of_idac2_cur = 0;\r
+ uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+// uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase7_ldr2_cur = 0;\r
uint8_t phase7_ad_inr_ctrl = 3;\r
uint8_t phase7_ad_of_idac_ctrl = 0;\r
-// uint8_t phase7_afe_offset = 0;\r
- uint8_t phase7_led_en = 0; /* phase1 led enable*/\r
- \r
- uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+// uint8_t phase7_led_en = 0; /* phase7 led enable*/ \r
+ uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
+ \r
+ hx3695_write_reg(0X43, phase7_mux_sel); \r
+ hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); \r
+ hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase7_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase7_led_offset_idac);\r
+ hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); \r
+ hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X30, phase7_led_en<<6);\r
+ hx3695_write_reg(0X72, phase7_led_en<<6);\r
+}\r
+ \r
+void hx3695_factory_ft_single_check_config(void)\r
+{\r
+ uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
+ uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */\r
\r
- uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase8_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase8_led_drv2_cha_sel = 0;\r
- uint8_t phase8_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase8_ldr1_cur = 50; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase8_ldr2_cur = 0;\r
-// uint8_t phase8_of_idac1_cur = 0;\r
-// uint8_t phase8_of_idac2_cur = 0;\r
- uint8_t phase8_ad_inr_ctrl = 3;\r
- uint8_t phase8_ad_of_idac_ctrl = 0;\r
-// uint8_t phase8_afe_offset = 0;\r
- uint8_t phase8_led_en = 0; /* phase1 led enable*/\r
- \r
- uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ;\r
- 4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ \r
- \r
- uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ;\r
- 4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */\r
- \r
- uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/\r
- \r
- uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ \r
- \r
- uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ \r
- \r
- uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ;\r
- 4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */\r
- \r
- hx3695_delay_ms(10); \r
- \r
- hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6\r
- hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8>\r
- hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> \r
- \r
- hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); \r
- hx3695_write_reg(0X2d, phase7_8_internal); \r
- hx3695_write_reg(0X2e, 0x33);// gpio ctrl \r
- hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay));\r
- hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
- hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
-\r
-\r
- hx3695_write_reg(0X31, (led_on_time<<4| 0x00));\r
- hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置；\r
- hx3695_write_reg(0X34, 0x00);// 中断特殊配置；\r
- hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置；\r
- hx3695_write_reg(0X38, 0x00);\r
- \r
- hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); \r
- hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); \r
- hx3695_write_reg(0X3c, (phase5_inner_avg | (phase6_inner_avg<<4))); \r
- hx3695_write_reg(0X3d, (phase7_inner_avg | (phase8_inner_avg<<4))); \r
- hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); \r
- hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num );\r
- \r
- hx3695_write_reg(0X43, phase1_mux_sel); \r
- hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); \r
- hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase1_als_offset_idac);\r
- hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4);\r
-\r
- \r
- hx3695_write_reg(0X43, phase2_mux_sel); \r
- hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); \r
- hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase2_als_offset_idac);\r
- hx3695_write_reg(0X48, phase2_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4);\r
- \r
-//phase3 sel\r
-\r
- hx3695_write_reg(0X43, phase3_mux_sel); \r
- hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); \r
- hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase3_als_offset_idac);\r
- hx3695_write_reg(0X48, phase3_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4);\r
- \r
-//phase4 sel\r
-\r
- hx3695_write_reg(0X43, phase4_mux_sel); \r
- hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); \r
- hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase4_als_offset_idac);\r
- hx3695_write_reg(0X48, phase4_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4);\r
-\r
- hx3695_write_reg(0X43, phase5_mux_sel); \r
- hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); \r
- hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase5_als_offset_idac);\r
- hx3695_write_reg(0X48, phase5_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase6_mux_sel); \r
- hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); \r
- hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase6_als_offset_idac);\r
- hx3695_write_reg(0X48, phase6_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase6_led_offset_idac);\r
- hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase7_mux_sel); \r
- hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); \r
- hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase7_als_offset_idac);\r
- hx3695_write_reg(0X48, phase7_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase7_led_offset_idac);\r
- hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase8_mux_sel); \r
- hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); \r
- hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase8_als_offset_idac);\r
- hx3695_write_reg(0X48, phase8_led_offset_idac);\r
-// hx3695_write_reg(0X48, phas8_led_offset_idac);\r
- hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4);\r
- \r
-\r
-// analog circuit cfg \r
- hx3695_write_reg(0X60, 0x14); //\r
- hx3695_write_reg(0X61, 0xf0); \r
- hx3695_write_reg(0X62, 0x22); \r
- hx3695_write_reg(0X63, 0x15); \r
- \r
- hx3695_write_reg(0X64, 0x08); \r
- hx3695_write_reg(0X65, 0x88); //bug\r
- \r
- hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30\r
- hx3695_write_reg(0X67, 0x23); \r
- hx3695_write_reg(0X68, 0x46); \r
- hx3695_write_reg(0X69, 0x42); \r
- \r
- hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg\r
- hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable\r
- \r
- hx3695_write_reg(0X6a, 0X0f); \r
- hx3695_write_reg(0X6b, 0X22); \r
- hx3695_write_reg(0X6c, 0X00); \r
- hx3695_write_reg(0X6d, 0X37); \r
- hx3695_write_reg(0X6e, 0X82); \r
- hx3695_write_reg(0X6f, 0X08);\r
-/////////FIFO and adc conversion ready config////////\r
-/////////FIFO and adc conversion ready config////////\r
-#if defined(PPG_INT_MODE)\r
- hx3695_write_reg(0X1b, 0x00);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear\r
- hx3695_write_reg(0X38, 0x08); // int sel,00=close almost full int,04=enable almost full int\r
-#elif defined(INT_MODE) //(FIFO_ALL_MOST_FULL)\r
- hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
- hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark\r
- hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] \r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
-\r
-#else\r
- hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\r
- // 0011=p4;0100=p5;0101=p6;0110=p7;\r
- // bits<7> fifo enble \r
- hx3695_write_reg(0X36, 0x00); //intrupt \r
- \r
- hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int\r
-\r
-#endif\r
-\r
- \r
- hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); \r
- hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); \r
- hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) );\r
- hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); \r
-\r
-// hx3695_write_reg(0X5c, 0x02);//soft reset\r
- hx3695_delay_ms(5); \r
- hx3695_write_reg(0X5c, 0x00);//release\r
-\r
- return ;\r
-}\r
-\r
-void hx3695_factory_led_off_config(void)\r
-{\r
- uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
- uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */\r
-\r
- uint8_t adc_rst_post_num=0; /* 00=16,01=32,10=64,11=128*/ \r
- uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
+ uint16_t fifo_watermark= 250 ;\r
+ uint8_t adc_rst_post_num= 0; /* 00=16,01=32,10=64,11=128*/ \r
+ uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/\r
uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/\r
- uint8_t phase7_8_internal = 0; /* phase7 and phase8 prf internal cfg */\r
- \r
+ uint8_t phase7_8_internal = 0; //0x18; /* phase7 and phase8 prf internal cfg */\r
+ \r
uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */\r
- uint8_t phase5_enable = 0; /*phase5_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase6_enable = 0; /*phase6_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase7_enable = 0; /*phase7_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase8_enable = 0; /*phase8_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase5_enable = 1; /*phase5_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase6_enable = 1; /*phase6_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase7_enable = 1; /*phase7_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ \r
\r
uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
\r
- uint8_t phase1_mux_sel = 0; /* sel phase1*/\r
- uint8_t phase2_mux_sel = 1; /* sel phase2*/\r
- uint8_t phase3_mux_sel = 2; /* sel phase3*/\r
- uint8_t phase4_mux_sel = 3; /* sel phase4*/\r
- uint8_t phase5_mux_sel = 4; /* sel phase5*/\r
- uint8_t phase6_mux_sel = 5; /* sel phase6*/\r
- uint8_t phase7_mux_sel = 6; /* sel phase7*/\r
- uint8_t phase8_mux_sel = 7; /* sel phase8*/\r
+ uint8_t phase1_mux_sel = 0; /* sel phase1*/ \r
+ uint8_t phase8_mux_sel = 7; /* sel phase8*/\r
\r
\r
- uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase1_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ \r
+ uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ \r
+ uint8_t phase1_tia_res = PS_SINGLE_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */\r
uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */\r
- uint8_t phase1_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase1_pd_sel = ALS_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase1_ldr2_cur = 0;\r
-// uint8_t phase1_of_idac1_cur = 0;\r
-// uint8_t phase1_of_idac2_cur = 0;\r
+ uint8_t phase1_ldr2_cur = 0;\r
uint8_t phase1_ad_inr_ctrl = 3;\r
uint8_t phase1_ad_of_idac_ctrl = 0;\r
-// uint8_t afe_offset = 0;\r
- uint8_t phase1_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase1_led_en = 0; /* phase1 led enable*/ \r
+ uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
-\r
-\r
- uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase2_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase2_led_drv1_cha_sel = GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase2_led_drv2_cha_sel = 0;\r
- uint8_t phase2_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase2_ldr1_cur = 15; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase2_ldr2_cur = 0;\r
-// uint8_t phase2_of_idac1_cur = 0;\r
-// uint8_t phase2_of_idac2_cur = 0;\r
- uint8_t phase2_ad_inr_ctrl = 3;\r
- uint8_t phase2_ad_of_idac_ctrl = 0;\r
-// uint8_t phase2_afe_offset = 0;\r
- uint8_t phase2_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- \r
- uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase3_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase3_led_drv1_cha_sel = RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase3_led_drv2_cha_sel = 0;\r
- uint8_t phase3_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase3_ldr1_cur = 15; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase3_ldr2_cur = 0;\r
-// uint8_t phase3_of_idac1_cur = 0;\r
-// uint8_t phase3_of_idac2_cur = 0;\r
- uint8_t phase3_ad_inr_ctrl = 3;\r
- uint8_t phase3_ad_of_idac_ctrl = 0;\r
-// uint8_t phase3_afe_offset = 0;\r
- uint8_t phase3_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- \r
- uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase4_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase4_led_drv1_cha_sel = IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase4_led_drv2_cha_sel = 0;\r
- uint8_t phase4_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase4_ldr1_cur = 15; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase4_ldr2_cur = 0;\r
-// uint8_t phase4_of_idac1_cur = 0;\r
-// uint8_t phase4_of_idac2_cur = 0;\r
- uint8_t phase4_ad_inr_ctrl = 3;\r
- uint8_t phase4_ad_of_idac_ctrl = 0;\r
-// uint8_t phase4_afe_offset = 0;\r
- uint8_t phase4_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase5_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase5_led_drv2_cha_sel = 0;\r
- uint8_t phase5_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase5_ldr2_cur = 0;\r
-// uint8_t phase5_of_idac1_cur = 0;\r
-// uint8_t phase5_of_idac2_cur = 0;\r
- uint8_t phase5_ad_inr_ctrl = 3;\r
- uint8_t phase5_ad_of_idac_ctrl = 0;\r
-// uint8_t phase5_afe_offset = 0;\r
- uint8_t phase5_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase6_led_drv2_cha_sel = 0;\r
- uint8_t phase6_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase6_ldr2_cur = 0;\r
-// uint8_t phase6_of_idac1_cur = 0;\r
-// uint8_t phase6_of_idac2_cur = 0;\r
- uint8_t phase6_ad_inr_ctrl = 3;\r
- uint8_t phase6_ad_of_idac_ctrl = 0;\r
-// uint8_t phase6_afe_offset = 0;\r
- uint8_t phase6_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase7_led_drv2_cha_sel = 0;\r
- uint8_t phase7_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
- uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase7_ldr2_cur = 0;\r
-// uint8_t phase7_of_idac1_cur = 0;\r
-// uint8_t phase7_of_idac2_cur = 0;\r
- uint8_t phase7_ad_inr_ctrl = 3;\r
- uint8_t phase7_ad_of_idac_ctrl = 0;\r
-// uint8_t phase7_afe_offset = 0;\r
- uint8_t phase7_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
- uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
-\r
- uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase8_led_drv1_cha_sel = 0; //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ \r
+ \r
+ uint8_t phase8_tia_res = 3; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase8_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase8_led_drv2_cha_sel = 0;\r
- uint8_t phase8_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase8_pd_sel = 0; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase8_ldr1_cur = 20; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase8_ldr2_cur = 0;\r
-// uint8_t phase8_of_idac1_cur = 0;\r
-// uint8_t phase8_of_idac2_cur = 0;\r
+ uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase8_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase8_ldr2_cur = 0;\r
uint8_t phase8_ad_inr_ctrl = 3;\r
uint8_t phase8_ad_of_idac_ctrl = 0;\r
-// uint8_t phase8_afe_offset = 0;\r
- uint8_t phase8_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase8_led_en = 0; /* phase1 led enable*/ \r
+ uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
- uint8_t init_wait_delay = 5 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ;\r
+ uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ;\r
4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ \r
\r
uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ;\r
4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */\r
\r
- uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/\r
- \r
+ uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/\r
+\r
uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ \r
- \r
- uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ \r
- \r
- uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ;\r
+\r
+ uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ \r
+ \r
+ uint8_t led_on_time = 3; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ;\r
4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */\r
\r
hx3695_delay_ms(10); \r
- \r
+ \r
hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6\r
hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8>\r
hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> \r
\r
hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); \r
- hx3695_write_reg(0X2d, phase7_8_internal); \r
- hx3695_write_reg(0X2e, 0x33);// gpio ctrl \r
+ hx3695_write_reg(0X2d, phase7_8_internal); \r
+ hx3695_write_reg(0X2e, 0x33);// gpio ctrl \r
hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay));\r
- hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
- hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
-\r
+ \r
+ hx3695_write_reg(0X30, (phase8_led_en<<7 | phase1_led_en));\r
+ hx3695_write_reg(0X72, (phase8_led_en<<7 | phase1_led_en));\r
+ hx3695_write_reg(0X2e, 0x33);// gpio ctrl \r
\r
hx3695_write_reg(0X31, (led_on_time<<4| 0x00));\r
- hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置；\r
- hx3695_write_reg(0X34, 0x00);// 中断特殊配置；\r
- hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置；\r
- hx3695_write_reg(0X38, 0x00);\r
+ hx3695_write_reg(0X33, 0x83);// �жϼ��Լ��������ã�\r
+ hx3695_write_reg(0X34, 0x00);// �ж��������ã�\r
+ hx3695_write_reg(0X36, 0x00);// phase data ready ��־���ã�\r
+ hx3695_write_reg(0X38, 0x00);\r
\r
hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); \r
hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); \r
hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); \r
hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num );\r
hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num );\r
- \r
- hx3695_write_reg(0X43, phase1_mux_sel); \r
- hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); \r
- hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase1_als_offset_idac);\r
- hx3695_write_reg(0X48, phase1_led_offset_idac);\r
-\r
+ hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num );\r
+ hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num );\r
+ \r
+ hx3695_write_reg(0X43, phase1_mux_sel); \r
+ hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); \r
+ hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase1_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase1_led_offset_idac);\r
hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4);\r
-\r
-// hx3695_write_reg(0X4e, thred_value);\r
-// hx3695_write_reg(0X4f, thred_value>>5);\r
- \r
- hx3695_write_reg(0X43, phase2_mux_sel); \r
- hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); \r
- hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase2_als_offset_idac);\r
- hx3695_write_reg(0X48, phase2_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4);\r
- \r
-//phase3 sel\r
-\r
- hx3695_write_reg(0X43, phase3_mux_sel); \r
- hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); \r
- hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase3_als_offset_idac);\r
- hx3695_write_reg(0X48, phase3_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4);\r
- \r
-//phase4 sel\r
-\r
- hx3695_write_reg(0X43, phase4_mux_sel); \r
- hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); \r
- hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase4_als_offset_idac);\r
- hx3695_write_reg(0X48, phase4_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4);\r
-\r
- hx3695_write_reg(0X43, phase5_mux_sel); \r
- hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); \r
- hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase5_pd_sel)); //<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase5_als_offset_idac);\r
- hx3695_write_reg(0X48, phase5_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
- hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase6_mux_sel); \r
- hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); \r
- hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase6_als_offset_idac);\r
- hx3695_write_reg(0X48, phase6_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase6_led_offset_idac);\r
- hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase7_mux_sel); \r
- hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); \r
- hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase7_als_offset_idac);\r
- hx3695_write_reg(0X48, phase7_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase7_led_offset_idac);\r
- hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase8_mux_sel); \r
- hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); \r
- hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase8_als_offset_idac);\r
- hx3695_write_reg(0X48, phase8_led_offset_idac);\r
-// hx3695_write_reg(0X48, phas8_led_offset_idac);\r
+ hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4);\r
+ \r
+ hx3695_write_reg(0X43, phase8_mux_sel); \r
+ hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); \r
+ hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase8_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase8_led_offset_idac);\r
hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4);\r
\r
-\r
// analog circuit cfg \r
- hx3695_write_reg(0X60, 0x14); //\r
- hx3695_write_reg(0X61, 0xf0); \r
- hx3695_write_reg(0X62, 0x22); \r
- hx3695_write_reg(0X63, 0x15); \r
- \r
- hx3695_write_reg(0X64, 0x08); \r
- hx3695_write_reg(0X65, 0x88); //bug\r
- \r
- hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30\r
- hx3695_write_reg(0X67, 0x23); \r
- hx3695_write_reg(0X68, 0x46); \r
- hx3695_write_reg(0X69, 0x42); \r
- \r
- hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg\r
- hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable\r
+ hx3695_write_reg(0X60, 0x34); //\r
+ hx3695_write_reg(0X61, 0xf0); \r
+ hx3695_write_reg(0X62, 0x22); \r
+ hx3695_write_reg(0X63, 0x15); \r
+ \r
+ hx3695_write_reg(0X64, 0x08); \r
+ hx3695_write_reg(0X65, 0x88); //bug\r
+ \r
+ hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30\r
+ hx3695_write_reg(0X67, 0x23); \r
+ hx3695_write_reg(0X68, 0x46); \r
+ hx3695_write_reg(0X69, 0x42); \r
+ \r
+ hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg\r
+ hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable\r
\r
hx3695_write_reg(0X6a, 0X0f); \r
- hx3695_write_reg(0X6b, 0X22); \r
- hx3695_write_reg(0X6c, 0X00); \r
- hx3695_write_reg(0X6d, 0X37); \r
- hx3695_write_reg(0X6e, 0X82); \r
- hx3695_write_reg(0X6f, 0X08);\r
+ hx3695_write_reg(0X6b, 0X22); \r
+ hx3695_write_reg(0X6c, 0X00); \r
+ hx3695_write_reg(0X6d, 0X37); \r
+ hx3695_write_reg(0X6e, 0X82); \r
+ hx3695_write_reg(0X6f, 0X00);\r
/////////FIFO and adc conversion ready config////////\r
/////////FIFO and adc conversion ready config////////\r
-#if defined(PPG_INT_MODE)\r
- hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear\r
- hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int\r
-#elif defined(INT_MODE) //FIFO_ALL_MOST_FULL)\r
- hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
- 0011=p4;0100=p5;0101=p6;0110=p7;\\r
- bits<7> fifo enble\r
- hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark\r
- hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] \r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear\r
- hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
+#if defined(INT_MODE) //(FIFO_ALL_MOST_FULL)\r
+ hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;0011=p4;0100=p5;0101=p6;0110=p7;bits<7> fifo enble\r
+ hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark\r
+ hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] \r
+ hx3695_write_reg(0X33, 0x83); // int width \r
+ hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
\r
#else\r
- hx3695_write_reg(0X1b, 0x92); // bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\r
- // 0011=p4;0100=p5;0101=p6;0110=p7;\r
- // bits<7> fifo enble \r
- hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int\r
- \r
+ hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;0011=p4;0100=p5;0101=p6;0110=p7;\bits<7> fifo enble \r
+ hx3695_write_reg(0X36, 0x00); //intrupt \r
+ hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int\r
+\r
#endif\r
\r
\r
- hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); \r
- hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); \r
- hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) );\r
- hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); \r
+ hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); \r
+ hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); \r
+ hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) );\r
+ hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); \r
\r
// hx3695_write_reg(0X5c, 0x02);//soft reset\r
- hx3695_delay_ms(5); \r
- hx3695_write_reg(0X5c, 0x00);//release\r
-// read_fifo_first_flg = 1;\r
+ hx3695_delay_ms(5); \r
+ hx3695_write_reg(0X5c, 0x00);//release\r
+\r
return ;\r
}\r
\r
-void hx3695_factory_ft_int_test_config(void)//中断测试配置\r
+void hx3695_factory_ft_aging_check_config(void)\r
{\r
- uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
+ uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/\r
uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */\r
\r
- uint8_t adc_rst_post_num=0; /* 00=16,01=32,10=64,11=128*/ \r
- uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
+ uint16_t fifo_watermark= 250 ;\r
+ uint8_t adc_rst_post_num= 0; /* 00=16,01=32,10=64,11=128*/ \r
+ uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ \r
uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/\r
uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/\r
- uint8_t phase7_8_internal = 0; /* phase7 and phase8 prf internal cfg */\r
- \r
+ uint8_t phase7_8_internal = 0; //0x18; /* phase7 and phase8 prf internal cfg */\r
+\r
+ \r
uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ \r
uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */\r
- uint8_t phase5_enable = 0; /*phase5_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase6_enable = 0; /*phase6_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase7_enable = 0; /*phase7_enable , 1 mean enable ; 0 mean disable */ \r
- uint8_t phase8_enable = 0; /*phase8_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase5_enable = 1; /*phase5_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase6_enable = 1; /*phase6_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase7_enable = 1; /*phase7_enable , 1 mean enable ; 0 mean disable */ \r
+ uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ \r
\r
uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
- uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
+ uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/\r
\r
- uint8_t phase1_mux_sel = 0; /* sel phase1*/\r
- uint8_t phase2_mux_sel = 1; /* sel phase2*/\r
- uint8_t phase3_mux_sel = 2; /* sel phase3*/\r
- uint8_t phase4_mux_sel = 3; /* sel phase4*/\r
- uint8_t phase5_mux_sel = 4; /* sel phase5*/\r
- uint8_t phase6_mux_sel = 5; /* sel phase6*/\r
- uint8_t phase7_mux_sel = 6; /* sel phase7*/\r
- uint8_t phase8_mux_sel = 7; /* sel phase8*/\r
+ uint8_t phase1_mux_sel = 0; /* sel phase1*/\r
+ uint8_t phase2_mux_sel = 1; /* sel phase2*/\r
+ uint8_t phase3_mux_sel = 2; /* sel phase3*/\r
+ uint8_t phase4_mux_sel = 3; /* sel phase4*/\r
+ uint8_t phase5_mux_sel = 4; /* sel phase5*/\r
+ uint8_t phase6_mux_sel = 5; /* sel phase6*/\r
+ uint8_t phase7_mux_sel = 6; /* sel phase7*/\r
+ uint8_t phase8_mux_sel = 7; /* sel phase8*/\r
\r
\r
- uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase1_tia_res = 3; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ uint8_t phase1_tia_res = PS_AGING_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */\r
uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */\r
- uint8_t phase1_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
- uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase1_pd_sel = ALS_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase1_als_offset_idac = 1; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
+ uint8_t phase1_led_offset_idac = 1; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase1_ldr2_cur = 0;\r
-// uint8_t phase1_of_idac1_cur = 0;\r
-// uint8_t phase1_of_idac2_cur = 0;\r
+ uint8_t phase1_ldr2_cur = 0;\r
uint8_t phase1_ad_inr_ctrl = 3;\r
uint8_t phase1_ad_of_idac_ctrl = 0;\r
-// uint8_t afe_offset = 0;\r
- uint8_t phase1_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase1_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
\r
\r
- uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase2_tia_res = 3; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase2_led_drv1_cha_sel = GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase2_led_drv2_cha_sel = 0;\r
- uint8_t phase2_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
+ uint8_t phase2_tia_res = PS_AGING_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase2_led_drv1_cha_sel = LDR0_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase2_led_drv2_cha_sel = LDR0_FT_SEL;\r
+ uint8_t phase2_pd_sel = LDR0_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase2_ldr1_cur = 15; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase2_ldr2_cur = 0;\r
-// uint8_t phase2_of_idac1_cur = 0;\r
-// uint8_t phase2_of_idac2_cur = 0;\r
+ uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase2_ldr1_cur = DRV1_AGING_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase2_ldr2_cur = DRV2_AGING_CUR;\r
uint8_t phase2_ad_inr_ctrl = 3;\r
uint8_t phase2_ad_of_idac_ctrl = 0;\r
-// uint8_t phase2_afe_offset = 0;\r
- uint8_t phase2_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase2_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
\r
uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase3_tia_res = 3; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase3_led_drv1_cha_sel = RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase3_led_drv2_cha_sel = 0;\r
- uint8_t phase3_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase3_tia_res = PS_AGING_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase3_led_drv1_cha_sel = LDR1_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase3_led_drv2_cha_sel = LDR1_FT_SEL;\r
+ uint8_t phase3_pd_sel = LDR1_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase3_ldr1_cur = 15; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase3_ldr2_cur = 0;\r
-// uint8_t phase3_of_idac1_cur = 0;\r
-// uint8_t phase3_of_idac2_cur = 0;\r
+ uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase3_ldr1_cur = DRV1_AGING_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase3_ldr2_cur = DRV2_AGING_CUR;\r
uint8_t phase3_ad_inr_ctrl = 3;\r
uint8_t phase3_ad_of_idac_ctrl = 0;\r
-// uint8_t phase3_afe_offset = 0;\r
- uint8_t phase3_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase3_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
\r
uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase4_tia_res = 3; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase4_led_drv1_cha_sel = IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase4_led_drv2_cha_sel = 0;\r
- uint8_t phase4_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
+ uint8_t phase4_tia_res = PS_AGING_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase4_led_drv1_cha_sel = LDR2_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase4_led_drv2_cha_sel = LDR2_FT_SEL;\r
+ uint8_t phase4_pd_sel = LDR2_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/\r
uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase4_ldr1_cur = 15; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase4_ldr2_cur = 0;\r
-// uint8_t phase4_of_idac1_cur = 0;\r
-// uint8_t phase4_of_idac2_cur = 0;\r
+ uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase4_ldr1_cur = DRV1_AGING_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase4_ldr2_cur = DRV2_AGING_CUR;\r
uint8_t phase4_ad_inr_ctrl = 3;\r
uint8_t phase4_ad_of_idac_ctrl = 0;\r
-// uint8_t phase4_afe_offset = 0;\r
- uint8_t phase4_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase4_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase5_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase5_led_drv2_cha_sel = 0;\r
- uint8_t phase5_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase5_tia_res = PS_AGING_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase5_led_drv1_cha_sel = LDR3_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase5_led_drv2_cha_sel = LDR3_FT_SEL;\r
+ uint8_t phase5_pd_sel = LDR3_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase5_ldr2_cur = 0;\r
-// uint8_t phase5_of_idac1_cur = 0;\r
-// uint8_t phase5_of_idac2_cur = 0;\r
+ uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase5_ldr1_cur = DRV1_AGING_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase5_ldr2_cur = DRV2_AGING_CUR;\r
uint8_t phase5_ad_inr_ctrl = 3;\r
uint8_t phase5_ad_of_idac_ctrl = 0;\r
-// uint8_t phase5_afe_offset = 0;\r
- uint8_t phase5_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase5_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase6_led_drv2_cha_sel = 0;\r
- uint8_t phase6_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase6_tia_res = PS_AGING_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase6_led_drv1_cha_sel = LDR4_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase6_led_drv2_cha_sel = LDR4_FT_SEL;\r
+ uint8_t phase6_pd_sel = LDR4_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase6_ldr2_cur = 0;\r
-// uint8_t phase6_of_idac1_cur = 0;\r
-// uint8_t phase6_of_idac2_cur = 0;\r
+ uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase6_ldr1_cur = DRV1_AGING_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase6_ldr2_cur = DRV2_AGING_CUR;\r
uint8_t phase6_ad_inr_ctrl = 3;\r
uint8_t phase6_ad_of_idac_ctrl = 0;\r
-// uint8_t phase6_afe_offset = 0;\r
- uint8_t phase6_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase6_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
- uint8_t phase7_led_drv2_cha_sel = 0;\r
- uint8_t phase7_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase7_tia_res = PS_AGING_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase7_led_drv1_cha_sel = LDR5_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase7_led_drv2_cha_sel = LDR5_FT_SEL;\r
+ uint8_t phase7_pd_sel = LDR5_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
- uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase7_ldr2_cur = 0;\r
-// uint8_t phase7_of_idac1_cur = 0;\r
-// uint8_t phase7_of_idac2_cur = 0;\r
+ uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase7_ldr1_cur = DRV1_AGING_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
+ uint8_t phase7_ldr2_cur = DRV2_AGING_CUR;\r
uint8_t phase7_ad_inr_ctrl = 3;\r
uint8_t phase7_ad_of_idac_ctrl = 0;\r
-// uint8_t phase7_afe_offset = 0;\r
- uint8_t phase7_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase7_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/\r
- uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
- uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
- uint8_t phase8_led_drv1_cha_sel = 0; //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
+ uint8_t phase8_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/\r
+ uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */\r
+ uint8_t phase8_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */\r
uint8_t phase8_led_drv2_cha_sel = 0;\r
- uint8_t phase8_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */\r
+ uint8_t phase8_pd_sel = 0; /* 1 = pd1; 2 = pd2; */\r
uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */\r
- uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
+ uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */\r
uint8_t phase8_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */\r
- uint8_t phase8_ldr2_cur = 0;\r
-// uint8_t phase8_of_idac1_cur = 0;\r
-// uint8_t phase8_of_idac2_cur = 0;\r
+ uint8_t phase8_ldr2_cur = 0;\r
uint8_t phase8_ad_inr_ctrl = 3;\r
uint8_t phase8_ad_of_idac_ctrl = 0;\r
-// uint8_t phase8_afe_offset = 0;\r
- uint8_t phase8_led_en = 1; /* phase1 led enable*/\r
- \r
- uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
+ uint8_t phase8_led_en = 1; /* phase1 led enable*/ \r
+ uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */\r
uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */\r
\r
- uint8_t init_wait_delay = 5 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ;\r
+ uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ;\r
4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ \r
\r
uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ;\r
4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */\r
\r
- uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/\r
- \r
+ uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/\r
+\r
uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ \r
- \r
- uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ \r
- \r
+\r
+ uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ \r
+ \r
uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ;\r
4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */\r
\r
hx3695_delay_ms(10); \r
- \r
+ \r
hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6\r
hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8>\r
hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> \r
\r
hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); \r
- hx3695_write_reg(0X2d, phase7_8_internal); \r
- hx3695_write_reg(0X2e, 0x33);// gpio ctrl \r
+ hx3695_write_reg(0X2d, phase7_8_internal); \r
+ hx3695_write_reg(0X2e, 0x33);// gpio ctrl \r
hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay));\r
- hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
+ hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) );\r
\r
\r
hx3695_write_reg(0X31, (led_on_time<<4| 0x00));\r
- hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置；\r
- hx3695_write_reg(0X34, 0x00);// 中断特殊配置；\r
- hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置；\r
- hx3695_write_reg(0X38, 0x00);\r
+ hx3695_write_reg(0X33, 0x83);// �жϼ��Լ��������ã�\r
+ hx3695_write_reg(0X34, 0x00);// �ж��������ã�\r
+ hx3695_write_reg(0X36, 0x00);// phase data ready ��־���ã�\r
+ hx3695_write_reg(0X38, 0x00);\r
\r
hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); \r
hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); \r
hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); \r
hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num );\r
hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num );\r
- hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num );\r
- \r
- hx3695_write_reg(0X43, phase1_mux_sel); \r
- hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); \r
- hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase1_als_offset_idac);\r
- hx3695_write_reg(0X48, phase1_led_offset_idac);\r
-\r
+ hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num );\r
+ hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num );\r
+ \r
+ hx3695_write_reg(0X43, phase1_mux_sel); \r
+ hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); \r
+ hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase1_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase1_led_offset_idac);\r
hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4);\r
\r
-// hx3695_write_reg(0X4e, thred_value);\r
-// hx3695_write_reg(0X4f, thred_value>>5);\r
- \r
+ \r
hx3695_write_reg(0X43, phase2_mux_sel); \r
- hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); \r
- hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase2_als_offset_idac);\r
- hx3695_write_reg(0X48, phase2_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
+ hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); \r
+ hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase2_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase2_led_offset_idac);\r
hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4);\r
\r
//phase3 sel\r
\r
hx3695_write_reg(0X43, phase3_mux_sel); \r
- hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); \r
- hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase3_als_offset_idac);\r
- hx3695_write_reg(0X48, phase3_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
+ hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); \r
+ hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase3_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase3_led_offset_idac);\r
hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4);\r
\r
//phase4 sel\r
\r
hx3695_write_reg(0X43, phase4_mux_sel); \r
- hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); \r
- hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase4_als_offset_idac);\r
- hx3695_write_reg(0X48, phase4_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
+ hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); \r
+ hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase4_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase4_led_offset_idac);\r
hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4);\r
-\r
- hx3695_write_reg(0X43, phase5_mux_sel); \r
- hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); \r
- hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase5_pd_sel)); //<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase5_als_offset_idac);\r
- hx3695_write_reg(0X48, phase5_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase1_led_offset_idac);\r
+ hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4);\r
+\r
+ hx3695_write_reg(0X43, phase5_mux_sel); \r
+ hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); \r
+ hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase5_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase5_led_offset_idac);\r
hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4);\r
- \r
- \r
- hx3695_write_reg(0X43, phase6_mux_sel); \r
- hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); \r
- hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase6_als_offset_idac);\r
- hx3695_write_reg(0X48, phase6_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase6_led_offset_idac);\r
+ hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4);\r
+ \r
+ \r
+ hx3695_write_reg(0X43, phase6_mux_sel); \r
+ hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); \r
+ hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase6_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase6_led_offset_idac);\r
hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4);\r
\r
\r
- hx3695_write_reg(0X43, phase7_mux_sel); \r
- hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); \r
- hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase7_als_offset_idac);\r
- hx3695_write_reg(0X48, phase7_led_offset_idac);\r
-// hx3695_write_reg(0X48, phase7_led_offset_idac);\r
+ hx3695_write_reg(0X43, phase7_mux_sel); \r
+ hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); \r
+ hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase7_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase7_led_offset_idac);\r
hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4);\r
\r
\r
- hx3695_write_reg(0X43, phase8_mux_sel); \r
- hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); \r
- hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR\r
- hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur\r
- hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00));\r
- hx3695_write_reg(0X47, phase8_als_offset_idac);\r
- hx3695_write_reg(0X48, phase8_led_offset_idac);\r
-// hx3695_write_reg(0X48, phas8_led_offset_idac);\r
+ hx3695_write_reg(0X43, phase8_mux_sel); \r
+ hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); \r
+ hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR\r
+ hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur\r
+ hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00));\r
+ hx3695_write_reg(0X47, phase8_als_offset_idac);\r
+ hx3695_write_reg(0X48, phase8_led_offset_idac);\r
hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); \r
- hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel);\r
- hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel);\r
- hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4);\r
+ hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel);\r
+ hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel);\r
+ hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4);\r
\r
\r
// analog circuit cfg \r
- hx3695_write_reg(0X60, 0x14); //\r
- hx3695_write_reg(0X61, 0xf0); \r
- hx3695_write_reg(0X62, 0x22); \r
- hx3695_write_reg(0X63, 0x15); \r
- \r
- hx3695_write_reg(0X64, 0x08); \r
- hx3695_write_reg(0X65, 0x88); //bug\r
- \r
- hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30\r
- hx3695_write_reg(0X67, 0x23); \r
- hx3695_write_reg(0X68, 0x46); \r
- hx3695_write_reg(0X69, 0x42); \r
- \r
- hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg\r
- hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable\r
+ hx3695_write_reg(0X60, 0x34); //\r
+ hx3695_write_reg(0X61, 0xf0); \r
+ hx3695_write_reg(0X62, 0x22); \r
+ hx3695_write_reg(0X63, 0x15); \r
+ \r
+ hx3695_write_reg(0X64, 0x08); \r
+ hx3695_write_reg(0X65, 0x88); //bug\r
+ \r
+ hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30\r
+ hx3695_write_reg(0X67, 0x23); \r
+ hx3695_write_reg(0X68, 0x46); \r
+ hx3695_write_reg(0X69, 0x42); \r
+ \r
+ hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg\r
+ hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable\r
\r
hx3695_write_reg(0X6a, 0X0f); \r
- hx3695_write_reg(0X6b, 0X22); \r
- hx3695_write_reg(0X6c, 0X00); \r
- hx3695_write_reg(0X6d, 0X37); \r
- hx3695_write_reg(0X6e, 0X82); \r
- hx3695_write_reg(0X6f, 0X08);\r
+ hx3695_write_reg(0X6b, 0X22); \r
+ hx3695_write_reg(0X6c, 0X00); \r
+ hx3695_write_reg(0X6d, 0X37); \r
+ hx3695_write_reg(0X6e, 0X82); \r
+ hx3695_write_reg(0X6f, 0X00);\r
/////////FIFO and adc conversion ready config////////\r
/////////FIFO and adc conversion ready config////////\r
-#if defined(PPG_INT_MODE)\r
- hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\r
- // 0011=p4;0100=p5;0101=p6;0110=p7;\r
- // bits<7> fifo enble\r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear\r
- hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int\r
-#elif defined(INT_MODE) //FIFO_ALL_MOST_FULL)\r
- hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\r
- // 0011=p4;0100=p5;0101=p6;0110=p7;\r
- // bits<7> fifo enble\r
- hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark\r
- hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] \r
- hx3695_write_reg(0X33, 0x83); // int width \r
- hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear\r
- hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
+#if defined(INT_MODE) //(FIFO_ALL_MOST_FULL)\r
+ hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\\r
+ 0011=p4;0100=p5;0101=p6;0110=p7;\\r
+ bits<7> fifo enble\r
+ hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark\r
+ hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] \r
+ hx3695_write_reg(0X33, 0x83); // int width \r
+ hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int\r
\r
#else\r
- hx3695_write_reg(0X1b, 0x92); // bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\r
- // 0011=p4;0100=p5;0101=p6;0110=p7;\r
- // bits<7> fifo enble \r
- hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int\r
- \r
+ hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;0011=p4;0100=p5;0101=p6;0110=p7;bits<7> fifo enble \r
+ hx3695_write_reg(0X36, 0x00); //intrupt \r
+ \r
+ hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int\r
+\r
#endif\r
\r
\r
- hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); \r
- hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); \r
- hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) );\r
- hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); \r
+ hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); \r
+ hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); \r
+ hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) );\r
+ hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); \r
\r
// hx3695_write_reg(0X5c, 0x02);//soft reset\r
- hx3695_delay_ms(5); \r
- hx3695_write_reg(0X5c, 0x00);//release\r
+ hx3695_delay_ms(5); \r
+ hx3695_write_reg(0X5c, 0x00);//release\r
\r
- \r
+ return ;\r
+ \r
}\r
\r
bool hx3695_factory_test_read(int32_t *phase_data)\r
{\r
uint8_t databuf[12] = {0};\r
+ uint8_t databuf2[12] = {0};\r
int32_t P1 = 0, P2 = 0,P3 = 0,P4 = 0;\r
+ int32_t P5 = 0, P6 = 0,P7 = 0,P8 = 0;\r
+ uint8_t m,k;\r
hx3695_brust_read_reg(0x03, databuf, 12);\r
+ hx3695_brust_read_reg(0x0F, databuf2, 12);\r
P1 = ((databuf[0])|(databuf[1]<<8)|(databuf[2]<<16));\r
P2 = ((databuf[3])|(databuf[4]<<8)|(databuf[5]<<16));\r
P3 = ((databuf[6])|(databuf[7]<<8)|(databuf[8]<<16));\r
P4 = ((databuf[9])|(databuf[10]<<8)|(databuf[11]<<16));\r
-\r
+ \r
+ P5 = ((databuf2[0])|(databuf2[1]<<8)|(databuf2[2]<<16));\r
+ P6 = ((databuf2[3])|(databuf2[4]<<8)|(databuf2[5]<<16));\r
+ P7 = ((databuf2[6])|(databuf2[7]<<8)|(databuf2[8]<<16));\r
+ P8 = ((databuf2[9])|(databuf2[10]<<8)|(databuf2[11]<<16));\r
phase_data[0] = P1 ;\r
phase_data[1] = P2 ;\r
phase_data[2] = P3 ;\r
phase_data[3] = P4 ;\r
+ phase_data[4] = P5 ;\r
+ phase_data[5] = P6 ;\r
+ phase_data[6] = P7 ;\r
+ phase_data[7] = P8 ;\r
+ \r
+// DEBUG_PRINTF("p1,p2,p3,p4,p5,p6,p7 %d %d %d %d %d %d %d\r\n", P1, P2, P3, P4,P5, P6,P7);\r
\r
- DEBUG_PRINTF("p1,p2,p3,p4 %d %d %d %d\r\n", P1, P2, P3, P4);\r
return true;\r
}\r
-\r
int32_t hx3695_sort_cal(int32_t *data)\r
{\r
uint8_t ii,jj;\r
data_final = (data[1]+data[2])>>1;\r
return data_final;\r
}\r
-\r
+int32_t hx3695_sort_cal_min(int32_t *data)\r
+{\r
+ uint8_t ii,jj;\r
+ int32_t data_temp = 0;\r
+ int32_t data_final = 0;\r
+ for(ii=0; ii<(TEST_NUM-1); ii++)\r
+ {\r
+ for(jj=0; jj<9-ii; jj++)\r
+ {\r
+ if(data[jj]>=data[jj+1])\r
+ {\r
+ data_temp = data[jj];\r
+ data[jj] = data[jj+1];\r
+ data[jj+1] = data_temp;\r
+ }\r
+ }\r
+ }\r
+ data_final = data[0];\r
+ return data_final;\r
+}\r
+int32_t hx3695_sort_cal_mid(int32_t *data)\r
+{\r
+ uint8_t ii,jj;\r
+ int32_t data_temp = 0;\r
+ int32_t data_final = 0;\r
+ for(ii=0; ii<(TEST_NUM-1); ii++)\r
+ {\r
+ for(jj=0; jj<9-ii; jj++)\r
+ {\r
+ if(data[jj]>=data[jj+1])\r
+ {\r
+ data_temp = data[jj];\r
+ data[jj] = data[jj+1];\r
+ data[jj+1] = data_temp;\r
+ }\r
+ }\r
+ }\r
+ data_final = ((data[3]+data[4]+data[5]+data[6]+data[7]+data[8])/6);\r
+ return data_final;\r
+}\r
+int32_t hx3695_sort_cal_max(int32_t *data)\r
+{\r
+ uint8_t ii,jj;\r
+ int32_t data_temp = 0;\r
+ int32_t data_final = 0;\r
+ for(ii=0; ii<(TEST_NUM-1); ii++)\r
+ {\r
+ for(jj=0; jj<9-ii; jj++)\r
+ {\r
+ if(data[jj]>=data[jj+1])\r
+ {\r
+ data_temp = data[jj];\r
+ data[jj] = data[jj+1];\r
+ data[jj+1] = data_temp;\r
+ }\r
+ }\r
+ }\r
+ data_final = data[9];\r
+ return data_final;\r
+}\r
\r
bool hx3695_chip_check_id(void)\r
{\r
return false;\r
}\r
\r
-FT_RESULTS_t hx3695_factory_led_off_get_result(void)\r
+bool hx3695_led_off(void)\r
{\r
- uint8_t ii = 0;\r
- int32_t phase_data[4] = {0,0,0,0};\r
- int32_t phase1_data[4] = {0,0,0,0};\r
- int32_t phase2_data[4] = {0,0,0,0};\r
- int32_t phase3_data[4] = {0,0,0,0};\r
- int32_t phase4_data[4] = {0,0,0,0};\r
- int32_t gr_buffer[4] = {0,0,0,0};\r
- int32_t red_buffer[4] = {0,0,0,0};\r
- int32_t ir_buffer[4] = {0,0,0,0};\r
- FT_RESULTS_t ft_result = {0,0,0,0,0,0,0,0,0,0,0,0};\r
+ hx3695_delay_ms(10);\r
+ hx3695_write_reg(0x30, 0x00);\r
+ hx3695_write_reg(0x72, 0x00);\r
+ hx3695_delay_ms(100);\r
+ return 1;\r
+}\r
\r
+FT_RESULTS_t hx3695_factory_ft_leak_light_test_get_result(void)\r
+{\r
+ uint8_t ii = 0;\r
+ int32_t phase_data[8] = {0,0,0,0,0,0,0,0};\r
+ int32_t ldr0_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr1_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr2_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr3_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr4_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr5_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr0_OFF_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr1_OFF_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr2_OFF_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr3_OFF_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr4_OFF_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr5_OFF_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr0_data_ledoff = 0;\r
+ int32_t ldr1_data_ledoff = 0;\r
+ int32_t ldr2_data_ledoff = 0;\r
+ int32_t ldr3_data_ledoff = 0;\r
+ int32_t ldr4_data_ledoff = 0;\r
+ int32_t ldr5_data_ledoff = 0;\r
+ int32_t ldr0_data_ledon = 0;\r
+ int32_t ldr1_data_ledon = 0;\r
+ int32_t ldr2_data_ledon = 0;\r
+ int32_t ldr3_data_ledon = 0;\r
+ int32_t ldr4_data_ledon = 0;\r
+ int32_t ldr5_data_ledon = 0;\r
+// uint8_t i,j;\r
+ FT_RESULTS_t ft_result = {0};\r
+\r
+ for(ii=0; ii<TEST_NUM; ii++)\r
+ {\r
+ hx3695_delay_ms(40);\r
+ hx3695_factory_test_read(phase_data);\r
+ \r
+ for(int j=1;j<(LDR_NUM+1);j++)\r
+ {\r
+\r
+ phase_result[ii][j] = phase_data[j];\r
+ \r
+ DEBUG_PRINTF("%d ", phase_result[ii][j]);\r
+ }\r
+ \r
+ DEBUG_PRINTF("\n");\r
+ \r
+ ldr0_buffer[ii] = phase_data[1] - phase_data[0];\r
+ ldr1_buffer[ii] = phase_data[2] - phase_data[0];\r
+ ldr2_buffer[ii] = phase_data[3] - phase_data[0];\r
+ \r
+ ldr3_buffer[ii] = phase_data[4] - phase_data[0];\r
+ ldr4_buffer[ii] = phase_data[5] - phase_data[0];\r
+ ldr5_buffer[ii] = phase_data[6] - phase_data[0];\r
+ \r
+ }\r
+ ldr0_data_ledon = hx3695_sort_cal_max(ldr0_buffer);\r
+ ldr1_data_ledon = hx3695_sort_cal_max(ldr1_buffer);\r
+ ldr2_data_ledon = hx3695_sort_cal_max(ldr2_buffer);\r
+ ldr3_data_ledon = hx3695_sort_cal_max(ldr3_buffer);\r
+ ldr4_data_ledon = hx3695_sort_cal_max(ldr4_buffer);\r
+ ldr5_data_ledon = hx3695_sort_cal_max(ldr5_buffer);\r
+\r
+ hx3695_led_off();\r
+// DEBUG_PRINTF("LED_OFF RESULTS:\r\n ");\r
for(ii=0; ii<4; ii++)\r
{\r
hx3695_delay_ms(40);\r
hx3695_factory_test_read(phase_data);\r
- gr_buffer[ii] = phase_data[1] - phase_data[0];\r
- red_buffer[ii] = phase_data[2] - phase_data[0];\r
- ir_buffer[ii] = phase_data[3] - phase_data[0];\r
- phase1_data[ii] = phase_data[0];\r
- phase2_data[ii] = phase_data[1];\r
- phase3_data[ii] = phase_data[2];\r
- phase4_data[ii] = phase_data[3];\r
+// for(int j=1;j<(LDR_NUM+1);j++)\r
+// {\r
+\r
+// phase_result[ii][j] = phase_data[j];\r
+// DEBUG_PRINTF("%d ", phase_result[ii][j]);\r
+// }\r
+// \r
+// DEBUG_PRINTF("\n");\r
+// \r
+ ldr0_OFF_buffer[ii] = phase_data[1] - phase_data[0];\r
+ ldr1_OFF_buffer[ii] = phase_data[2] - phase_data[0];\r
+ ldr2_OFF_buffer[ii] = phase_data[3] - phase_data[0];\r
+ \r
+ ldr3_OFF_buffer[ii] = phase_data[4] - phase_data[0];\r
+ ldr4_OFF_buffer[ii] = phase_data[5] - phase_data[0];\r
+ ldr5_OFF_buffer[ii] = phase_data[6] - phase_data[0];\r
}\r
- ft_result.phase1_data_avg = hx3695_sort_cal(phase1_data);\r
- ft_result.phase2_data_avg = hx3695_sort_cal(phase2_data);\r
- ft_result.phase3_data_avg = hx3695_sort_cal(phase3_data);\r
- ft_result.phase4_data_avg = hx3695_sort_cal(phase4_data);\r
- ft_result.gr_ps_dif = hx3695_sort_cal(gr_buffer);\r
- ft_result.red_ps_dif = hx3695_sort_cal(red_buffer);\r
- ft_result.ir_ps_dif = hx3695_sort_cal(ir_buffer);\r
+ ldr0_data_ledoff = hx3695_sort_cal(ldr0_buffer);\r
+ ldr1_data_ledoff = hx3695_sort_cal(ldr1_buffer);\r
+ ldr2_data_ledoff = hx3695_sort_cal(ldr2_buffer);\r
+ \r
+ ldr3_data_ledoff = hx3695_sort_cal(ldr3_buffer);\r
+ ldr4_data_ledoff = hx3695_sort_cal(ldr4_buffer);\r
+ ldr5_data_ledoff = hx3695_sort_cal(ldr5_buffer);\r
+ \r
+ ft_result.ldr0_ps_dif = ldr0_data_ledoff;\r
+ ft_result.ldr1_ps_dif = ldr1_data_ledoff;\r
+ ft_result.ldr2_ps_dif = ldr2_data_ledoff;\r
+ \r
+ ft_result.ldr0_data_final = ldr0_data_ledon - ldr0_data_ledoff;\r
+ ft_result.ldr1_data_final = ldr1_data_ledon - ldr1_data_ledoff;\r
+ ft_result.ldr2_data_final = ldr2_data_ledon - ldr2_data_ledoff;\r
+ \r
+ ft_result.ldr3_ps_dif = ldr3_data_ledoff;\r
+ ft_result.ldr4_ps_dif = ldr4_data_ledoff;\r
+ ft_result.ldr5_ps_dif = ldr5_data_ledoff;\r
+ ft_result.ldr3_data_final = ldr3_data_ledon - ldr3_data_ledoff;\r
+ ft_result.ldr4_data_final = ldr4_data_ledon - ldr4_data_ledoff;\r
+ ft_result.ldr5_data_final = ldr5_data_ledon - ldr5_data_ledoff;\r
+ \r
+ \r
+ \r
+ \r
+ if(ft_result.ldr0_data_final<0)\r
+ {\r
+ ft_result.ldr0_data_final = 0;\r
+ }\r
+ if(ft_result.ldr1_data_final<0)\r
+ {\r
+ ft_result.ldr1_data_final = 0;\r
+ }\r
+ if(ft_result.ldr2_data_final<0)\r
+ {\r
+ ft_result.ldr2_data_final = 0;\r
+ }\r
+ \r
+ if(ft_result.ldr3_data_final<0)\r
+ {\r
+ ft_result.ldr3_data_final = 0;\r
+ }\r
+ if(ft_result.ldr4_data_final<0)\r
+ {\r
+ ft_result.ldr4_data_final = 0;\r
+ }\r
+ if(ft_result.ldr5_data_final<0)\r
+ {\r
+ ft_result.ldr5_data_final = 0;\r
+ }\r
+ TYHX_LOG("leaking result 1=%d leaking result2=%d\r\n",ft_result.ldr0_data_final,ft_result.ldr3_data_final);\r
+ //hrsresult.leak_green =ft_result.ldr0_data_final;\r
+ DEBUG_PRINTF("ft card,LDR0:%d,LDR1:%d,LDR2:%d,LDR3:%d,LDR4:%d,LDR5:%d\r\n",ft_result.ldr0_data_final,ft_result.ldr1_data_final,ft_result.ldr2_data_final ,\r
+ ft_result.ldr3_data_final,ft_result.ldr4_data_final,ft_result.ldr5_data_final);\r
+\r
\r
return ft_result;\r
}\r
\r
-FT_RESULTS_t hx3695_factory_wear_mode_get_result(void)\r
+FT_RESULTS_t hx3695_factory_ft_card_test_get_result(void)\r
{\r
uint8_t ii = 0;\r
- int32_t phase_data[4] = {0,0,0,0};\r
- int32_t data_buffer[4] = {0,0,0,0};\r
- FT_RESULTS_t ft_result = {0,0,0,0,0,0,0,0,0,0,0,0};\r
-\r
- for(ii=0; ii<4; ii++)\r
+ int32_t phase_data[8] = {0,0,0,0,0,0,0,0};\r
+ int32_t ldr0_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr1_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr2_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr3_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr4_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr5_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ \r
+ FT_RESULTS_t ft_result = {0};\r
+\r
+ for(ii=0; ii<TEST_NUM; ii++)\r
{\r
- hx3695_delay_ms(110);\r
+ hx3695_delay_ms(40);\r
hx3695_factory_test_read(phase_data);\r
- data_buffer[ii] = phase_data[0] - phase_data[1];\r
+ for(int j=1;j<(LDR_NUM+1);j++)\r
+ {\r
+ phase_result[ii][j] = phase_data[j];\r
+ DEBUG_PRINTF("%d ", phase_result[ii][j]);\r
+ }\r
+ \r
+ DEBUG_PRINTF("\n");\r
+ ldr0_buffer[ii] = phase_data[1] - phase_data[0];\r
+ ldr1_buffer[ii] = phase_data[2] - phase_data[0];\r
+ ldr2_buffer[ii] = phase_data[3] - phase_data[0];\r
+ \r
+ ldr3_buffer[ii] = phase_data[4] - phase_data[0];\r
+ ldr4_buffer[ii] = phase_data[5] - phase_data[0];\r
+ ldr5_buffer[ii] = phase_data[6] - phase_data[0];\r
}\r
- ft_result.gr_data_final = hx3695_sort_cal(data_buffer);\r
- if(data_buffer[0]==data_buffer[1] && data_buffer[0]==data_buffer[2] && data_buffer[0]==data_buffer[3])\r
+ hx3695_led_off();\r
+ \r
+ ft_result.ldr0_data_final = hx3695_sort_cal(ldr0_buffer);\r
+ ft_result.ldr1_data_final = hx3695_sort_cal(ldr1_buffer);\r
+ ft_result.ldr2_data_final = hx3695_sort_cal(ldr2_buffer);\r
+ \r
+ ft_result.ldr3_data_final = hx3695_sort_cal(ldr3_buffer);\r
+ ft_result.ldr4_data_final = hx3695_sort_cal(ldr4_buffer);\r
+ ft_result.ldr5_data_final = hx3695_sort_cal(ldr5_buffer);\r
+ \r
+ DEBUG_PRINTF("ft card,LDR0:%d,LDR1:%d,LDR2:%d,LDR3 :%d,LDR4 :%d,LDR5 :%d\r\n",ft_result.ldr0_data_final,ft_result.ldr1_data_final,ft_result.ldr2_data_final ,\r
+ ft_result.ldr3_data_final,ft_result.ldr4_data_final,ft_result.ldr5_data_final);\r
+ \r
+ if(ldr0_buffer[0] == ldr0_buffer[1] && ldr0_buffer[0] == ldr0_buffer[2] && ldr0_buffer[0] == ldr0_buffer[3])\r
{\r
- ft_result.gr_data_final = 0;\r
+ ft_result.ldr0_data_final = 0;\r
+ ft_result.ldr1_data_final = 0;\r
+ ft_result.ldr2_data_final = 0;\r
+ }\r
+ if(ft_result.ldr0_data_final < 0)\r
+ {\r
+ ft_result.ldr0_data_final = 0;\r
+ }\r
+ if(ft_result.ldr1_data_final < 0)\r
+ {\r
+ ft_result.ldr1_data_final = 0;\r
+ }\r
+ if(ft_result.ldr2_data_final < 0)\r
+ {\r
+ ft_result.ldr2_data_final = 0;\r
+ }\r
+if(ldr3_buffer[0] == ldr3_buffer[1] && ldr3_buffer[0] == ldr3_buffer[2] && ldr3_buffer[0] == ldr3_buffer[3])\r
+ {\r
+ ft_result.ldr3_data_final = 0;\r
+ ft_result.ldr4_data_final = 0;\r
+ ft_result.ldr5_data_final = 0;\r
+ }\r
+ if(ft_result.ldr3_data_final < 0)\r
+ {\r
+ ft_result.ldr3_data_final = 0;\r
+ }\r
+ if(ft_result.ldr4_data_final < 0)\r
+ {\r
+ ft_result.ldr4_data_final = 0;\r
+ }\r
+ if(ft_result.ldr5_data_final < 0)\r
+ {\r
+ ft_result.ldr5_data_final = 0;\r
}\r
-\r
return ft_result;\r
}\r
-\r
-FT_RESULTS_t hx3695_factory_ft_leak_light_test_get_result(void)\r
+FT_RESULTS_t hx3695_factory_Gnoise_result(void)\r
{\r
uint8_t ii = 0;\r
- int32_t phase_data[4] = {0,0,0,0};\r
- int32_t gr_buffer[4] = {0,0,0,0};\r
- int32_t red_buffer[4] = {0,0,0,0};\r
- int32_t ir_buffer[4] = {0,0,0,0};\r
- int32_t gr_data_ledoff = 0;\r
- int32_t red_data_ledoff = 0;\r
- int32_t ir_data_ledoff = 0;\r
- int32_t gr_data_ledon = 0;\r
- int32_t red_data_ledon = 0;\r
- int32_t ir_data_ledon = 0;\r
- FT_RESULTS_t ft_result = {0,0,0,0,0,0,0,0,0,0,0,0};\r
-\r
- for(ii=0; ii<4; ii++)\r
+ int32_t phase_data[8] = {0,0,0,0,0,0,0,0};\r
+ int32_t phase1_data[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t phase2_data[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t phase3_data[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t phase4_data[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t phase5_data[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t phase6_data[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t phase7_data[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t phase8_data[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr0_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr1_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr2_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr3_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr4_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr5_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ FT_RESULTS_t ft_result = {0};\r
+\r
+ for(ii=0; ii<TEST_NUM; ii++)\r
{\r
hx3695_delay_ms(40);\r
hx3695_factory_test_read(phase_data);\r
- gr_buffer[ii] = phase_data[1] - phase_data[0];\r
- red_buffer[ii] = phase_data[2] - phase_data[0];\r
- ir_buffer[ii] = phase_data[3] - phase_data[0];\r
- }\r
- gr_data_ledon = hx3695_sort_cal(gr_buffer);\r
- red_data_ledon = hx3695_sort_cal(red_buffer);\r
- ir_data_ledon = hx3695_sort_cal(ir_buffer);\r
\r
- hx3695_write_reg(0x30, 0x00);\r
- hx3695_write_reg(0x72, 0x00);\r
- hx3695_delay_ms(100);\r
+ phase1_data[ii] = phase_data[0];\r
+ phase2_data[ii] = phase_data[1];\r
+ phase3_data[ii] = phase_data[2];\r
+ phase4_data[ii] = phase_data[3];\r
+ phase5_data[ii] = phase_data[4];\r
+ phase6_data[ii] = phase_data[5];\r
+ phase7_data[ii] = phase_data[6];\r
+ phase8_data[ii] = phase_data[7];\r
+ \r
+ for(int j=1;j<(LDR_NUM+1);j++)\r
+ {\r
+ phase_result[ii][j] = phase_data[j];\r
+ DEBUG_PRINTF("%d ", phase_result[ii][j]);\r
+ }\r
+ DEBUG_PRINTF("\n");\r
+ }\r
+ ft_result.phase1_data_avg = hx3695_sort_cal_max(phase1_data);\r
+ ft_result.phase2_data_avg = hx3695_sort_cal_max(phase2_data);\r
+ ft_result.phase3_data_avg = hx3695_sort_cal_max(phase3_data);\r
+ ft_result.phase4_data_avg = hx3695_sort_cal_max(phase4_data);\r
+ ft_result.phase5_data_avg = hx3695_sort_cal_max(phase5_data);\r
+ ft_result.phase6_data_avg = hx3695_sort_cal_max(phase6_data);\r
+ ft_result.phase7_data_avg = hx3695_sort_cal_max(phase7_data);\r
+ ft_result.phase8_data_avg = hx3695_sort_cal_max(phase8_data);\r
+ \r
+ \r
+ ft_result.ldr0_data_final = hx3695_sort_cal_max(ldr0_buffer);\r
+ ft_result.ldr1_data_final = hx3695_sort_cal_max(ldr1_buffer);\r
+ ft_result.ldr2_data_final = hx3695_sort_cal_max(ldr2_buffer);\r
+ \r
+ ft_result.ldr3_data_final = hx3695_sort_cal_max(ldr3_buffer);\r
+ ft_result.ldr4_data_final = hx3695_sort_cal_max(ldr4_buffer);\r
+ ft_result.ldr5_data_final = hx3695_sort_cal_max(ldr5_buffer);\r
+ \r
+ DEBUG_PRINTF("%d %d %d %d %d %d %d %d %d %d %d %d %d %d\r\n", ft_result.phase1_data_avg, ft_result.phase2_data_avg, ft_result.phase3_data_avg, ft_result.phase4_data_avg, \r
+ ft_result.phase5_data_avg, ft_result.phase6_data_avg, ft_result.phase7_data_avg, ft_result.phase8_data_avg, \r
+ ft_result.ldr0_data_final, ft_result.ldr1_data_final, ft_result.ldr2_data_final,ft_result.ldr3_data_final, ft_result.ldr4_data_final, ft_result.ldr5_data_final);\r
\r
- for(ii=0; ii<4; ii++)\r
+ return ft_result;\r
+}\r
+FT_RESULTS_t hx3695_factory_ft_single_check_get_result(void)\r
+{\r
+ uint8_t ii = 0;\r
+ int32_t phase_data[8] = {0,0,0,0,0,0,0,0};\r
+ int32_t ldr0_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr1_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr2_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr3_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr4_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr5_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ FT_RESULTS_t ft_result = {0};\r
+ \r
+ for(ii=0; ii<TEST_NUM; ii++)\r
+ {\r
+ hx3695_delay_ms(20);\r
+ hx3695_LDR0_led_control(1,32); //1=led on;0=led off;ledcur= (led_config*0.8 )ma\r
+ hx3695_delay_ms(40);\r
+ hx3695_factory_test_read(phase_data); \r
+ ldr0_buffer[ii] = phase_data[1] - phase_data[0];\r
+ DEBUG_PRINTF("LDR0: %d \r\n", ldr0_buffer[ii]);\r
+ }\r
+ ft_result.ldr0_data_final = hx3695_sort_cal_mid(ldr0_buffer);\r
+ \r
+ hx3695_led_off();\r
+ hx3695_delay_ms(1000);\r
+ DEBUG_PRINTF("ft single,LDR0: %d\r\n",ft_result.ldr0_data_final);\r
+ \r
+ for(ii=0; ii<TEST_NUM; ii++)\r
{\r
+ hx3695_delay_ms(20); \r
+ hx3695_LDR1_led_control(1,32); //1=led on;0=led off;ledcur= (led_config*0.8 )ma\r
hx3695_delay_ms(40);\r
hx3695_factory_test_read(phase_data);\r
- gr_buffer[ii] = phase_data[1] - phase_data[0];\r
- red_buffer[ii] = phase_data[2] - phase_data[0];\r
- ir_buffer[ii] = phase_data[3] - phase_data[0];\r
+ ldr1_buffer[ii] = phase_data[2] - phase_data[0];\r
+ DEBUG_PRINTF("LDR1: %d \r\n", ldr1_buffer[ii]);\r
}\r
- gr_data_ledoff = hx3695_sort_cal(gr_buffer);\r
- red_data_ledoff = hx3695_sort_cal(red_buffer);\r
- ir_data_ledoff = hx3695_sort_cal(ir_buffer);\r
-\r
- ft_result.gr_ps_dif = gr_data_ledoff;\r
- ft_result.red_ps_dif = red_data_ledoff;\r
- ft_result.ir_ps_dif = ir_data_ledoff;\r
- ft_result.gr_data_final = gr_data_ledon - gr_data_ledoff;\r
- ft_result.red_data_final = red_data_ledon - red_data_ledoff;\r
- ft_result.ir_data_final = ir_data_ledon - ir_data_ledoff;\r
- if(ft_result.gr_data_final<0)\r
+ ft_result.ldr1_data_final = hx3695_sort_cal_mid(ldr1_buffer);\r
+ hx3695_led_off();\r
+ hx3695_delay_ms(1000);\r
+ DEBUG_PRINTF("ft single,LDR1:%d,\r\n",ft_result.ldr1_data_final );\r
+ \r
+ for(ii=0; ii<TEST_NUM; ii++)\r
{\r
- ft_result.gr_data_final = 0;\r
+ hx3695_delay_ms(20);\r
+ hx3695_LDR2_led_control(1,32); //1=led on;0=led off;ledcur= (led_config*0.8 )ma\r
+ hx3695_delay_ms(40); \r
+ hx3695_factory_test_read(phase_data); \r
+ ldr2_buffer[ii] = phase_data[3] - phase_data[0]; \r
+ DEBUG_PRINTF("LDR2: %d \r\n", ldr2_buffer[ii]); \r
}\r
- if(ft_result.red_data_final<0)\r
+ ft_result.ldr2_data_final = hx3695_sort_cal_mid(ldr2_buffer);\r
+ hx3695_led_off();\r
+ hx3695_delay_ms(1000);\r
+ DEBUG_PRINTF("ft single,LDR2:%d\r\n",ft_result.ldr2_data_final ); \r
+ \r
+ for(ii=0; ii<TEST_NUM; ii++)\r
{\r
- ft_result.red_data_final = 0;\r
+ hx3695_delay_ms(10);\r
+ hx3695_LDR3_led_control(1,32); //1=led on;0=led off;ledcur= (led_config*0.8 )ma \r
+ hx3695_delay_ms(40); \r
+ hx3695_factory_test_read(phase_data); \r
+ \r
+ ldr3_buffer[ii] = phase_data[4] - phase_data[0];\r
+ DEBUG_PRINTF("LDR3: %d \r\n", ldr3_buffer[ii]);\r
}\r
- if(ft_result.ir_data_final<0)\r
+ ft_result.ldr3_data_final = hx3695_sort_cal_mid(ldr3_buffer);\r
+ hx3695_led_off();\r
+ hx3695_delay_ms(1000);\r
+ DEBUG_PRINTF("ft single,LDR3:%d\r\n",ft_result.ldr0_data_final);\r
+ \r
+ for(ii=0; ii<TEST_NUM; ii++)\r
{\r
- ft_result.ir_data_final = 0;\r
+ hx3695_delay_ms(20);\r
+ hx3695_LDR4_led_control(1,32); //1=led on;0=led off;ledcur= (led_config*0.8 )ma\r
+ hx3695_delay_ms(40);\r
+ hx3695_factory_test_read(phase_data); \r
+ ldr4_buffer[ii] = phase_data[5] - phase_data[0];\r
+ DEBUG_PRINTF("LDR4: %d \r\n", ldr4_buffer[ii]);\r
}\r
- //TYHX_LOG("leaking result=%d\r\n",ft_result.gr_data_final );\r
- //hrsresult.leak_green =ft_result.gr_data_final;\r
-\r
-\r
-\r
- return ft_result;\r
-}\r
-\r
-FT_RESULTS_t hx3695_factory_ft_card_test_get_result(void)\r
-{\r
- uint8_t ii = 0;\r
- int32_t phase_data[4] = {0,0,0,0};\r
- int32_t gr_buffer[4] = {0,0,0,0};\r
- int32_t red_buffer[4] = {0,0,0,0};\r
- int32_t ir_buffer[4] = {0,0,0,0};\r
- FT_RESULTS_t ft_result = {0,0,0,0,0,0,0,0,0,0,0,0};\r
-\r
- for(ii=0; ii<4; ii++)\r
+ ft_result.ldr4_data_final = hx3695_sort_cal_mid(ldr4_buffer);\r
+ hx3695_led_off();\r
+ hx3695_delay_ms(1000);\r
+ DEBUG_PRINTF("ft single,LDR4:%d,\r\n",ft_result.ldr4_data_final );\r
+ \r
+ for(ii=0; ii<TEST_NUM; ii++)\r
{\r
+ hx3695_delay_ms(20);\r
+ hx3695_LDR5_led_control(1,32); //1=led on;0=led off;ledcur= (led_config*0.8 )ma\r
hx3695_delay_ms(40);\r
hx3695_factory_test_read(phase_data);\r
- gr_buffer[ii] = phase_data[1] - phase_data[0];\r
- red_buffer[ii] = phase_data[2] - phase_data[0];\r
- ir_buffer[ii] = phase_data[3] - phase_data[0];\r
+ \r
+ ldr5_buffer[ii] = phase_data[6] - phase_data[0]; \r
+ DEBUG_PRINTF("LDR5: %d \r\n", ldr5_buffer[ii]); \r
}\r
- ft_result.gr_data_final = hx3695_sort_cal(gr_buffer);\r
- ft_result.red_data_final = hx3695_sort_cal(red_buffer);\r
- ft_result.ir_data_final = hx3695_sort_cal(ir_buffer);\r
- DEBUG_PRINTF("ft card,g%d,r%d,ir%d\r\n",ft_result.gr_data_final,ft_result.red_data_final,ft_result.ir_data_final );\r
+ ft_result.ldr5_data_final = hx3695_sort_cal_mid(ldr5_buffer);\r
+ hx3695_led_off();\r
+ hx3695_delay_ms(1000);\r
+ DEBUG_PRINTF("ft single,LDR5:%d\r\n",ft_result.ldr5_data_final ); \r
+ \r
+ hx3695_delay_ms(10);\r
\r
- if(gr_buffer[0] == gr_buffer[1] && gr_buffer[0] == gr_buffer[2] && gr_buffer[0] == gr_buffer[3])\r
+ if(ldr0_buffer[0] == ldr0_buffer[1] && ldr0_buffer[0] == ldr0_buffer[2] && ldr0_buffer[0] == ldr0_buffer[3])\r
+ {\r
+ ft_result.ldr0_data_final = 0;\r
+ ft_result.ldr1_data_final = 0;\r
+ ft_result.ldr2_data_final = 0;\r
+ }\r
+ if(ft_result.ldr0_data_final < 0)\r
+ {\r
+ ft_result.ldr0_data_final = 0;\r
+ }\r
+ if(ft_result.ldr1_data_final < 0)\r
{\r
- ft_result.gr_data_final = 0;\r
- ft_result.red_data_final = 0;\r
- ft_result.ir_data_final = 0;\r
+ ft_result.ldr1_data_final = 0;\r
}\r
- if(ft_result.gr_data_final < 0)\r
+ if(ft_result.ldr2_data_final < 0)\r
{\r
- ft_result.gr_data_final = 0;\r
+ ft_result.ldr2_data_final = 0;\r
}\r
- if(ft_result.red_data_final < 0)\r
+ if(ft_result.ldr0_data_final > 0)\r
{\r
- ft_result.red_data_final = 0;\r
+ ft_result.single_gr_led_judge = ft_result.ldr0_data_final*100/ft_result.ldr0_data_final;\r
}\r
- if(ft_result.ir_data_final < 0)\r
+ if(ldr3_buffer[0] == ldr3_buffer[1] && ldr3_buffer[0] == ldr3_buffer[2] && ldr3_buffer[0] == ldr3_buffer[3])\r
{\r
- ft_result.ir_data_final = 0;\r
+ ft_result.ldr3_data_final = 0;\r
+ ft_result.ldr4_data_final = 0;\r
+ ft_result.ldr5_data_final = 0;\r
+ }\r
+ if(ft_result.ldr3_data_final < 0)\r
+ {\r
+ ft_result.ldr3_data_final = 0;\r
+ }\r
+ if(ft_result.ldr4_data_final < 0)\r
+ {\r
+ ft_result.ldr4_data_final = 0;\r
+ }\r
+ if(ft_result.ldr5_data_final < 0)\r
+ {\r
+ ft_result.ldr5_data_final = 0;\r
}\r
\r
return ft_result;\r
}\r
-\r
-FT_RESULTS_t hx3695_factory_ft_single_check_get_result(void)\r
+FT_RESULTS_t hx3695_factory_ft_aging_test_get_result(void)\r
{\r
uint8_t ii = 0;\r
- int32_t phase_data[4] = {0,0,0,0};\r
- int32_t gr_buffer[4] = {0,0,0,0};\r
- int32_t red_buffer[4] = {0,0,0,0};\r
- int32_t ir_buffer[4] = {0,0,0,0};\r
- FT_RESULTS_t ft_result = {0,0,0,0,0,0,0,0,0,0,0,0};\r
-\r
- for(ii=0; ii<4; ii++)\r
+ int32_t phase_data[8] = {0,0,0,0,0,0,0,0};\r
+ int32_t ldr0_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr1_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr2_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr3_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr4_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ int32_t ldr5_buffer[10] = {0,0,0,0,0,0,0,0,0,0};\r
+ \r
+ FT_RESULTS_t ft_result = {0};\r
+\r
+ for(ii=0; ii<TEST_NUM; ii++)\r
{\r
- hx3695_delay_ms(12);\r
+ hx3695_delay_ms(40);\r
hx3695_factory_test_read(phase_data);\r
- gr_buffer[ii] = phase_data[1] - phase_data[0];\r
- red_buffer[ii] = phase_data[2] - phase_data[0];\r
- ir_buffer[ii] = phase_data[3] - phase_data[0];\r
+ for(int j=1;j<(LDR_NUM+1);j++)\r
+ {\r
+ phase_result[ii][j] = phase_data[j];\r
+ DEBUG_PRINTF("%d ", phase_result[ii][j]);\r
+ }\r
+ \r
+ DEBUG_PRINTF("\n");\r
+ \r
+ ldr0_buffer[ii] = phase_data[1] - phase_data[0];\r
+ ldr1_buffer[ii] = phase_data[2] - phase_data[0];\r
+ ldr2_buffer[ii] = phase_data[3] - phase_data[0];\r
+ \r
+ ldr3_buffer[ii] = phase_data[4] - phase_data[0];\r
+ ldr4_buffer[ii] = phase_data[5] - phase_data[0];\r
+ ldr5_buffer[ii] = phase_data[6] - phase_data[0];\r
}\r
- ft_result.gr_data_final = hx3695_sort_cal(gr_buffer);\r
- ft_result.red_data_final = hx3695_sort_cal(red_buffer);\r
- ft_result.ir_data_final = hx3695_sort_cal(ir_buffer);\r
-\r
- hx3695_write_reg(0x33, 0xff);\r
- hx3695_delay_ms(10);\r
+// hx3695_led_off();\r
+ \r
+ ft_result.ldr0_data_final = hx3695_sort_cal(ldr0_buffer);\r
+ ft_result.ldr1_data_final = hx3695_sort_cal(ldr1_buffer);\r
+ ft_result.ldr2_data_final = hx3695_sort_cal(ldr2_buffer);\r
+ \r
+ ft_result.ldr3_data_final = hx3695_sort_cal(ldr3_buffer);\r
+ ft_result.ldr4_data_final = hx3695_sort_cal(ldr4_buffer);\r
+ ft_result.ldr5_data_final = hx3695_sort_cal(ldr5_buffer);\r
+ \r
+ DEBUG_PRINTF("aging,LDR0:%d,LDR1:%d,LDR2:%d,LDR3:%d,LDR4:%d,LDR5 :%d\r\n",ft_result.ldr0_data_final,ft_result.ldr1_data_final,ft_result.ldr2_data_final ,\r
+ ft_result.ldr3_data_final,ft_result.ldr4_data_final,ft_result.ldr5_data_final);\r
+ \r
\r
- for(ii=0; ii<4; ii++)\r
+ if(ldr0_buffer[0] == ldr0_buffer[1] && ldr0_buffer[0] == ldr0_buffer[2] && ldr0_buffer[0] == ldr0_buffer[3])\r
{\r
- hx3695_delay_ms(12);\r
- hx3695_factory_test_read(phase_data);\r
- gr_buffer[ii] = phase_data[1] - phase_data[0];\r
- red_buffer[ii] = phase_data[2] - phase_data[0];\r
- ir_buffer[ii] = phase_data[3] - phase_data[0];\r
+ ft_result.ldr0_data_final = 0;\r
+ ft_result.ldr1_data_final = 0;\r
+ ft_result.ldr2_data_final = 0;\r
}\r
- ft_result.gr_data_high = hx3695_sort_cal(gr_buffer);\r
-\r
- if(gr_buffer[0] == gr_buffer[1] && gr_buffer[0] == gr_buffer[2] && gr_buffer[0] == gr_buffer[3])\r
+ if(ft_result.ldr0_data_final < 0)\r
{\r
- ft_result.gr_data_final = 0;\r
- ft_result.red_data_final = 0;\r
- ft_result.ir_data_final = 0;\r
+ ft_result.ldr0_data_final = 0;\r
}\r
- if(ft_result.gr_data_final < 0)\r
+ if(ft_result.ldr1_data_final < 0)\r
{\r
- ft_result.gr_data_final = 0;\r
+ ft_result.ldr1_data_final = 0;\r
}\r
- if(ft_result.red_data_final < 0)\r
+ if(ft_result.ldr2_data_final < 0)\r
{\r
- ft_result.red_data_final = 0;\r
+ ft_result.ldr2_data_final = 0;\r
}\r
- if(ft_result.ir_data_final < 0)\r
+if(ldr3_buffer[0] == ldr3_buffer[1] && ldr3_buffer[0] == ldr3_buffer[2] && ldr3_buffer[0] == ldr3_buffer[3])\r
{\r
- ft_result.ir_data_final = 0;\r
+ ft_result.ldr3_data_final = 0;\r
+ ft_result.ldr4_data_final = 0;\r
+ ft_result.ldr5_data_final = 0;\r
}\r
- if(ft_result.gr_data_final > 0)\r
+ if(ft_result.ldr3_data_final < 0)\r
{\r
- ft_result.single_gr_led_judge = ft_result.gr_data_high*100/ft_result.gr_data_final;\r
+ ft_result.ldr3_data_final = 0;\r
+ }\r
+ if(ft_result.ldr4_data_final < 0)\r
+ {\r
+ ft_result.ldr4_data_final = 0;\r
+ }\r
+ if(ft_result.ldr5_data_final < 0)\r
+ {\r
+ ft_result.ldr5_data_final = 0;\r
}\r
-\r
return ft_result;\r
}\r
-\r
FT_RESULTS_t hx3695_factroy_test(TEST_MODE_t test_mode)\r
{\r
- FT_RESULTS_t ft_result = {0,0,0,0,0,0,0,0,0,0,0,0};\r
\r
- //if (hx3695_chip_check_id() == false)\r
- {\r
- // return ft_result;\r
- }\r
+ FT_RESULTS_t ft_result = {0};\r
+\r
switch(test_mode)\r
{\r
- case LED_OFF_TEST:\r
- hx3695_factory_led_off_config();\r
- hx3695_delay_ms(50);\r
- ft_result = hx3695_factory_led_off_get_result();\r
- break;\r
- case WEAR_MODE_TEST:\r
- hx3695_factory_wear_mode_config();\r
- hx3695_delay_ms(50);\r
- ft_result = hx3695_factory_wear_mode_get_result();\r
- break;\r
+\r
case LEAK_LIGHT_TEST:\r
+ \r
hx3695_factory_ft_leak_light_test_config();\r
hx3695_delay_ms(50);\r
ft_result = hx3695_factory_ft_leak_light_test_get_result();\r
- factory_green = ft_result.gr_data_final;\r
- factory_red = ft_result.red_data_final;\r
- factory_ir = ft_result.ir_data_final;\r
- printf("factory_green : %d, factory_red:%d, factory_ir:%d\n",factory_green,factory_red,factory_ir);\r
+ // hrsresult.leak_ldr0 = ft_result.ldr0_data_final;\r
+ // hrsresult.leak_ldr1 = ft_result.ldr1_data_final;\r
+ // hrsresult.leak_ldr2 = ft_result.ldr2_data_final;\r
+\r
+ factory_green = ft_result.ldr0_data_final;\r
+ factory_red = ft_result.ldr1_data_final;\r
+ factory_ir = ft_result.ldr2_data_final;\r
+\r
+ // TYHX_LOG("leak LDR0=%d\r\n",hrsresult.leak_ldr0);\r
break;\r
+ \r
case GRAY_CARD_TEST:\r
+ \r
hx3695_factory_ft_card_test_config();\r
hx3695_delay_ms(50);\r
ft_result = hx3695_factory_ft_card_test_get_result();\r
- factory_green = ft_result.gr_data_final;\r
- factory_red = ft_result.red_data_final;\r
- factory_ir = ft_result.ir_data_final;\r
+ // hrsresult.card_ldr0 = ft_result.ldr0_data_final;\r
+ // hrsresult.card_ldr1 = ft_result.ldr1_data_final;\r
+ // hrsresult.card_ldr2 = ft_result.ldr2_data_final;\r
+\r
+ factory_green = ft_result.ldr0_data_final;\r
+ factory_red = ft_result.ldr1_data_final;\r
+ factory_ir = ft_result.ldr2_data_final;\r
break;\r
- case FT_INT_TEST:\r
- hx3695_factory_ft_int_test_config();\r
+ case GNOISE_TEST:\r
+ hx3695_factory_Gnoise_config();\r
+ hx3695_delay_ms(50);\r
+ ft_result = hx3695_factory_Gnoise_result();\r
break;\r
- case SINGLE_CHECK_TEST:\r
+ case SINGLE_CHECK_TEST:\r
hx3695_factory_ft_single_check_config();\r
hx3695_delay_ms(50);\r
ft_result = hx3695_factory_ft_single_check_get_result();\r
break;\r
- default:\r
+ case AGING_CHECK_TEST:\r
+ hx3695_factory_ft_aging_check_config();\r
+ hx3695_delay_ms(50);\r
+ ft_result = hx3695_factory_ft_aging_test_get_result();\r
break;\r
}\r
\r
- //hx3695_ppg_off();\r
- DEBUG_PRINTF("%d %d %d %d %d %d %d %d %d %d %d %d\r\n", ft_result.phase1_data_avg, ft_result.phase2_data_avg, ft_result.phase3_data_avg, ft_result.phase4_data_avg, \\r
- ft_result.gr_ps_dif, ft_result.red_ps_dif, ft_result.ir_ps_dif, ft_result.gr_data_final, ft_result.red_data_final, ft_result.ir_data_final, ft_result.gr_data_high, \\r
- ft_result.single_gr_led_judge);\r
+ //hx3695_ppg_off();\r
+// DEBUG_PRINTF("%d %d %d %d %d %d %d %d %d %d %d %d\r\n", ft_result.phase1_data_avg, ft_result.phase2_data_avg, ft_result.phase3_data_avg, ft_result.phase4_data_avg, \\r
+// ft_result.ldr0_data_final, ft_result.ldr1_data_final, ft_result.ldr2_data_final, ft_result.ldr0_data_final, ft_result.ldr1_data_final, ft_result.ldr2_data_final, ft_result.ldr0_data_final, \\r
+// ft_result.single_gr_led_judge);\r
\r
return ft_result;\r
}\r
-/*\r
- * @Author: penglei 1624952103@qq.com\r
- * @Date: 2025-05-15 11:28:07\r
- * @LastEditors: penglei 1624952103@qq.com\r
- * @LastEditTime: 2025-07-31 17:02:23\r
- * @FilePath: /FD230/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_factory_test.h\r
- * @Description: 这是默认设置,请设置`customMade`, 打开koroFileHeader查看配置 进行设置: https://github.com/OBKoro1/koro1FileHeader/wiki/%E9%85%8D%E7%BD%AE\r
- */\r
#ifndef _HX3695_FACTORY_TEST_H_\r
#define _HX3695_FACTORY_TEST_H_\r
\r
#include <stdint.h>\r
#include <stdbool.h>\r
\r
+\r
+/***********ѡ��*************/\r
+#define LDR0_FT_SEL 0x50 \r
+#define LDR1_FT_SEL 0x28\r
+#define LDR2_FT_SEL 0x81\r
+#define LDR3_FT_SEL 0x81\r
+#define LDR4_FT_SEL 0x40\r
+#define LDR5_FT_SEL 0x80\r
+\r
+/***********ѡPD*************/\r
+#define LDR0_PD_FT_SEL 0x06\r
+#define LDR1_PD_FT_SEL 0x06\r
+#define LDR2_PD_FT_SEL 0x06\r
+#define LDR3_PD_FT_SEL 0x06\r
+#define LDR4_PD_FT_SEL 0x0f\r
+#define LDR5_PD_FT_SEL 0x0f\r
+#define ALS_PD_FT_SEL 0x0f\r
+\r
+/***********���õ���*************/\r
+\r
+#define DRV1_LEAK_CUR 64 //Ĭ������ led driver 1 ����50MA��driver2�����õ���\r
+#define DRV2_LEAK_CUR 0\r
+\r
+#define DRV1_GRAD_CUR 32 //Ĭ������ led driver 1 ����25MA��driver2�����õ���\r
+#define DRV2_GRAD_CUR 0\r
+\r
+#define DRV1_AGING_CUR 128 //Ĭ������ led driver 1 ����100MA��driver2����100MA���� �ϼ�200mA\r
+#define DRV2_AGING_CUR 128\r
+\r
+#define DRV1_SINGLE_CUR 64 //Ĭ������ led driver 1 ����50MA��driver2�����õ���\r
+#define DRV2_SINGLE_CUR 0\r
+\r
+/***********��������TIA*************/\r
+\r
+#define PS_LEAK_TIA 5\r
+\r
+#define PS_GRAD_TIA 1\r
+\r
+#define PS_AGING_TIA 5\r
+\r
+#define PS_SINGLE_TIA 3\r
+\r
+#define PS_Gnoise_TIA 3\r
+\r
+#define TEST_NUM 6 //���Դ��� \r
+#define LDR_NUM 3 //LDR����������ldr˳��\r
typedef enum {\r
LEAK_LIGHT_TEST = 1,\r
GRAY_CARD_TEST = 2,\r
- FT_INT_TEST = 3,\r
- SINGLE_CHECK_TEST = 4,\r
- LED_OFF_TEST = 5,\r
- WEAR_MODE_TEST = 6\r
+ GNOISE_TEST=3,\r
+ SINGLE_CHECK_TEST=4,\r
+ AGING_CHECK_TEST=5\r
} TEST_MODE_t;\r
\r
typedef struct { \r
int32_t phase2_data_avg;\r
int32_t phase3_data_avg;\r
int32_t phase4_data_avg;\r
- int32_t gr_ps_dif;\r
- int32_t red_ps_dif;\r
- int32_t ir_ps_dif;\r
- int32_t gr_data_final;\r
- int32_t red_data_final;\r
- int32_t ir_data_final;\r
- int32_t gr_data_high;\r
+ int32_t phase5_data_avg;\r
+ int32_t phase6_data_avg;\r
+ int32_t phase7_data_avg;\r
+ int32_t phase8_data_avg;\r
+ int32_t ldr0_ps_dif;\r
+ int32_t ldr1_ps_dif;\r
+ int32_t ldr2_ps_dif;\r
+ int32_t ldr0_data_final;\r
+ int32_t ldr1_data_final;\r
+ int32_t ldr2_data_final;\r
+ int32_t ldr0_data_high;\r
+ int32_t ldr3_ps_dif;\r
+ int32_t ldr4_ps_dif;\r
+ int32_t ldr5_ps_dif;\r
+ int32_t ldr3_data_final;\r
+ int32_t ldr4_data_final;\r
+ int32_t ldr5_data_final;\r
+ int32_t ldr3_data_high;\r
int32_t single_gr_led_judge;\r
} FT_RESULTS_t;\r
\r
void hx3695_factory_ft_leak_light_test_config(void);\r
void hx3695_factory_ft_card_test_config(void);\r
void hx3695_factory_ft_int_test_config(void);\r
+void hx3695_factory_new_config_init(void) ;\r
\r
bool hx3695_factory_test_read(int32_t *phase_data);\r
FT_RESULTS_t hx3695_factroy_test(TEST_MODE_t test_mode);\r
}\r
}\r
\r
-SENSOR_ERROR_T hx3695_hrs_enable(void)\r
-{\r
- if (!hx3695_chip_check())\r
- {\r
- AGC_LOG("hx3695 check id failed!\r\n");\r
- return SENSOR_OP_FAILED;\r
- }\r
+// SENSOR_ERROR_T hx3695_hrs_enable(void)\r
+// {\r
+// if (!hx3695_chip_check())\r
+// {\r
+// AGC_LOG("hx3695 check id failed!\r\n");\r
+// return SENSOR_OP_FAILED;\r
+// }\r
\r
- AGC_LOG("hx3695 check id success!\r\n");\r
+// AGC_LOG("hx3695 check id success!\r\n");\r
\r
- if (s_ppg_state)\r
- {\r
- AGC_LOG("ppg already on!\r\n");\r
- return SENSOR_OP_FAILED;\r
- }\r
- if(!tyhx_hrs_alg_open())\r
- {\r
- AGC_LOG("hrs alg open fail,or dynamic ram not enough!\r\n");\r
- }\r
+// if (s_ppg_state)\r
+// {\r
+// AGC_LOG("ppg already on!\r\n");\r
+// return SENSOR_OP_FAILED;\r
+// }\r
+// if(!tyhx_hrs_alg_open())\r
+// {\r
+// AGC_LOG("hrs alg open fail,or dynamic ram not enough!\r\n");\r
+// }\r
\r
- hrs_wear_status = MSG_HRS_NO_WEAR;\r
- hrs_wear_status_pre = MSG_HRS_NO_WEAR;\r
+// hrs_wear_status = MSG_HRS_NO_WEAR;\r
+// hrs_wear_status_pre = MSG_HRS_NO_WEAR;\r
\r
- hx3695_hrs_set_mode(PPG_INIT);\r
+// hx3695_hrs_set_mode(PPG_INIT);\r
\r
- AGC_LOG("hx3695 enable!\r\n");\r
+// AGC_LOG("hx3695 enable!\r\n");\r
\r
- return SENSOR_OK;\r
-}\r
+// return SENSOR_OK;\r
+// }\r
\r
void hx3695_hrs_disable(void)\r
{\r
return cal;\r
}\r
\r
-uint8_t hx3695_hrs_read(hrs_sensor_data_t * s_dat)\r
-{\r
- int32_t PPG_src_data, PPG_src_data2;\r
- int32_t Ir_src_data;\r
- bool recal = false;\r
- uint8_t size = 0;\r
- uint8_t data_count = 0;\r
- uint8_t size_byte = 0;\r
- int32_t *PPG_buf = &(s_dat->green_data[0]);\r
- int32_t *ir_buf = &(s_dat->ir_data[0]); \r
- int32_t *s_buf = &(s_dat->s_buf[0]); \r
+// uint8_t hx3695_hrs_read(hrs_sensor_data_t * s_dat)\r
+// {\r
+// int32_t PPG_src_data, PPG_src_data2;\r
+// int32_t Ir_src_data;\r
+// bool recal = false;\r
+// uint8_t size = 0;\r
+// uint8_t data_count = 0;\r
+// uint8_t size_byte = 0;\r
+// int32_t *PPG_buf = &(s_dat->green_data[0]);\r
+// int32_t *ir_buf = &(s_dat->ir_data[0]); \r
+// int32_t *s_buf = &(s_dat->s_buf[0]); \r
\r
- int32_t ps_data[8] = {0};\r
- int32_t ps_green_data = 0;\r
- s_dat->agc_green = calReg_Hrs.Group1_Cur;\r
-\r
- if (!s_ppg_state || hrs_cal_state) \r
- {\r
-// TYHX_LOG("ppg_state: %d ,hrs_cal_state: %d\r\n",s_ppg_state,hrs_cal_state);\r
- return 0;\r
- } \r
-// TYHX_LOG("ppg_state: %d ,hrs_cal_state: %d\r\n",s_ppg_state,hrs_cal_state); \r
- data_count = hx3695_read_fifo_data(s_buf,hrs_phase_num,1); \r
-\r
- if(data_count > 9)\r
- return 0;\r
-\r
- // PRINT("ppg data size: %d %d\r\n", data_count,hrs_phase_num);\r
-// SEGGER_RTT_printf(0,"af_hx3695_read_fifo_data:::%d %d %d\r\n", hx3695_read_reg(0X2a),hx3695_read_reg(0X2b),hx3695_read_reg(0X2c));\r
- s_dat->count = data_count; \r
-\r
- read_hrs_data_packet(ps_data);\r
- for (uint8_t i=0; i<data_count; i++) \r
- {\r
-// PPG_src_data = ps_data[1] - ps_data[0]; // s_buf[i*3];\r
- Ir_src_data = ps_data[7] - ps_data[6]; //s_buf[i*3+2]; \r
- PPG_src_data = s_buf[i*3];\r
- PPG_src_data2 = s_buf[i*3+1];\r
-// Ir_src_data = s_buf[i*4+3]; \r
-\r
- PPG_buf[i] = PPG_src_data * 2;\r
- ir_buf[i] = Ir_src_data; //Ir_src_data;\r
-// SEGGER_RTT_printf(0,"PPG_data: %d , PPG_src_data2: %d\r\n", PPG_src_data,PPG_src_data2);\r
- // PRINT("hx3695 Ir_src_data %d \r\n", Ir_src_data);\r
- hx3695_hrs_wear_mode_check(HRS_MODE,Ir_src_data); \r
-\r
- }\r
- ps_green_data = ps_data[1]; // - ((ps_data[2]+ps_data[0])>>1);\r
-// SEGGER_RTT_printf(0,"ps_green_data: %d PS8: %d, PS7: %d\r\n", ps_green_data,ps_data[7],ps_data[6]);\r
- if (ps_green_data<300000 || ps_green_data>800000) \r
- {\r
- recal = true;\r
+// int32_t ps_data[8] = {0};\r
+// int32_t ps_green_data = 0;\r
+// s_dat->agc_green = calReg_Hrs.Group1_Cur;\r
+\r
+// if (!s_ppg_state || hrs_cal_state) \r
+// {\r
+// // TYHX_LOG("ppg_state: %d ,hrs_cal_state: %d\r\n",s_ppg_state,hrs_cal_state);\r
+// return 0;\r
+// } \r
+// // TYHX_LOG("ppg_state: %d ,hrs_cal_state: %d\r\n",s_ppg_state,hrs_cal_state); \r
+// data_count = hx3695_read_fifo_data(s_buf,hrs_phase_num,1); \r
+\r
+// if(data_count > 9)\r
+// return 0;\r
+\r
+// // PRINT("ppg data size: %d %d\r\n", data_count,hrs_phase_num);\r
+// // SEGGER_RTT_printf(0,"af_hx3695_read_fifo_data:::%d %d %d\r\n", hx3695_read_reg(0X2a),hx3695_read_reg(0X2b),hx3695_read_reg(0X2c));\r
+// s_dat->count = data_count; \r
+\r
+// read_hrs_data_packet(ps_data);\r
+// for (uint8_t i=0; i<data_count; i++) \r
+// {\r
+// // PPG_src_data = ps_data[1] - ps_data[0]; // s_buf[i*3];\r
+// Ir_src_data = ps_data[7] - ps_data[6]; //s_buf[i*3+2]; \r
+// PPG_src_data = s_buf[i*3];\r
+// PPG_src_data2 = s_buf[i*3+1];\r
+// // Ir_src_data = s_buf[i*4+3]; \r
+\r
+// PPG_buf[i] = PPG_src_data * 2;\r
+// ir_buf[i] = Ir_src_data; //Ir_src_data;\r
+// // SEGGER_RTT_printf(0,"PPG_data: %d , PPG_src_data2: %d\r\n", PPG_src_data,PPG_src_data2);\r
+// // PRINT("hx3695 Ir_src_data %d \r\n", Ir_src_data);\r
+// hx3695_hrs_wear_mode_check(HRS_MODE,Ir_src_data); \r
+\r
+// }\r
+// ps_green_data = ps_data[1]; // - ((ps_data[2]+ps_data[0])>>1);\r
+// // SEGGER_RTT_printf(0,"ps_green_data: %d PS8: %d, PS7: %d\r\n", ps_green_data,ps_data[7],ps_data[6]);\r
+// if (ps_green_data<300000 || ps_green_data>800000) \r
+// {\r
+// recal = true;\r
\r
- if(hrs_wear_status==MSG_HRS_NO_WEAR)\r
- {\r
- recal = false;\r
- } \r
- }\r
- if (recal) \r
- //if (0)\r
- {\r
- cal_delay--;\r
-\r
- if (cal_delay <= 0) \r
- {\r
- cal_delay = CAL_DELAY_COUNT;\r
- hx3695_hrs_set_mode(RECAL_INIT);\r
- AGC_LOG("========>>>>LED_IDAC = %d %d %d\r\n",calReg_Hrs.Group1_Ledidac,calReg_Hrs.Group2_Ledidac,calReg_Hrs.Group3_Ledidac);\r
- }\r
- }\r
- else \r
- {\r
- cal_delay = CAL_DELAY_COUNT;\r
- }\r
-// } \r
- return 1;\r
-}\r
+// if(hrs_wear_status==MSG_HRS_NO_WEAR)\r
+// {\r
+// recal = false;\r
+// } \r
+// }\r
+// if (recal) \r
+// //if (0)\r
+// {\r
+// cal_delay--;\r
+\r
+// if (cal_delay <= 0) \r
+// {\r
+// cal_delay = CAL_DELAY_COUNT;\r
+// hx3695_hrs_set_mode(RECAL_INIT);\r
+// AGC_LOG("========>>>>LED_IDAC = %d %d %d\r\n",calReg_Hrs.Group1_Ledidac,calReg_Hrs.Group2_Ledidac,calReg_Hrs.Group3_Ledidac);\r
+// }\r
+// }\r
+// else \r
+// {\r
+// cal_delay = CAL_DELAY_COUNT;\r
+// }\r
+// // } \r
+// return 1;\r
+// }\r
\r
\r
#endif\r
void hx3695_hrs_normal_power(void);\r
void hx3695_hrs_updata_reg(void);\r
void hx3695_hrs_set_mode(uint8_t mode_cmd);\r
-SENSOR_ERROR_T hx3695_hrs_enable(void);\r
+// SENSOR_ERROR_T hx3695_hrs_enable(void);\r
void hx3695_hrs_disable(void);\r
hrs_wear_msg_code_t hx3695_hrs_get_wear_status(void);\r
-uint8_t hx3695_hrs_read(hrs_sensor_data_t *s_dat);\r
+// uint8_t hx3695_hrs_read(hrs_sensor_data_t *s_dat);\r
bool hx3695_hrs_init(void); \r
hrs_wear_msg_code_t hx3695_hrs_wear_mode_check(WORK_MODE_T mode, int32_t infrared_data);\r
\r
+/*\r
+ * @Author: penglei 1624952103@qq.com\r
+ * @Date: 2025-05-15 11:28:07\r
+ * @LastEditors: penglei 1624952103@qq.com\r
+ * @LastEditTime: 2025-10-25 10:14:36\r
+ * @FilePath: /FD230/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrv_agc.c\r
+ * @Description: 这是默认设置,请设置`customMade`, 打开koroFileHeader查看配置 进行设置: https://github.com/OBKoro1/koro1FileHeader/wiki/%E9%85%8D%E7%BD%AE\r
+ */\r
#include <stdio.h>\r
#include <stdbool.h>\r
#include <stdint.h>\r
}\r
}\r
\r
-SENSOR_ERROR_T hx3695_hrv_enable(void)\r
-{\r
- if (!hx3695_chip_check())\r
- {\r
- AGC_LOG("hx3695 check id failed!\r\n");\r
- return SENSOR_OP_FAILED;\r
- }\r
+// SENSOR_ERROR_T hx3695_hrv_enable(void)\r
+// {\r
+// if (!hx3695_chip_check())\r
+// {\r
+// AGC_LOG("hx3695 check id failed!\r\n");\r
+// return SENSOR_OP_FAILED;\r
+// }\r
\r
- AGC_LOG("hx3695 check id success!\r\n");\r
+// AGC_LOG("hx3695 check id success!\r\n");\r
\r
- if (s_ppg_state)\r
- {\r
- AGC_LOG("ppg already on!\r\n");\r
- return SENSOR_OP_FAILED;\r
- }\r
- if(!tyhx_hrv_alg_open())\r
- {\r
- AGC_LOG("hrv alg open fail,or dynamic ram not enough!\r\n");\r
- }\r
+// if (s_ppg_state)\r
+// {\r
+// AGC_LOG("ppg already on!\r\n");\r
+// return SENSOR_OP_FAILED;\r
+// }\r
+// if(!tyhx_hrv_alg_open())\r
+// {\r
+// AGC_LOG("hrv alg open fail,or dynamic ram not enough!\r\n");\r
+// }\r
\r
- hrv_wear_status = MSG_HRV_NO_WEAR;\r
- hrv_wear_status_pre = MSG_HRV_NO_WEAR;\r
+// hrv_wear_status = MSG_HRV_NO_WEAR;\r
+// hrv_wear_status_pre = MSG_HRV_NO_WEAR;\r
\r
- hx3695_hrv_set_mode(PPG_INIT);\r
+// hx3695_hrv_set_mode(PPG_INIT);\r
\r
- AGC_LOG("hx3695 enable!\r\n");\r
+// AGC_LOG("hx3695 enable!\r\n");\r
\r
- return SENSOR_OK;\r
-}\r
+// printf("hx3695_hrv_enable!!!\n");\r
+\r
+// return SENSOR_OK;\r
+// }\r
\r
\r
void hx3695_hrv_disable(void)\r
// }\r
//}\r
\r
-uint8_t hx3695_hrv_read(hrv_sensor_data_t *s_dat)\r
-{\r
- uint8_t i = 0;\r
- int32_t PPG_src_data = 0;\r
- int32_t Ir_src_data = 0;\r
- bool recal = false;\r
- uint8_t size = 0;\r
- uint8_t fifo_out_size = 0;\r
- int32_t *PPG_buf = &(s_dat->green_data[0]);\r
- int32_t *ir_buf = &(s_dat->ir_data[0]);\r
- int32_t *s_buf = &(s_dat->s_buf[0]);\r
- s_dat->green_cur = calReg.LED;\r
- int32_t ps_data[4];\r
-\r
- if (!s_ppg_state || s_cal_state)\r
- {\r
- DEBUG_PRINTF("ppg state = %d, cal_state = %d\r\n",s_ppg_state,s_cal_state);\r
- return 0;\r
- }\r
-// size = hx3695_read_fifo_size();\r
-// DEBUG_PRINTF("size = %d\r\n",size);\r
-\r
-// if(size<1)\r
-// {\r
-// return 0;\r
-// }\r
-\r
- hx3695_hrv_read_data_packet(ps_data);\r
- Ir_src_data = ps_data[2]-ps_data[3];\r
- DEBUG_PRINTF("%d %d \r\n" ,ps_data[2],ps_data[3]);\r
- ir_buf[0] = Ir_src_data;\r
- //DEBUG_PRINTF("111: %d \r\n" ,ir_buf[0] );\r
- hx3695_hrv_wear_mode_check(Ir_src_data);\r
-\r
-// if ((size) && (size <= 64))\r
-// {\r
- fifo_out_size = hx3695_read_fifo_data(s_buf,hrv_phase_num,1);\r
- s_dat->count = fifo_out_size;\r
- for (i=0; i<fifo_out_size; i++)\r
- {\r
- PPG_src_data = s_buf[i];\r
- if (s_buf[i]<350000 || s_buf[i]>750000)\r
- {\r
- recal = true;\r
-\r
- if(hrv_wear_status==MSG_HRV_NO_WEAR)\r
- {\r
- recal = false;\r
- }\r
- }\r
- PPG_buf[i] = PPG_src_data;\r
- //AGC_LOG("%d/%d %d %d %d\r\n" ,1+i,size, s_buf[i],calReg.LED,recal);\r
- }\r
-\r
- if (recal)\r
- {\r
- cal_delay--;\r
- if (cal_delay <= 0)\r
- {\r
- cal_delay = HRV_CAL_DELAY_COUNT;\r
- hx3695_hrv_set_mode(RECAL_INIT);\r
- }\r
- }\r
- else\r
- {\r
- cal_delay = HRV_CAL_DELAY_COUNT;\r
- }\r
-// }\r
- return 1;\r
-}\r
+// uint8_t hx3695_hrv_read(hrv_sensor_data_t *s_dat)\r
+// {\r
+// uint8_t i = 0;\r
+// int32_t PPG_src_data = 0;\r
+// int32_t Ir_src_data = 0;\r
+// bool recal = false;\r
+// uint8_t size = 0;\r
+// uint8_t fifo_out_size = 0;\r
+// int32_t *PPG_buf = &(s_dat->green_data[0]);\r
+// int32_t *ir_buf = &(s_dat->ir_data[0]);\r
+// int32_t *s_buf = &(s_dat->s_buf[0]);\r
+// s_dat->green_cur = calReg.LED;\r
+// int32_t ps_data[4];\r
+\r
+// if (!s_ppg_state || s_cal_state)\r
+// {\r
+// DEBUG_PRINTF("ppg state = %d, cal_state = %d\r\n",s_ppg_state,s_cal_state);\r
+// return 0;\r
+// }\r
+// // size = hx3695_read_fifo_size();\r
+// // DEBUG_PRINTF("size = %d\r\n",size);\r
+\r
+// // if(size<1)\r
+// // {\r
+// // return 0;\r
+// // }\r
+\r
+// hx3695_hrv_read_data_packet(ps_data);\r
+// Ir_src_data = ps_data[2]-ps_data[3];\r
+// DEBUG_PRINTF("%d %d \r\n" ,ps_data[2],ps_data[3]);\r
+// ir_buf[0] = Ir_src_data;\r
+// DEBUG_PRINTF("111: %d \r\n" ,ir_buf[0] );\r
+// hx3695_hrv_wear_mode_check(Ir_src_data);\r
+\r
+// // if ((size) && (size <= 64))\r
+// // {\r
+// fifo_out_size = hx3695_read_fifo_data(s_buf,hrv_phase_num,1);\r
+// s_dat->count = fifo_out_size;\r
+// for (i=0; i<fifo_out_size; i++)\r
+// {\r
+// PPG_src_data = s_buf[i];\r
+// if (s_buf[i]<350000 || s_buf[i]>750000)\r
+// {\r
+// recal = true;\r
+\r
+// if(hrv_wear_status==MSG_HRV_NO_WEAR)\r
+// {\r
+// recal = false;\r
+// }\r
+// }\r
+// PPG_buf[i] = PPG_src_data;\r
+// AGC_LOG("%d/%d %d %d %d\r\n" ,1+i,size, s_buf[i],calReg.LED,recal);\r
+// }\r
+\r
+// if (recal)\r
+// {\r
+// cal_delay--;\r
+// if (cal_delay <= 0)\r
+// {\r
+// cal_delay = HRV_CAL_DELAY_COUNT;\r
+// hx3695_hrv_set_mode(RECAL_INIT);\r
+// }\r
+// }\r
+// else\r
+// {\r
+// cal_delay = HRV_CAL_DELAY_COUNT;\r
+// }\r
+// // }\r
+// return 1;\r
+// }\r
\r
#endif\r
+/*\r
+ * @Author: penglei 1624952103@qq.com\r
+ * @Date: 2025-05-15 11:28:07\r
+ * @LastEditors: penglei 1624952103@qq.com\r
+ * @LastEditTime: 2025-10-25 10:13:59\r
+ * @FilePath: /FD230/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrv_agc.h\r
+ * @Description: 这是默认设置,请设置`customMade`, 打开koroFileHeader查看配置 进行设置: https://github.com/OBKoro1/koro1FileHeader/wiki/%E9%85%8D%E7%BD%AE\r
+ */\r
#ifndef _hx3695_hrv_agc_H_\r
#define _hx3695_hrv_agc_H_\r
//#endif\r
void hx3695_hrv_low_power(void);\r
void hx3695_hrv_updata_reg(void);\r
void hx3695_hrv_set_mode(uint8_t mode_cmd);\r
-SENSOR_ERROR_T hx3695_hrv_enable(void);\r
+// SENSOR_ERROR_T hx3695_hrv_enable(void);\r
void hx3695_hrv_disable(void);\r
hrv_wear_msg_code_t hx3695_hrv_get_wear_status(void);\r
-uint8_t hx3695_hrv_read(hrv_sensor_data_t * s_dat);\r
+// uint8_t hx3695_hrv_read(hrv_sensor_data_t * s_dat);\r
bool hx3695_hrv_init(void);\r
HRV_CAL_SET_T PPG_hrv_agc(void);\r
hrv_wear_msg_code_t hx3695_hrv_wear_mode_check(int32_t infrared_data);\r
}\r
}\r
\r
-SENSOR_ERROR_T hx3695_spo2_enable(void)\r
-{\r
- if (!hx3695_chip_check())\r
- {\r
- AGC_LOG("hx3695 check id failed!\r\n");\r
- return SENSOR_OP_FAILED;\r
- }\r
-\r
- AGC_LOG("hx3695 check id success!\r\n");\r
-\r
- if (s_ppg_state)\r
- {\r
- AGC_LOG("ppg already on!\r\n");\r
- return SENSOR_OP_FAILED;\r
- }\r
-\r
- if(!tyhx_spo2_alg_open())\r
- {\r
- AGC_LOG("spo2 alg open fail,or dynamic ram not enough!\r\n");\r
- return SENSOR_OP_FAILED;\r
- }\r
- spo2_wear_status = MSG_SPO2_NO_WEAR;\r
- spo2_wear_status_pre = MSG_SPO2_NO_WEAR;\r
- hx3695_spo2_set_mode(PPG_INIT);\r
-\r
- AGC_LOG("hx3695 enable!\r\n");\r
-\r
- return SENSOR_OK;\r
-}\r
-\r
-SENSOR_ERROR_T hx3695_hrspo2_enable(void)\r
-{\r
- if (!hx3695_chip_check())\r
- {\r
- AGC_LOG("hx3695 check id failed!\r\n");\r
- return SENSOR_OP_FAILED;\r
- }\r
-\r
- AGC_LOG("hx3695 check id success!\r\n");\r
-\r
- if (s_ppg_state)\r
- {\r
- AGC_LOG("ppg already on!\r\n");\r
- return SENSOR_OP_FAILED;\r
- }\r
-\r
- if(!tyhx_spo2_alg_open())\r
- {\r
- AGC_LOG("spo2 alg open fail,or dynamic ram not enough!\r\n");\r
- return SENSOR_OP_FAILED;\r
- }\r
- if(!tyhx_hrs_alg_open())\r
- {\r
- AGC_LOG("spo2 alg open fail,or dynamic ram not enough!\r\n");\r
- return SENSOR_OP_FAILED;\r
- }\r
- spo2_wear_status = MSG_SPO2_NO_WEAR;\r
- spo2_wear_status_pre = MSG_SPO2_NO_WEAR;\r
- hx3695_spo2_set_mode(PPG_INIT);\r
-\r
- AGC_LOG("hx3695 enable!\r\n");\r
-\r
- return SENSOR_OK;\r
-}\r
+// SENSOR_ERROR_T hx3695_spo2_enable(void)\r
+// {\r
+// if (!hx3695_chip_check())\r
+// {\r
+// AGC_LOG("hx3695 check id failed!\r\n");\r
+// return SENSOR_OP_FAILED;\r
+// }\r
+\r
+// AGC_LOG("hx3695 check id success!\r\n");\r
+\r
+// if (s_ppg_state)\r
+// {\r
+// AGC_LOG("ppg already on!\r\n");\r
+// return SENSOR_OP_FAILED;\r
+// }\r
+\r
+// if(!tyhx_spo2_alg_open())\r
+// {\r
+// AGC_LOG("spo2 alg open fail,or dynamic ram not enough!\r\n");\r
+// return SENSOR_OP_FAILED;\r
+// }\r
+// spo2_wear_status = MSG_SPO2_NO_WEAR;\r
+// spo2_wear_status_pre = MSG_SPO2_NO_WEAR;\r
+// hx3695_spo2_set_mode(PPG_INIT);\r
+\r
+// AGC_LOG("hx3695 enable!\r\n");\r
+\r
+// return SENSOR_OK;\r
+// }\r
+\r
+// SENSOR_ERROR_T hx3695_hrspo2_enable(void)\r
+// {\r
+// if (!hx3695_chip_check())\r
+// {\r
+// AGC_LOG("hx3695 check id failed!\r\n");\r
+// return SENSOR_OP_FAILED;\r
+// }\r
+\r
+// AGC_LOG("hx3695 check id success!\r\n");\r
+\r
+// if (s_ppg_state)\r
+// {\r
+// AGC_LOG("ppg already on!\r\n");\r
+// return SENSOR_OP_FAILED;\r
+// }\r
+\r
+// if(!tyhx_spo2_alg_open())\r
+// {\r
+// AGC_LOG("spo2 alg open fail,or dynamic ram not enough!\r\n");\r
+// return SENSOR_OP_FAILED;\r
+// }\r
+// if(!tyhx_hrs_alg_open())\r
+// {\r
+// AGC_LOG("spo2 alg open fail,or dynamic ram not enough!\r\n");\r
+// return SENSOR_OP_FAILED;\r
+// }\r
+// spo2_wear_status = MSG_SPO2_NO_WEAR;\r
+// spo2_wear_status_pre = MSG_SPO2_NO_WEAR;\r
+// hx3695_spo2_set_mode(PPG_INIT);\r
+\r
+// AGC_LOG("hx3695 enable!\r\n");\r
+\r
+// return SENSOR_OK;\r
+// }\r
\r
void hx3695_spo2_disable(void)\r
{\r
void hx3695_spo2_normal_power(void); \r
void hx3695_spo2_updata_reg(void);\r
void hx3695_spo2_set_mode(uint8_t mode_cmd);\r
-SENSOR_ERROR_T hx3695_spo2_enable(void);\r
+// SENSOR_ERROR_T hx3695_spo2_enable(void);\r
void hx3695_spo2_disable(void);\r
spo2_wear_msg_code_t hx3695_spo2_get_wear_status(void);\r
uint8_t hx3695_spo2_read(spo2_sensor_data_t * s_dat);\r
-//vesion3.1.35\r
+//vesion3.1.53\r
#ifndef _TYHX_HRS_ALG_H_\r
#define _TYHX_HRS_ALG_H_\r
\r
#include <stdint.h>\r
-#if 0\r
-/* portable 8-bit unsigned integer */\r
-typedef unsigned char uint8_t;\r
-/* portable 8-bit signed integer */\r
-typedef signed char int8_t;\r
-/* portable 16-bit unsigned integer */\r
-typedef unsigned short int uint16_t;\r
-/* portable 16-bit signed integer */\r
-typedef signed short int int16_t;\r
-/* portable 32-bit unsigned integer */\r
-typedef unsigned int uint32_t;\r
-/* portable 32-bit signed integer */\r
-typedef signed int int32_t;\r
-#endif\r
+\r
+// /* portable 8-bit unsigned integer */\r
+// typedef unsigned char uint8_t;\r
+// /* portable 8-bit signed integer */\r
+// typedef signed char int8_t;\r
+// /* portable 16-bit unsigned integer */\r
+// typedef unsigned short int uint16_t;\r
+// /* portable 16-bit signed integer */\r
+// typedef signed short int int16_t;\r
+// /* portable 32-bit unsigned integer */\r
+// //typedef unsigned int uint32_t;\r
+// /* portable 32-bit signed integer */\r
+// //typedef signed int int32_t;\r
+\r
#ifndef bool\r
#define bool unsigned char\r
#endif\r
#define false 0\r
#endif\r
\r
-#ifdef HRS_ALG_LIB\r
+\r
+///////////////////////// config ///////////////////////////\r
+#define BP_CUSTDOWN_ALG_LIB\r
+#define SHARED_RAM\r
+#define NO_MATH_LIB\r
+\r
+//define DEBUG_DATA\r
+//////////////////////////////////////////////////////////////\r
+\r
+\r
+// #ifdef DEBUG_DATA\r
+// #define DEBUG_PRINTF(...) SEGGER_RTT_printf(0,__VA_ARGS__)\r
+// #else\r
+// #define DEBUG_PRINTF(...)\r
+// #endif\r
+\r
+#ifdef SHARED_RAM\r
+extern uint8_t alg_ram[11 * 1024] __attribute__((aligned(4)));\r
+#endif\r
\r
typedef enum {\r
NORMAL_MODE,\r
WALK_MODE,\r
JUMP_MODE,\r
ALLDAY_HR_MODE,\r
- HIGH_POW_MODE\r
+ HIGH_POW_MODE,\r
+ CLICK_MODE\r
} hrs_sports_mode_t;\r
\r
typedef enum {\r
uint16_t cal_result;\r
uint8_t hr_result_qual;\r
uint32_t hr_result_std;\r
+ hrs_sports_mode_t hr_mode;\r
+ uint8_t stress;\r
+ uint8_t breath;\r
+ uint32_t rri;\r
+ uint32_t rri_num;\r
+ uint32_t rri_std;\r
+ uint32_t rmssd;\r
} hrs_results_t;\r
\r
#ifdef BP_CUSTDOWN_ALG_LIB\r
typedef struct {\r
bp_msg_code_t bp_alg_status;\r
uint8_t sbp;\r
- uint8_t dbp; \r
+ uint8_t dbp;\r
uint32_t data_cnt;\r
uint8_t hr_result;\r
bool object_flg;\r
hrs_results_t tyhx_hrs_alg_get_results(void);\r
void tyhx_hrs_set_alg_para(hrs_sports_mode_t sports_mode, uint16_t static_thre_val, uint8_t gsen_fun_lv_val);\r
void tyhx_hrs_set_living(uint8_t mode, uint8_t qu_thre, uint8_t st_thre);\r
-#endif //HRS_ALG_LIB\r
\r
#endif\r
\r
* @Author: penglei 1624952103@qq.com
* @Date: 2024-03-26 20:29:58
* @LastEditors: penglei 1624952103@qq.com
- * @LastEditTime: 2024-11-18 17:32:40
+ * @LastEditTime: 2025-10-22 17:41:15
* @FilePath: /FD230/code/sdk/drivers/peripheral/ppg/hx3695/tyhx_hrs_custom.h
* @Description:
*
} FT_CUSTOM_RESULTS_t;
extern FT_CUSTOM_RESULTS_t hrsresult;
-//#define TYHX_DEBUG
+
+#define TYHX_DEBUG
#ifdef TYHX_DEBUG
#define TYHX_LOG(fmt, ...) \
+//tyhx_hrv_v1.0.3\r
+\r
#ifndef _TYHX_HRV_ALG_H_\r
#define _TYHX_HRV_ALG_H_\r
-#endif\r
\r
#include <stdint.h>\r
+\r
#if 0\r
/* portable 8-bit unsigned integer */\r
typedef unsigned char uint8_t;\r
typedef unsigned int uint32_t;\r
/* portable 32-bit signed integer */\r
typedef signed int int32_t;\r
-#endif\r
+\r
#ifndef bool\r
#define bool unsigned char\r
#endif\r
#ifndef false\r
#define false 0\r
#endif\r
+#endif\r
+\r
\r
#define HRV_GLITCH_THRES 20000 \r
#define HRV_GSEN_POW_THRE 150\r
\r
-#ifdef HRV_ALG_LIB\r
+///////////////////////// config ///////////////////////////\r
+#define SHARED_RAM\r
+//define DEBUG_DATA\r
+//////////////////////////////////////////////////////////////\r
+\r
+\r
+// #ifdef DEBUG_DATA\r
+// #define DEBUG_PRINTF(...) SEGGER_RTT_printf(0,__VA_ARGS__)\r
+// #else\r
+// #define DEBUG_PRINTF(...)\r
+// #endif\r
+\r
+#ifdef SHARED_RAM\r
+extern uint8_t alg_ram[11 * 1024] __attribute__((aligned(4)));\r
+#endif\r
\r
typedef enum {\r
MSG_HRV_ALG_NOT_OPEN,\r
typedef struct {\r
hrv_alg_msg_code_t hrv_alg_status;\r
uint32_t data_cnt;\r
- uint8_t hrv_result;\r
+ uint32_t hrv_result;\r
+ uint32_t hr;\r
uint32_t hrv_peak; \r
+ uint32_t rri_cnt; \r
uint8_t spirit_pressure;\r
uint8_t p_m;\r
uint8_t screen_up;\r
\r
hrv_results_t tyhx_hrv_alg_send_data(int32_t new_raw_data, int32_t green_data_als, int32_t infrared_data);\r
hrv_results_t tyhx_hrv_alg_send_bufdata(int32_t *new_raw_data, uint8_t count, int16_t *gsen_data_x, int16_t *gsen_data_y, int16_t *gsen_data_z);\r
-#endif //HRV_ALG_LIB\r
- \r
+\r
+#endif\r
#endif\r
#include <stdint.h>\r
\r
-//version:3.3.17\r
+//version:xiaoche3.3.5\r
\r
//#include "tyhx_spo2_alg_para.h"\r
\r
-#if 0\r
-/* portable 8-bit unsigned integer */\r
-typedef unsigned char uint8_t;\r
-/* portable 8-bit signed integer */\r
-typedef signed char int8_t;\r
-/* portable 16-bit unsigned integer */\r
-typedef unsigned short int uint16_t;\r
-/* portable 16-bit signed integer */\r
-typedef signed short int int16_t;\r
-/* portable 32-bit unsigned integer */\r
-typedef unsigned int uint32_t;\r
-/* portable 32-bit signed integer */\r
-typedef signed int int32_t;\r
-#endif\r
+\r
+// /* portable 8-bit unsigned integer */\r
+// typedef unsigned char uint8_t;\r
+// /* portable 8-bit signed integer */\r
+// typedef signed char int8_t;\r
+// /* portable 16-bit unsigned integer */\r
+// typedef unsigned short int uint16_t;\r
+// /* portable 16-bit signed integer */\r
+// typedef signed short int int16_t;\r
+// /* portable 32-bit unsigned integer */\r
+// //typedef unsigned int uint32_t;\r
+// /* portable 32-bit signed integer */\r
+// //typedef signed int int32_t;\r
\r
#ifndef bool\r
#define bool unsigned char\r
\r
\r
#ifdef SPO2_ALG_LIB\r
-\r
+extern uint32_t hr_sqrt(uint32_t x);\r
typedef enum {\r
MSG_SPO2_ALG_NOT_OPEN,\r
MSG_SPO2_ALG_OPEN,\r
uint8_t screen_up;\r
uint8_t motion;\r
uint8_t poor_signal;\r
- \r
+\r
uint8_t signal_snr;\r
uint32_t signal_std;\r
- \r
+\r
} spo2_results_t;\r
\r
typedef struct {\r
\r
typedef struct {\r
uint32_t data_cnt;\r
- int32_t red_new_raw_data;\r
- int32_t ir_new_raw_data;\r
- int32_t green_new_raw_data;\r
- int32_t ir_iir_data_filter_out;\r
- int32_t ir_data_smooth;\r
- int32_t red_iir_data_filter_out;\r
- int32_t red_data_smooth;\r
+ uint8_t motion;\r
uint8_t ir_offset_50;\r
uint8_t red_offset_50;\r
uint8_t green_offset_50;\r
int32_t ir_dc;\r
int32_t red_dc;\r
int32_t green_dc;\r
- int32_t ir_data_o2_128;\r
- int32_t red_data_o2_128;\r
- int32_t green_data_o2_128;\r
- int16_t red_ir_dc;\r
- int16_t red_green_dc;\r
- int16_t ir_green_dc;\r
- int16_t ir_fft_snr;\r
- int8_t motion_status;\r
- uint8_t xcorr_max;\r
- int16_t COUNT_IN_judge;\r
+ int32_t ir_ac;\r
+ int32_t red_ac;\r
+ int32_t green_ac;\r
+ int32_t sa_temp;\r
+ int32_t gi_temp;\r
+ int32_t sa_final;\r
+ uint16_t ir_fft_snr;\r
+ uint16_t red_fft_snr;\r
+ uint8_t count_block;\r
uint8_t spo2_result;\r
- uint8_t count_block;\r
- int32_t SaO2_data_temp;\r
} spo2_debug_t;\r
\r
typedef struct {\r
uint8_t red_offset_idac;\r
- uint8_t ir_offset_idac; \r
- uint8_t green_offset_idac; \r
+ uint8_t ir_offset_idac;\r
+ uint8_t green_offset_idac;\r
uint16_t spo2_start_cnt;\r
} spo2_agcpara_t;\r
\r
spo2_results_t tyhx_spo2_alg_get_results(void);\r
spo2_debug_t tyhx_spo2_alg_debug_results(void);\r
\r
-#endif \r
+#endif\r
\r
* @Author: penglei 1624952103@qq.com\r
* @Date: 2024-06-17 14:31:08\r
* @LastEditors: penglei 1624952103@qq.com\r
- * @LastEditTime: 2025-10-21 11:11:55\r
+ * @LastEditTime: 2025-10-24 17:25:15\r
* @FilePath: /FD230/code/sdk/application/wearable/service/factorytest_service/factorytest_protocol.c\r
* @Description: \r
* \r
uint8_t databuf[4] = {0};\r
#ifdef BOARD_FD230\r
#ifdef PPG_HX3695\r
- send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_DO_SINGLE_CHECK_MODE_TEST);\r
- LOS_Msleep(2000);\r
- FT_RESULTS_t ft_result = hx3695_factroy_test(SINGLE_CHECK_TEST);\r
- send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_STOP_PPG_TEST);\r
+ // send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_DO_SINGLE_CHECK_MODE_TEST);\r
+ // LOS_Msleep(2000);\r
+ // FT_RESULTS_t ft_result = ppg_get_factory_data(SINGLE_CHECK_TEST);\r
+ // send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_STOP_PPG_TEST);\r
\r
- databuf[0] = (uint8_t)((ft_result.gr_data_final & 0xFF000000) >> 24);\r
- databuf[1] = (uint8_t)((ft_result.gr_data_final & 0x00FF0000) >> 16);\r
- databuf[2] = (uint8_t)((ft_result.gr_data_final & 0x0000FF00) >> 8);\r
- databuf[3] = (uint8_t)((ft_result.gr_data_final & 0x000000FF) >> 0);\r
+ // databuf[0] = (uint8_t)((ft_result.gr_data_final & 0xFF000000) >> 24);\r
+ // databuf[1] = (uint8_t)((ft_result.gr_data_final & 0x00FF0000) >> 16);\r
+ // databuf[2] = (uint8_t)((ft_result.gr_data_final & 0x0000FF00) >> 8);\r
+ // databuf[3] = (uint8_t)((ft_result.gr_data_final & 0x000000FF) >> 0);\r
\r
- PRINT("%2X %2X %2X %2X \r\n",databuf[0],databuf[1],databuf[2],databuf[3]);\r
+ // PRINT("%2X %2X %2X %2X \r\n",databuf[0],databuf[1],databuf[2],databuf[3]);\r
\r
factorytest_protocol_replymsg(BLE_TEST_CMD_MODE_SOFT_TEST,\r
BLE_TEST_CMD_SOFT_TEST_SUB_MODE_HRS,\r
uint8_t databuf[4] = {0};\r
#ifdef BOARD_FD230\r
#ifdef PPG_HX3695\r
- send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_DO_SINGLE_CHECK_MODE_TEST);\r
- LOS_Msleep(500);\r
- FT_RESULTS_t ft_result = hx3695_factroy_test(SINGLE_CHECK_TEST);\r
- send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_STOP_PPG_TEST);\r
-\r
- databuf[0] = (uint8_t)((ft_result.red_data_final & 0xFF000000) >> 24);\r
- databuf[1] = (uint8_t)((ft_result.red_data_final & 0x00FF0000) >> 16);\r
- databuf[2] = (uint8_t)((ft_result.red_data_final & 0x0000FF00) >> 8);\r
- databuf[3] = (uint8_t)((ft_result.red_data_final & 0x000000FF) >> 0);\r
+ // send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_DO_SINGLE_CHECK_MODE_TEST);\r
+ // LOS_Msleep(500);\r
+ // FT_RESULTS_t ft_result = hx3695_factroy_test(SINGLE_CHECK_TEST);\r
+ // send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_STOP_PPG_TEST);\r
+\r
+ // databuf[0] = (uint8_t)((ft_result.red_data_final & 0xFF000000) >> 24);\r
+ // databuf[1] = (uint8_t)((ft_result.red_data_final & 0x00FF0000) >> 16);\r
+ // databuf[2] = (uint8_t)((ft_result.red_data_final & 0x0000FF00) >> 8);\r
+ // databuf[3] = (uint8_t)((ft_result.red_data_final & 0x000000FF) >> 0);\r
#endif\r
#elif defined BOARD_N9\r
//获取红灯数据\r
send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_DO_GRAYCARD_TEST);\r
LOS_Msleep(2000);\r
uint8_t databuf[12] = {0};\r
- FT_RESULTS_t ft_result = hx3695_factroy_test(GRAY_CARD_TEST);\r
- databuf[0] = (uint8_t)((ft_result.gr_data_final & 0xFF000000) >> 24);\r
- databuf[1] = (uint8_t)((ft_result.gr_data_final & 0x00FF0000) >> 16);\r
- databuf[2] = (uint8_t)((ft_result.gr_data_final & 0x0000FF00) >> 8);\r
- databuf[3] = (uint8_t)((ft_result.gr_data_final & 0x000000FF) >> 0);\r
-\r
- databuf[4] = (uint8_t)((ft_result.red_data_final & 0xFF000000) >> 24);\r
- databuf[5] = (uint8_t)((ft_result.red_data_final & 0x00FF0000) >> 16);\r
- databuf[6] = (uint8_t)((ft_result.red_data_final & 0x0000FF00) >> 8);\r
- databuf[7] = (uint8_t)((ft_result.red_data_final & 0x000000FF) >> 0);\r
-\r
- databuf[8] = (uint8_t)((ft_result.ir_data_final & 0xFF000000) >> 24);\r
- databuf[9] = (uint8_t)((ft_result.ir_data_final & 0x00FF0000) >> 16);\r
- databuf[10] = (uint8_t)((ft_result.ir_data_final & 0x0000FF00) >> 8);\r
- databuf[11] = (uint8_t)((ft_result.ir_data_final & 0x000000FF) >> 0);\r
+ // FT_RESULTS_t ft_result = hx3695_factroy_test(GRAY_CARD_TEST);\r
+ // databuf[0] = (uint8_t)((ft_result.gr_data_final & 0xFF000000) >> 24);\r
+ // databuf[1] = (uint8_t)((ft_result.gr_data_final & 0x00FF0000) >> 16);\r
+ // databuf[2] = (uint8_t)((ft_result.gr_data_final & 0x0000FF00) >> 8);\r
+ // databuf[3] = (uint8_t)((ft_result.gr_data_final & 0x000000FF) >> 0);\r
+\r
+ // databuf[4] = (uint8_t)((ft_result.red_data_final & 0xFF000000) >> 24);\r
+ // databuf[5] = (uint8_t)((ft_result.red_data_final & 0x00FF0000) >> 16);\r
+ // databuf[6] = (uint8_t)((ft_result.red_data_final & 0x0000FF00) >> 8);\r
+ // databuf[7] = (uint8_t)((ft_result.red_data_final & 0x000000FF) >> 0);\r
+\r
+ // databuf[8] = (uint8_t)((ft_result.ir_data_final & 0xFF000000) >> 24);\r
+ // databuf[9] = (uint8_t)((ft_result.ir_data_final & 0x00FF0000) >> 16);\r
+ // databuf[10] = (uint8_t)((ft_result.ir_data_final & 0x0000FF00) >> 8);\r
+ // databuf[11] = (uint8_t)((ft_result.ir_data_final & 0x000000FF) >> 0);\r
\r
factorytest_protocol_replymsg(BLE_TEST_CMD_MODE_SOFT_TEST,\r
BLE_TEST_CMD_SOFT_TEST_SUB_MODE_HRS,\r
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