${CMAKE_CURRENT_SOURCE_DIR}/nandflash_ds35x1g.c
${CMAKE_CURRENT_SOURCE_DIR}/nandflash_f35uqa001g.c
${CMAKE_CURRENT_SOURCE_DIR}/nandflash_gd5f2gm7re.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/nandflash_xt26q02d.c
${CMAKE_CURRENT_SOURCE_DIR}/nandflash_w25n01g.c
${CMAKE_CURRENT_SOURCE_DIR}/nandflash_config.c
${CMAKE_CURRENT_SOURCE_DIR}/hal_nandflash.c
* @Author: penglei 1624952103@qq.com
* @Date: 2025-09-04 10:28:47
* @LastEditors: penglei 1624952103@qq.com
- * @LastEditTime: 2025-09-05 10:09:36
+ * @LastEditTime: 2025-09-15 14:22:31
* @FilePath: /FD230/code/sdk/bootloader/flashboot/brandy/nandflash/include/nandflash_gd5f2gm7re.h
* @Description: 这是默认设置,请设置`customMade`, 打开koroFileHeader查看配置 进行设置: https://github.com/OBKoro1/koro1FileHeader/wiki/%E9%85%8D%E7%BD%AE
*/
#define GD5F2GM7RE_BYTES_PER_OOB 64
#define GD5F2GM7RE_PAGES_PER_BLOCK 64
#define GD5F2GM7RE_TOTAL_BLOCKS 2048
-#define GD5F2GM7RE_CHIP_ID 0xC881
+#define GD5F2GM7RE_CHIP_ID 0xC882
#define GD5F2GM7RE_OOB_TOTAL_LEN 4
#define GD5F2GM7RE_OOB_PER_SIZE 8
#define GD5F2GM7RE_OOB_1_OFFSET 0
--- /dev/null
+/*
+ * @Author: penglei 1624952103@qq.com
+ * @Date: 2025-09-04 10:28:47
+ * @LastEditors: penglei 1624952103@qq.com
+ * @LastEditTime: 2025-09-15 16:59:01
+ * @FilePath: /FD230/code/sdk/bootloader/flashboot/brandy/nandflash/include/nandflash_xt26q02d.h
+ * @Description: 这是默认设置,请设置`customMade`, 打开koroFileHeader查看配置 进行设置: https://github.com/OBKoro1/koro1FileHeader/wiki/%E9%85%8D%E7%BD%AE
+ */
+/*
+ * Copyright (c) @CompanyNameMagicTag 2018-2020. All rights reserved.
+ * Description: NON-OS NANDFLASH DRIVER
+ * Author: @CompanyNameTag
+ * Create: 2020-10-15
+ */
+
+#ifndef NANDFLASH_XT26Q02D_H
+#define NANDFLASH_XT26Q02D_H
+
+#define XT26Q02D_BYTES_PER_PAGE 2048
+#define XT26Q02D_BYTES_PER_OOB 64
+#define XT26Q02D_PAGES_PER_BLOCK 64
+#define XT26Q02D_TOTAL_BLOCKS 2048
+#define XT26Q02D_CHIP_ID 0xC882
+#define XT26Q02D_OOB_TOTAL_LEN 4
+#define XT26Q02D_OOB_PER_SIZE 8
+#define XT26Q02D_OOB_1_OFFSET 0
+#define XT26Q02D_OOB_2_OFFSET 16
+#define XT26Q02D_OOB_3_OFFSET 32
+#define XT26Q02D_OOB_4_OFFSET 48
+
+extern struct nand_driver_struct g_xt26q02d_driver;
+
+#endif /* End of #ifndef MC_NAND_XT26Q02D_H */
#include "nandflash_w25n01g.h"\r
#include "nandflash_f35uqa001g.h"\r
#include "nandflash_gd5f2gm7re.h"\r
+#include "nandflash_xt26q02d.h"\r
#include "nandflash_inner.h"\r
#include "nandflash.h"\r
#include "hal_nandflash.h"\r
return &g_f35uqa001g_driver;\r
#elif defined(NANDFLASH_GD5F2G)\r
return &g_gd5f2gm7re_driver; \r
+ #elif defined(NANDFLASH_XT26Q02D)\r
+ return &g_xt26q02d_driver; \r
#else\r
return &g_ds35x1g_driver; \r
#endif\r
--- /dev/null
+/*
+ * Copyright (c) @CompanyNameMagicTag 2018-2020. All rights reserved.
+ * Description: NON-OS NANDFLASH DRIVER
+ * Author: @CompanyNameTag
+ * Create: 2020-10-15
+ */
+
+#include <stdint.h>
+#include "debug_print.h"
+#include "nandflash_inner.h"
+#include "nandflash.h"
+#include "hal_nandflash.h"
+#include "nandflash_config.h"
+#include "nandflash_xt26q02d.h"
+
+#define XT26Q02D_GET_ECC_STATUS(x) ((0x30 & (x)) >> 4)
+#define XT26Q02D_ECC_CORRECTION 0x00
+#define XT26Q02D_ECC_1BIT_CORRET 0x01
+#define XT26Q02D_ECC_4BIT_CORRET 0x02
+#define XT26Q02D_ECC_ERROR 0x03
+#define NAND_ID_DATA_SIZE 0x2
+
+static qspi_data_type_def g_qspi_data = {0};
+
+static uint32_t mc_xt26q02d_read_page(
+ uint32_t nand_page, uint8_t *data, uint32_t data_len, uint8_t *oob, uint32_t oob_len, const uint32_t *ecc_result)
+{
+ uint32_t ret;
+ uint8_t status_reg;
+
+ UNUSED(ecc_result);
+ ret = mc_flash_read_page(nand_page, data, data_len, oob, oob_len, &status_reg);
+ if (get_nand_flash()->enable_ecc == true) {
+ if (XT26Q02D_GET_ECC_STATUS(status_reg) >= XT26Q02D_ECC_ERROR) {
+ return MC_FAILURE;
+ } else {
+ return MC_SUCCESS;
+ }
+ }
+ return ret;
+}
+
+static uint32_t mc_xt26q02d_init(void)
+{
+ nand_driver_init(SPEED_MID);
+ PRINT("xt26q02d_init \r\n");
+ uint32_t ret;
+ mc_flash_write_cmd(CMD_FLASH_RESET); /* tRST 5us,no command will be accepted */
+ mc_flash_busy_wait();
+ write_cmd(CMD_FLASH_WREN);
+ ret = mc_flash_write_sr(CMD_FLASH_SR1_ADDR, 0x0); /* set SR1 0,Clear block protect bits */
+ if (get_nand_flash()->enable_ecc == true) {
+ ret = mc_flash_write_sr(CMD_FLASH_SR2_ADDR, 0x11); /* set SR1 0,Clear block protect bits */
+ } else {
+ ret = mc_flash_write_sr(CMD_FLASH_SR2_ADDR, 0x01); /* set SR1 0,Clear block protect bits */
+ }
+ PRINT("nandflash mc_flash_write_sr ret %d \r\n", ret);
+ uint8_t status_reg;
+ mc_flash_read_sr(CMD_FLASH_SR1_ADDR, (uint8_t *)&status_reg);
+ PRINT("nandflash A0 Reg:0x%x \r\n", status_reg);
+ mc_flash_read_sr(CMD_FLASH_SR2_ADDR, (uint8_t *)&status_reg);
+ PRINT("nandflash B0 Reg:0x%x \r\n", status_reg);
+ mc_flash_read_sr(CMD_FLASH_SR3_ADDR, (uint8_t *)&status_reg);
+ PRINT("nandflash C0 Reg:0x%x \r\n", status_reg);
+ if (ret != MC_SUCCESS || status_reg != 0x2) {
+ return MC_FAILURE;
+ }
+ return MC_SUCCESS;
+}
+
+static uint16_t mc_xt26q02d_check_id(void)
+{
+ g_qspi_data.instruction = CMD_FLASH_ID;
+ g_qspi_data.address_mode = MC_OSPI_ADDRESS_NONE;
+ g_qspi_data.address = 0;
+ g_qspi_data.address_size = 0;
+ g_qspi_data.dummy_cycles = MC_OSPI_CYCLES_8_BITS;
+ g_qspi_data.data_mode = MC_OSPI_DATA_1_LINE;
+ g_qspi_data.data_size = NAND_ID_DATA_SIZE;
+ uint16_t nand_flash_id = read_id(&g_qspi_data);
+ PRINT("nandflash id 0x%04X \r\n",nand_flash_id);
+ return nand_flash_id;
+}
+
+struct nand_driver_struct g_xt26q02d_driver = {mc_xt26q02d_init,
+ mc_xt26q02d_check_id,
+ mc_xt26q02d_read_page,
+ mc_flash_write_page,
+ mc_flash_erase_block,
+ mc_flash_mark_bad_block,
+ mc_flash_check_bad_block,
+ XT26Q02D_BYTES_PER_PAGE,
+ XT26Q02D_BYTES_PER_OOB,
+ XT26Q02D_PAGES_PER_BLOCK,
+ XT26Q02D_TOTAL_BLOCKS,
+ XT26Q02D_CHIP_ID,
+ XT26Q02D_OOB_TOTAL_LEN,
+ XT26Q02D_OOB_PER_SIZE,
+ XT26Q02D_OOB_PER_SIZE,
+ XT26Q02D_OOB_PER_SIZE,
+ XT26Q02D_OOB_PER_SIZE,
+ XT26Q02D_OOB_1_OFFSET,
+ XT26Q02D_OOB_2_OFFSET,
+ XT26Q02D_OOB_3_OFFSET,
+ XT26Q02D_OOB_4_OFFSET,
+#ifdef ENABLE_ECC
+ true
+#else
+ false
+#endif
+ };
# 'ROTARYENCODER_HX3507',
# 'NANDFLASH_F35UQA',
'NANDFLASH_GD5F2G',
+ # 'NANDFLASH_XT26Q02D',
'BLE_INSTRUCT',
'-:SUPPORT_ALIPAY_SEC',
# 'AILPAY_SUPPORT',
# 'MEMORY_CORRUPTION',
'SAP_EFFECT_SWS_SUPPORT',
'AUDIO_SMARTPA_AW88082',
+ 'LCD_JD9885',
# 'SUPPORT_LEINIAO',暂时屏蔽
],
#添加自定义应用
'FT_SINGLE_UART',
# 'NANDFLASH_F35UQA',
'NANDFLASH_GD5F2G',
+ # 'NANDFLASH_XT26Q02D',
# 'TPTYPE_FT6X46',
'CFG_FLASH_SIZE=16',
'LEINIAO',
'LEINIAO',
# 'NANDFLASH_F35UQA',
'NANDFLASH_GD5F2G',
- 'GPIO_POWERON_FLASH'
+ # 'NANDFLASH_XT26Q02D',
+ 'GPIO_POWERON_FLASH',
]
},
}
#endif\r
};\r
\r
-#ifdef BOARD_LEINIAO\r
+#ifdef LCD_JD9885\r
\r
/* display off sequence for common lcd */\r
const lcd_cmd_sequ g_common_cmd_display_off[] = {\r
${CMAKE_CURRENT_SOURCE_DIR}/nand/nandflash_ds35x1g.c
${CMAKE_CURRENT_SOURCE_DIR}/nand/nandflash_f35uqa001g.c
${CMAKE_CURRENT_SOURCE_DIR}/nand/nandflash_gd5f2gm7re.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/nand/nandflash_xt26q02d.c
${CMAKE_CURRENT_SOURCE_DIR}/nand/nandflash_tc58cyg.c
${CMAKE_CURRENT_SOURCE_DIR}/nand/nandflash_w25n01g.c
${CMAKE_CURRENT_SOURCE_DIR}/nand/nandflash_config.c
* @Author: penglei 1624952103@qq.com
* @Date: 2025-09-04 10:04:03
* @LastEditors: penglei 1624952103@qq.com
- * @LastEditTime: 2025-09-05 10:09:32
+ * @LastEditTime: 2025-09-15 14:23:04
* @FilePath: /FD230/code/sdk/drivers/drivers/driver/nand_flash/nand/include/nandflash_gd5f2gm7re.h
* @Description: 这是默认设置,请设置`customMade`, 打开koroFileHeader查看配置 进行设置: https://github.com/OBKoro1/koro1FileHeader/wiki/%E9%85%8D%E7%BD%AE
*/
#define GD5F2GM7RE_BYTES_PER_OOB 64
#define GD5F2GM7RE_PAGES_PER_BLOCK 64
#define GD5F2GM7RE_TOTAL_BLOCKS 2048
-#define GD5F2GM7RE_CHIP_ID 0xC881
+#define GD5F2GM7RE_CHIP_ID 0xC882
#define GD5F2GM7RE_OOB_TOTAL_LEN 4
#define GD5F2GM7RE_OOB_PER_SIZE 8
#define GD5F2GM7RE_OOB_1_OFFSET 0
--- /dev/null
+/*
+ * @Author: penglei 1624952103@qq.com
+ * @Date: 2025-09-04 10:28:47
+ * @LastEditors: penglei 1624952103@qq.com
+ * @LastEditTime: 2025-09-15 16:58:55
+ * @FilePath: /FD230/code/sdk/bootloader/flashboot/brandy/nandflash/include/nandflash_xt26q02d.h
+ * @Description: 这是默认设置,请设置`customMade`, 打开koroFileHeader查看配置 进行设置: https://github.com/OBKoro1/koro1FileHeader/wiki/%E9%85%8D%E7%BD%AE
+ */
+/*
+ * Copyright (c) @CompanyNameMagicTag 2018-2020. All rights reserved.
+ * Description: NON-OS NANDFLASH DRIVER
+ * Author: @CompanyNameTag
+ * Create: 2020-10-15
+ */
+
+#ifndef NANDFLASH_XT26Q02D_H
+#define NANDFLASH_XT26Q02D_H
+
+#define XT26Q02D_BYTES_PER_PAGE 2048
+#define XT26Q02D_BYTES_PER_OOB 64
+#define XT26Q02D_PAGES_PER_BLOCK 64
+#define XT26Q02D_TOTAL_BLOCKS 2048
+#define XT26Q02D_CHIP_ID 0xC882
+#define XT26Q02D_OOB_TOTAL_LEN 4
+#define XT26Q02D_OOB_PER_SIZE 8
+#define XT26Q02D_OOB_1_OFFSET 0
+#define XT26Q02D_OOB_2_OFFSET 16
+#define XT26Q02D_OOB_3_OFFSET 32
+#define XT26Q02D_OOB_4_OFFSET 48
+
+extern struct nand_driver_struct g_xt26q02d_driver;
+
+#endif /* End of #ifndef MC_NAND_XT26Q02D_H */
#include "nandflash_ds35x1g.h"\r
#include "nandflash_f35uqa001g.h"\r
#include "nandflash_gd5f2gm7re.h"\r
+#include "nandflash_xt26q02d.h"\r
#include "nandflash_w25n01g.h"\r
#include "nandflash_to_os.h"\r
#include "nandflash_inner.h"\r
return &g_f35uqa001g_driver;\r
#elif defined(NANDFLASH_GD5F2G)\r
return &g_gd5f2gm7re_driver; \r
+ #elif defined(NANDFLASH_XT26Q02D)\r
+ return &g_xt26q02d_driver; \r
#else\r
return &g_ds35x1g_driver; \r
#endif\r
--- /dev/null
+/*
+ * Copyright (c) @CompanyNameMagicTag 2018-2020. All rights reserved.
+ * Description: NON-OS NANDFLASH DRIVER
+ * Author: @CompanyNameTag
+ * Create: 2020-10-15
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include "debug_print.h"
+#include "nandflash_inner.h"
+#include "nandflash.h"
+#include "hal_nandflash.h"
+#include "nandflash_config.h"
+#include "nandflash_xt26q02d.h"
+
+#define XT26Q02D_GET_ECC_STATUS(x) ((0x30 & (x)) >> 4)
+#define XT26Q02D_ECC_CORRECTION 0x00
+#define XT26Q02D_ECC_1BIT_CORRET 0x01
+#define XT26Q02D_ECC_4BIT_CORRET 0x02
+#define XT26Q02D_ECC_ERROR 0x03
+#define NAND_ID_DATA_SIZE 0x2
+
+static qspi_data_type_def g_qspi_data = {0};
+
+static uint32_t mc_xt26q02d_read_page(uint32_t nand_page, uint8_t *data, uint32_t data_len, uint8_t *oob,
+ uint32_t oob_len, const uint32_t *ecc_result, enum nandflash_trans_type type)
+{
+ unused(ecc_result);
+ uint32_t ret;
+ uint8_t status_reg;
+ ret = mc_flash_read_page(nand_page, data, data_len, oob, oob_len, &status_reg, type);
+ if (get_nand_flash()->enable_ecc == true) {
+ if (XT26Q02D_GET_ECC_STATUS(status_reg) >= XT26Q02D_ECC_ERROR) {
+ return MC_FAILURE;
+ } else {
+ return MC_SUCCESS;
+ }
+ }
+ return ret;
+}
+
+static uint32_t mc_xt26q02d_init(void)
+{
+ nand_driver_init(SPEED_MID);
+ nand_driver_sem_init();
+ PRINT("xt26q02d_init \r\n");
+ uint32_t ret;
+ mc_flash_write_cmd(CMD_FLASH_RESET); /* tRST 5us,no command will be accepted */
+ mc_flash_busy_wait();
+ write_cmd(CMD_FLASH_WREN);
+ ret = mc_flash_write_sr(CMD_FLASH_SR1_ADDR, 0x0); /* set SR1 0,Clear block protect bits */
+ if (get_nand_flash()->enable_ecc == true) {
+ ret = mc_flash_write_sr(CMD_FLASH_SR2_ADDR, 0x11); /* set SR1 0,Clear block protect bits */
+ } else {
+ ret = mc_flash_write_sr(CMD_FLASH_SR2_ADDR, 0x01); /* set SR1 0,Clear block protect bits */
+ }
+ uint8_t status_reg;
+ mc_flash_read_sr(CMD_FLASH_SR1_ADDR, (uint8_t *)&status_reg);
+ PRINT("nandflash A0 Reg:0x%x \r\n", status_reg);
+ mc_flash_read_sr(CMD_FLASH_SR2_ADDR, (uint8_t *)&status_reg);
+ PRINT("nandflash B0 Reg:0x%x \r\n", status_reg);
+ mc_flash_read_sr(CMD_FLASH_SR3_ADDR, (uint8_t *)&status_reg);
+ PRINT("nandflash C0 Reg:0x%x \r\n", status_reg);
+ if (ret != MC_SUCCESS || status_reg != 0x2) {
+ return MC_FAILURE;
+ }
+ return MC_SUCCESS;
+}
+
+static uint16_t mc_xt26q02d_check_id(void)
+{
+ g_qspi_data.instruction = CMD_FLASH_ID;
+ g_qspi_data.address_mode = MC_OSPI_ADDRESS_NONE;
+ g_qspi_data.address = 0;
+ g_qspi_data.address_size = 0;
+ g_qspi_data.dummy_cycles = MC_OSPI_CYCLES_8_BITS;
+ g_qspi_data.data_mode = MC_OSPI_DATA_1_LINE;
+ g_qspi_data.data_size = NAND_ID_DATA_SIZE;
+ return read_id(&g_qspi_data);
+}
+
+struct nand_driver_struct g_xt26q02d_driver = {mc_xt26q02d_init,
+ mc_xt26q02d_check_id,
+ mc_xt26q02d_read_page,
+ mc_flash_write_page,
+ mc_flash_erase_block,
+ mc_flash_mark_bad_block,
+ mc_flash_check_bad_block,
+ XT26Q02D_BYTES_PER_PAGE,
+ XT26Q02D_BYTES_PER_OOB,
+ XT26Q02D_PAGES_PER_BLOCK,
+ XT26Q02D_TOTAL_BLOCKS,
+ XT26Q02D_CHIP_ID,
+ XT26Q02D_OOB_TOTAL_LEN,
+ XT26Q02D_OOB_PER_SIZE,
+ XT26Q02D_OOB_PER_SIZE,
+ XT26Q02D_OOB_PER_SIZE,
+ XT26Q02D_OOB_PER_SIZE,
+ XT26Q02D_OOB_1_OFFSET,
+ XT26Q02D_OOB_2_OFFSET,
+ XT26Q02D_OOB_3_OFFSET,
+ XT26Q02D_OOB_4_OFFSET,
+#ifdef ENABLE_ECC
+ true
+#else
+ false
+#endif
+ };
// 设置预估的总文件数（通常有多个.eph文件和一个AssistInfo.dat文件）
// 这个数值会在实际解析JSON后更新
- set_total_files(8); // 预估8个文件
+ set_total_files(26); // 预估26个文件
printf("Starting AGNSS download, set download flag, status: 0 (连接中)\n");
}
memset(best_folder_name, 0, 64);
- printf("=== AGNSS Status Check ===\n");
- printf("Current timestamp: %u\n", current_timestamp);
+ // printf("=== AGNSS Status Check ===\n");
+ // printf("Current timestamp: %u\n", current_timestamp);
// 遍历目录中的所有文件夹
while ((entry = readdir(dir)) != NULL) {
closedir(sub_dir);
}
- printf("Found AGNSS folder: %s (age: %u seconds, files: %d)\n",
- entry->d_name, time_diff, file_count);
+ // printf("Found AGNSS folder: %s (age: %u seconds, files: %d)\n",
+ // entry->d_name, time_diff, file_count);
// 检查是否在24小时内且文件数量足够
if (time_diff < 86400 && file_count >= 20) { // 24小时 = 86400秒
if (found_valid_folder) {
uint32_t remaining_time = 86400 - min_time_diff; // 24小时 - 已过时间
- printf("✓ AGNSS Status: VALID\n");
- printf(" Folder: %s\n", best_folder_name);
- printf(" File count: %d\n", best_file_count);
- printf(" Remaining time: %u seconds (%.1f hours)\n",
- remaining_time, remaining_time / 3600.0);
+ // printf("✓ AGNSS Status: VALID\n");
+ // printf(" Folder: %s\n", best_folder_name);
+ // printf(" File count: %d\n", best_file_count);
+ // printf(" Remaining time: %u seconds (%.1f hours)\n",
+ // remaining_time, remaining_time / 3600.0);
// 释放内存
free(best_folder_name);
// 返回剩余时间的分钟数
int remaining_minutes = remaining_time / 60;
- printf("=== AGNSS Status Check Complete ===\n");
+ // printf("=== AGNSS Status Check Complete ===\n");
return remaining_minutes;
} else {
- printf("✗ AGNSS Status: EXPIRED or NOT FOUND\n");
- printf(" No valid AGNSS data within 30 hours\n");
+ // printf("✗ AGNSS Status: EXPIRED or NOT FOUND\n");
+ // printf(" No valid AGNSS data within 24 hours\n");
// 释放内存
free(best_folder_name);
- printf("=== AGNSS Status Check Complete ===\n");
+ // printf("=== AGNSS Status Check Complete ===\n");
// 过期返回0
return 0;
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