From: penglei <1624952103@qq.com> Date: Mon, 27 Oct 2025 07:10:08 +0000 (+0800) Subject: 屏蔽运动不需要的topic，优化燃脂时间计算，合入3695新驱动，支持hrv测量 X-Git-Tag: V1.0.9_20251128_194606_LN~171 X-Git-Url: http://git.snicker.com.cn/?a=commitdiff_plain;h=caf5b1485ee614ead4673023d17969b9f67c8f42;p=mirrors%2FFD230.git 屏蔽运动不需要的topic，优化燃脂时间计算，合入3695新驱动，支持hrv测量 --- diff --git a/code/sdk/application/wearable/fd230/nativeapp/nativeui/traing/src/TraingModel.cpp b/code/sdk/application/wearable/fd230/nativeapp/nativeui/traing/src/TraingModel.cpp index 6b989104c..ff45122e6 100644 --- a/code/sdk/application/wearable/fd230/nativeapp/nativeui/traing/src/TraingModel.cpp +++ b/code/sdk/application/wearable/fd230/nativeapp/nativeui/traing/src/TraingModel.cpp @@ -167,42 +167,42 @@ return; } //训练基本信息更新 - if (request->msgId == TOPIC_EVENT_ACTIVITY_UPDATE) { - act_result_t *cyweeInfo = new act_result_t(); - int rets = memcpy_s(cyweeInfo, sizeof(act_result_t), - (act_result_t *)request->data, request->len); - if (rets != EOK) { - delete cyweeInfo; // 处理内存分配失败的情况 - cyweeInfo = NULL; - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, - "memcpy_s act_result_t fail ret = %d", rets); - return; - } - TraingModel::GetInstance()->AnalysisData(cyweeInfo); - // 更新其他目标完成度 - TraingModel::GetInstance()->CheckSportTag(); - delete cyweeInfo; // 释放内存 - } - //训练额外信息 - if (request->msgId == TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE) { - act_ext_result_t *cyweeInfo_ext = new act_ext_result_t(); - int rets = memcpy_s(cyweeInfo_ext, sizeof(act_ext_result_t), - (act_ext_result_t *)request->data, request->len); - if (rets != EOK) { - delete cyweeInfo_ext; // 处理内存分配失败的情况 - cyweeInfo_ext = NULL; - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, - "memcpy_s act_ext_result_t fail ret = %d", rets); - return; - } - TraingModel::GetInstance()->AnalysisExtraData(cyweeInfo_ext); - delete cyweeInfo_ext; // 释放内存 - } + // if (request->msgId == TOPIC_EVENT_ACTIVITY_UPDATE) { + // act_result_t *cyweeInfo = new act_result_t(); + // int rets = memcpy_s(cyweeInfo, sizeof(act_result_t), + // (act_result_t *)request->data, request->len); + // if (rets != EOK) { + // delete cyweeInfo; // 处理内存分配失败的情况 + // cyweeInfo = NULL; + // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, + // "memcpy_s act_result_t fail ret = %d", rets); + // return; + // } + // TraingModel::GetInstance()->AnalysisData(cyweeInfo); + // // 更新其他目标完成度 + // TraingModel::GetInstance()->CheckSportTag(); + // delete cyweeInfo; // 释放内存 + // } + // //训练额外信息 + // if (request->msgId == TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE) { + // act_ext_result_t *cyweeInfo_ext = new act_ext_result_t(); + // int rets = memcpy_s(cyweeInfo_ext, sizeof(act_ext_result_t), + // (act_ext_result_t *)request->data, request->len); + // if (rets != EOK) { + // delete cyweeInfo_ext; // 处理内存分配失败的情况 + // cyweeInfo_ext = NULL; + // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, + // "memcpy_s act_ext_result_t fail ret = %d", rets); + // return; + // } + // TraingModel::GetInstance()->AnalysisExtraData(cyweeInfo_ext); + // delete cyweeInfo_ext; // 释放内存 + // } //训练心率 - if (request->msgId == TOPIC_EVENT_HEARTRATE_UPDATA) { - uint8_t heart = *((u_int8_t *)(request->data)); // 进行类型转换 - TraingModel::GetInstance()->AnalysisHeartData(heart); - } + // if (request->msgId == TOPIC_EVENT_HEARTRATE_UPDATA) { + // uint8_t heart = *((u_int8_t *)(request->data)); // 进行类型转换 + // TraingModel::GetInstance()->AnalysisHeartData(heart); + // } #endif } #ifdef __cplusplus diff --git a/code/sdk/application/wearable/fd230/service/broadcast/include/broadcast_feature.h b/code/sdk/application/wearable/fd230/service/broadcast/include/broadcast_feature.h index ce6030c7b..42f1f9241 100644 --- a/code/sdk/application/wearable/fd230/service/broadcast/include/broadcast_feature.h +++ b/code/sdk/application/wearable/fd230/service/broadcast/include/broadcast_feature.h @@ -51,16 +51,16 @@ typedef enum { TOPIC_EVENT_SPORT_DISTANCE, TOPIC_EVENT_LOCATION, TOPIC_EVENT_HFP_HINT, -// #ifdef SUPPORT_CYWEE_SERVICE - TOPIC_EVENT_ACTIVITY_UPDATE, - TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, +#ifdef SUPPORT_CYWEE_SERVICE + // TOPIC_EVENT_ACTIVITY_UPDATE, + // TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, TOPIC_EVENT_AR_ALERT_TYPE_UPDATE, TOPIC_EVENT_INACTIVITY_UPDATE, - TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, + // TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, +#endif TOPIC_EVENT_BLE_TRAINING, TOPIC_EVENT_BLE_TRANSMIT, TOPIC_EVENT_GOAL_SHOW_VIEW, -// #endif TOPIC_EVENT_CHARGE_PLUG, TOPIC_EVENT_CHARGE_UNPLUG, TOPIC_EVENT_LOWPOWER_ALARM, diff --git a/code/sdk/application/wearable/fd230/service/broadcast/src/broadcast_implement.c b/code/sdk/application/wearable/fd230/service/broadcast/src/broadcast_implement.c index 963c28c53..5ec2a32f4 100644 --- a/code/sdk/application/wearable/fd230/service/broadcast/src/broadcast_implement.c +++ b/code/sdk/application/wearable/fd230/service/broadcast/src/broadcast_implement.c @@ -30,15 +30,14 @@ static const TopicToCore topicToCoreArray[] = { {TOPIC_EVENT_STATIC_HEARTRATE_UPDATA, A_CORE_MASK, 1}, {TOPIC_EVENT_BLE_TRAINING,A_CORE_MASK,1}, {TOPIC_EVENT_BLE_TRANSMIT,A_CORE_MASK,1}, -#ifdef CYWEE_SPORT - {TOPIC_EVENT_ACTIVITY_UPDATE, A_CORE_MASK, 1}, - {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, A_CORE_MASK, 1}, +#ifdef SUPPORT_CYWEE_SERVICE + // {TOPIC_EVENT_ACTIVITY_UPDATE, A_CORE_MASK, 1}, + // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, A_CORE_MASK, 1}, {TOPIC_EVENT_AR_ALERT_TYPE_UPDATE, A_CORE_MASK, 1}, {TOPIC_EVENT_INACTIVITY_UPDATE, A_CORE_MASK, 1}, - {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, A_CORE_MASK, 1}, - {TOPIC_EVENT_GOAL_SHOW_VIEW,A_CORE_MASK,1}, - + // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, A_CORE_MASK, 1}, #endif + {TOPIC_EVENT_GOAL_SHOW_VIEW,A_CORE_MASK,1}, #ifdef SUPPORT_SPO2_NOTIFICATION {TOPIC_EVENT_SPO2_UPDATE, A_CORE_MASK, 1}, {TOPIC_EVENT_START_HRS_MONITORING, A_CORE_MASK, 1}, diff --git a/code/sdk/application/wearable/fd230/service/msg_center/src/msg_center_customer.cpp b/code/sdk/application/wearable/fd230/service/msg_center/src/msg_center_customer.cpp index c311cc7ee..e5c15c5da 100644 --- a/code/sdk/application/wearable/fd230/service/msg_center/src/msg_center_customer.cpp +++ b/code/sdk/application/wearable/fd230/service/msg_center/src/msg_center_customer.cpp @@ -118,14 +118,14 @@ const PriorityMapper PRI_MAPPER[] = { #endif {TOPIC_EVENT_ON_TIME,PRIORITY_TWO}, -#if 0 - {TOPIC_EVENT_ACTIVITY_UPDATE,PRIORITY_TWO}, - {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,PRIORITY_TWO}, +#ifdef SUPPORT_CYWEE_SERVICE + // {TOPIC_EVENT_ACTIVITY_UPDATE,PRIORITY_TWO}, + // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,PRIORITY_TWO}, {TOPIC_EVENT_AR_ALERT_TYPE_UPDATE,PRIORITY_TWO}, {TOPIC_EVENT_INACTIVITY_UPDATE,PRIORITY_TWO}, - {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,PRIORITY_TWO}, - {TOPIC_EVENT_GOAL_SHOW_VIEW,PRIORITY_TWO}, + // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,PRIORITY_TWO}, #endif + {TOPIC_EVENT_GOAL_SHOW_VIEW,PRIORITY_TWO}, {TOPIC_EVENT_STEPDATA_UPDATE,PRIORITY_TWO}, @@ -179,11 +179,11 @@ void MsgCenterSubscribe() MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_PHONE_TO_WATCH); MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_WATCH_TO_PHONE); MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_HINT); - MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_UPDATE); - MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE); + // MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_UPDATE); + // MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE); MsgCenterSubscribeTopic(TOPIC_EVENT_AR_ALERT_TYPE_UPDATE); MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_UPDATE); - MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE); + // MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE); MsgCenterSubscribeTopic(TOPIC_EVENT_BLE_TRAINING); MsgCenterSubscribeTopic(TOPIC_EVENT_BLE_TRANSMIT); MsgCenterSubscribeTopic(TOPIC_EVENT_GOAL_SHOW_VIEW); @@ -1136,92 +1136,92 @@ void MsgCenterNotifyCat1FailEProc(const Topic topic, Request* req) } -#if 0 +#ifdef SUPPORT_CYWEE_SERVICE //每日训练数据刷新 - void MsgCenterNotifyActivityProc(const Topic topic, Request* req) - { - unused(topic); - cywee_activity_result_t* c_activity_result_t = (cywee_activity_result_t *) malloc(req->len); - if(c_activity_result_t==NULL) - { - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure"); - return; - } - - int rets = memcpy_s(c_activity_result_t, req->len, (cywee_activity_result_t*)req->data, req->len); - if (rets != EOK) - { - free(c_activity_result_t); - c_activity_result_t = NULL; - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_t failed, ret = %d", rets); - return; - } - if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_NORMAL) - { - /*更新卡路里数据*/ - //if(c_activity_result_t->calories!=0) - { - set_calories_data(c_activity_result_t->calories); - #if DIALDATASET - uint32_t calories= OHOS::GoalModel::GetInstance().show_data_calories_refresh(); + // void MsgCenterNotifyActivityProc(const Topic topic, Request* req) + // { + // unused(topic); + // cywee_activity_result_t* c_activity_result_t = (cywee_activity_result_t *) malloc(req->len); + // if(c_activity_result_t==NULL) + // { + // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure"); + // return; + // } + + // int rets = memcpy_s(c_activity_result_t, req->len, (cywee_activity_result_t*)req->data, req->len); + // if (rets != EOK) + // { + // free(c_activity_result_t); + // c_activity_result_t = NULL; + // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_t failed, ret = %d", rets); + // return; + // } + // if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_NORMAL) + // { + // /*更新卡路里数据*/ + // //if(c_activity_result_t->calories!=0) + // { + // set_calories_data(c_activity_result_t->calories); + // #if DIALDATASET + // uint32_t calories= OHOS::GoalModel::GetInstance().show_data_calories_refresh(); - DialModelCalorie::GetInstance()->UpdateCalorie(calories); - #endif - } - /*更新距离数据*/ - //if(c_activity_result_t->distance != 0) - { - set_distance_data(c_activity_result_t->distance); - #if DIALDATASET - float distance= OHOS::GoalModel::GetInstance().show_data_distance_refresh(); - DialModelDistance::GetInstance()->UpdateDistance(distance); - #endif - } - } - else if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_FREE_TRAINING && c_activity_result_t->MHR_zone >= 2) - { - /*更新燃脂时间数据*/ - set_fat_time_data(1); - } + // DialModelCalorie::GetInstance()->UpdateCalorie(calories); + // #endif + // } + // /*更新距离数据*/ + // //if(c_activity_result_t->distance != 0) + // { + // set_distance_data(c_activity_result_t->distance); + // #if DIALDATASET + // float distance= OHOS::GoalModel::GetInstance().show_data_distance_refresh(); + // DialModelDistance::GetInstance()->UpdateDistance(distance); + // #endif + // } + // } + // else if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_FREE_TRAINING && c_activity_result_t->MHR_zone >= 2) + // { + // /*更新燃脂时间数据*/ + // set_fat_time_data(1); + // } - free(c_activity_result_t); - c_activity_result_t = NULL; - } - static int train_fat_time = 0; - void MsgCenterNotifyActivityExtraInfoProc(const Topic topic, Request* req) - { - unused(topic); - cywee_activity_result_extre_info_t* c_activity_result_extre_info_t = (cywee_activity_result_extre_info_t *) malloc(req->len); - if(c_activity_result_extre_info_t==NULL) - { - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure"); - return; - } - - int rets = memcpy_s(c_activity_result_extre_info_t, req->len, (cywee_activity_result_extre_info_t*)req->data, req->len); - if (rets != EOK) - { - free(c_activity_result_extre_info_t); - c_activity_result_extre_info_t = NULL; - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_extre_info_t failed, ret = %d", rets); - return; - } - - if(uapi_dev_runtime_get_train_status() && c_activity_result_extre_info_t->ativity_zone_high_duration) - { - train_fat_time = c_activity_result_extre_info_t->ativity_zone_high_duration; - } - /*更新燃脂时间数据*/ - else if(uapi_dev_runtime_get_train_status() == 0 && train_fat_time) - { - set_fat_time_data(train_fat_time); - train_fat_time = 0; - } + // free(c_activity_result_t); + // c_activity_result_t = NULL; + // } + // static int train_fat_time = 0; + // void MsgCenterNotifyActivityExtraInfoProc(const Topic topic, Request* req) + // { + // unused(topic); + // cywee_activity_result_extre_info_t* c_activity_result_extre_info_t = (cywee_activity_result_extre_info_t *) malloc(req->len); + // if(c_activity_result_extre_info_t==NULL) + // { + // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure"); + // return; + // } + + // int rets = memcpy_s(c_activity_result_extre_info_t, req->len, (cywee_activity_result_extre_info_t*)req->data, req->len); + // if (rets != EOK) + // { + // free(c_activity_result_extre_info_t); + // c_activity_result_extre_info_t = NULL; + // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_extre_info_t failed, ret = %d", rets); + // return; + // } + + // if(uapi_dev_runtime_get_train_status() && c_activity_result_extre_info_t->ativity_zone_high_duration) + // { + // train_fat_time = c_activity_result_extre_info_t->ativity_zone_high_duration; + // } + // /*更新燃脂时间数据*/ + // else if(uapi_dev_runtime_get_train_status() == 0 && train_fat_time) + // { + // set_fat_time_data(train_fat_time); + // train_fat_time = 0; + // } + + // free(c_activity_result_extre_info_t); + // c_activity_result_extre_info_t = NULL; + // } - free(c_activity_result_extre_info_t); - c_activity_result_extre_info_t = NULL; - } -#endif /*运动识别*/ void MsgCenterNotifyArAlertProc(const Topic topic, Request* req) { @@ -1244,7 +1244,6 @@ void MsgCenterNotifyArAlertProc(const Topic topic, Request* req) void MsgCenterNotifyInactivityProc(const Topic topic, Request *req) { WEARABLE_LOGI(WEARABLE_LOG_MODULE_APP, "MsgCenterNotifyInactivityProc !"); -#ifdef SUPPORT_CYWEE_SERVICE inact_result_t *cywee_Inactivity_Info = (inact_result_t *)malloc(req->len); if (!cywee_Inactivity_Info) { @@ -1286,9 +1285,10 @@ void MsgCenterNotifyInactivityProc(const Topic topic, Request *req) free(cywee_Inactivity_Info); cywee_Inactivity_Info = NULL; -#endif } +#endif + //查找手表通知 void MsgCenterNotifyFindWatchProc(const Topic topic, Request* req) { @@ -1521,14 +1521,14 @@ static MsgCenterNotifyTable g_msgCenterNotifyTable[] = { {TOPIC_EVENT_HFP_PHONE_TO_WATCH, MsgCenterNotifyHfpWatchProc}, {TOPIC_EVENT_HFP_HINT, MsgCenterNotifyHfpWatchHintProc}, -#if 0 - {TOPIC_EVENT_ACTIVITY_UPDATE, MsgCenterNotifyActivityProc}, - {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, MsgCenterNotifyActivityExtraInfoProc}, +#ifdef SUPPORT_CYWEE_SERVICE + // {TOPIC_EVENT_ACTIVITY_UPDATE, MsgCenterNotifyActivityProc}, + // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, MsgCenterNotifyActivityExtraInfoProc}, {TOPIC_EVENT_AR_ALERT_TYPE_UPDATE, MsgCenterNotifyArAlertProc}, {TOPIC_EVENT_INACTIVITY_UPDATE, MsgCenterNotifyInactivityProc}, - {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, MsgCenterNotifyInactivityAccumulateTimeProc}, - {TOPIC_EVENT_GOAL_SHOW_VIEW, MsgCenterNotifygoalnotificationviewProc}, + // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, MsgCenterNotifyInactivityAccumulateTimeProc}, #endif + // {TOPIC_EVENT_GOAL_SHOW_VIEW, MsgCenterNotifygoalnotificationviewProc},//编译不过 {TOPIC_EVENT_BLE_TRANSMIT, MsgCenterNotifybleTransmit}, {TOPIC_EVENT_CHARGE_PLUG, MsgCenterNotifyChargePlugProc}, diff --git a/code/sdk/application/wearable/fd272/nativeapp/nativeui/traing/src/TraingModel.cpp b/code/sdk/application/wearable/fd272/nativeapp/nativeui/traing/src/TraingModel.cpp index 6b989104c..c755e30d5 100644 --- a/code/sdk/application/wearable/fd272/nativeapp/nativeui/traing/src/TraingModel.cpp +++ b/code/sdk/application/wearable/fd272/nativeapp/nativeui/traing/src/TraingModel.cpp @@ -167,42 +167,42 @@ return; } //训练基本信息更新 - if (request->msgId == TOPIC_EVENT_ACTIVITY_UPDATE) { - act_result_t *cyweeInfo = new act_result_t(); - int rets = memcpy_s(cyweeInfo, sizeof(act_result_t), - (act_result_t *)request->data, request->len); - if (rets != EOK) { - delete cyweeInfo; // 处理内存分配失败的情况 - cyweeInfo = NULL; - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, - "memcpy_s act_result_t fail ret = %d", rets); - return; - } - TraingModel::GetInstance()->AnalysisData(cyweeInfo); - // 更新其他目标完成度 - TraingModel::GetInstance()->CheckSportTag(); - delete cyweeInfo; // 释放内存 - } - //训练额外信息 - if (request->msgId == TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE) { - act_ext_result_t *cyweeInfo_ext = new act_ext_result_t(); - int rets = memcpy_s(cyweeInfo_ext, sizeof(act_ext_result_t), - (act_ext_result_t *)request->data, request->len); - if (rets != EOK) { - delete cyweeInfo_ext; // 处理内存分配失败的情况 - cyweeInfo_ext = NULL; - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, - "memcpy_s act_ext_result_t fail ret = %d", rets); - return; - } - TraingModel::GetInstance()->AnalysisExtraData(cyweeInfo_ext); - delete cyweeInfo_ext; // 释放内存 - } - //训练心率 - if (request->msgId == TOPIC_EVENT_HEARTRATE_UPDATA) { - uint8_t heart = *((u_int8_t *)(request->data)); // 进行类型转换 - TraingModel::GetInstance()->AnalysisHeartData(heart); - } + // if (request->msgId == TOPIC_EVENT_ACTIVITY_UPDATE) { + // act_result_t *cyweeInfo = new act_result_t(); + // int rets = memcpy_s(cyweeInfo, sizeof(act_result_t), + // (act_result_t *)request->data, request->len); + // if (rets != EOK) { + // delete cyweeInfo; // 处理内存分配失败的情况 + // cyweeInfo = NULL; + // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, + // "memcpy_s act_result_t fail ret = %d", rets); + // return; + // } + // TraingModel::GetInstance()->AnalysisData(cyweeInfo); + // // 更新其他目标完成度 + // TraingModel::GetInstance()->CheckSportTag(); + // delete cyweeInfo; // 释放内存 + // } + // //训练额外信息 + // if (request->msgId == TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE) { + // act_ext_result_t *cyweeInfo_ext = new act_ext_result_t(); + // int rets = memcpy_s(cyweeInfo_ext, sizeof(act_ext_result_t), + // (act_ext_result_t *)request->data, request->len); + // if (rets != EOK) { + // delete cyweeInfo_ext; // 处理内存分配失败的情况 + // cyweeInfo_ext = NULL; + // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, + // "memcpy_s act_ext_result_t fail ret = %d", rets); + // return; + // } + // TraingModel::GetInstance()->AnalysisExtraData(cyweeInfo_ext); + // delete cyweeInfo_ext; // 释放内存 + // } + // //训练心率 + // if (request->msgId == TOPIC_EVENT_HEARTRATE_UPDATA) { + // uint8_t heart = *((u_int8_t *)(request->data)); // 进行类型转换 + // TraingModel::GetInstance()->AnalysisHeartData(heart); + // } #endif } #ifdef __cplusplus diff --git a/code/sdk/application/wearable/fd272/service/broadcast/include/broadcast_feature.h b/code/sdk/application/wearable/fd272/service/broadcast/include/broadcast_feature.h index ce6030c7b..42f1f9241 100644 --- a/code/sdk/application/wearable/fd272/service/broadcast/include/broadcast_feature.h +++ b/code/sdk/application/wearable/fd272/service/broadcast/include/broadcast_feature.h @@ -51,16 +51,16 @@ typedef enum { TOPIC_EVENT_SPORT_DISTANCE, TOPIC_EVENT_LOCATION, TOPIC_EVENT_HFP_HINT, -// #ifdef SUPPORT_CYWEE_SERVICE - TOPIC_EVENT_ACTIVITY_UPDATE, - TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, +#ifdef SUPPORT_CYWEE_SERVICE + // TOPIC_EVENT_ACTIVITY_UPDATE, + // TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, TOPIC_EVENT_AR_ALERT_TYPE_UPDATE, TOPIC_EVENT_INACTIVITY_UPDATE, - TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, + // TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, +#endif TOPIC_EVENT_BLE_TRAINING, TOPIC_EVENT_BLE_TRANSMIT, TOPIC_EVENT_GOAL_SHOW_VIEW, -// #endif TOPIC_EVENT_CHARGE_PLUG, TOPIC_EVENT_CHARGE_UNPLUG, TOPIC_EVENT_LOWPOWER_ALARM, diff --git a/code/sdk/application/wearable/fd272/service/broadcast/src/broadcast_implement.c b/code/sdk/application/wearable/fd272/service/broadcast/src/broadcast_implement.c index 970db0274..b9ee08e45 100644 --- a/code/sdk/application/wearable/fd272/service/broadcast/src/broadcast_implement.c +++ b/code/sdk/application/wearable/fd272/service/broadcast/src/broadcast_implement.c @@ -30,14 +30,14 @@ static const TopicToCore topicToCoreArray[] = { {TOPIC_EVENT_STATIC_HEARTRATE_UPDATA, A_CORE_MASK, 1}, {TOPIC_EVENT_BLE_TRANSMIT,A_CORE_MASK,1}, {TOPIC_EVENT_BLE_TRAINING,A_CORE_MASK,1}, -#ifdef CYWEE_SPORT - {TOPIC_EVENT_ACTIVITY_UPDATE, A_CORE_MASK, 1}, - {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, A_CORE_MASK, 1}, +#ifdef SUPPORT_CYWEE_SERVICE + // {TOPIC_EVENT_ACTIVITY_UPDATE, A_CORE_MASK, 1}, + // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, A_CORE_MASK, 1}, {TOPIC_EVENT_AR_ALERT_TYPE_UPDATE, A_CORE_MASK, 1}, {TOPIC_EVENT_INACTIVITY_UPDATE, A_CORE_MASK, 1}, - {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, A_CORE_MASK, 1}, - {TOPIC_EVENT_GOAL_SHOW_VIEW,A_CORE_MASK,1}, + // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, A_CORE_MASK, 1}, #endif + {TOPIC_EVENT_GOAL_SHOW_VIEW,A_CORE_MASK,1}, #ifdef SUPPORT_SPO2_NOTIFICATION {TOPIC_EVENT_SPO2_UPDATE, A_CORE_MASK, 1}, {TOPIC_EVENT_START_HRS_MONITORING, A_CORE_MASK, 1}, diff --git a/code/sdk/application/wearable/fd272/service/msg_center/src/msg_center_customer.cpp b/code/sdk/application/wearable/fd272/service/msg_center/src/msg_center_customer.cpp index 5ece3e42d..9f602a2ab 100644 --- a/code/sdk/application/wearable/fd272/service/msg_center/src/msg_center_customer.cpp +++ b/code/sdk/application/wearable/fd272/service/msg_center/src/msg_center_customer.cpp @@ -115,16 +115,16 @@ const PriorityMapper PRI_MAPPER[] = { #endif {TOPIC_EVENT_ON_TIME,PRIORITY_TWO}, -#if 0 - {TOPIC_EVENT_ACTIVITY_UPDATE,PRIORITY_TWO}, - {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,PRIORITY_TWO}, +#ifdef SUPPORT_CYWEE_SERVICE + // {TOPIC_EVENT_ACTIVITY_UPDATE,PRIORITY_TWO}, + // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,PRIORITY_TWO}, {TOPIC_EVENT_AR_ALERT_TYPE_UPDATE,PRIORITY_TWO}, - {TOPIC_EVENT_STEPDATA_UPDATE,PRIORITY_TWO}, + // {TOPIC_EVENT_STEPDATA_UPDATE,PRIORITY_TWO}, {TOPIC_EVENT_INACTIVITY_UPDATE,PRIORITY_TWO}, - {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,PRIORITY_TWO}, - {TOPIC_EVENT_GOAL_SHOW_VIEW,PRIORITY_TWO}, -#endif + // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,PRIORITY_TWO} +#endif + {TOPIC_EVENT_GOAL_SHOW_VIEW,PRIORITY_TWO}, {TOPIC_EVENT_BLE_TRAINING,PRIORITY_TWO}, {TOPIC_EVENT_BLE_TRANSMIT,PRIORITY_ONE}, @@ -175,11 +175,11 @@ void MsgCenterSubscribe() MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_PHONE_TO_WATCH); MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_WATCH_TO_PHONE); MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_HINT); - MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_UPDATE); - MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE); + // MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_UPDATE); + // MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE); MsgCenterSubscribeTopic(TOPIC_EVENT_AR_ALERT_TYPE_UPDATE); MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_UPDATE); - MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE); + // MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE); MsgCenterSubscribeTopic(TOPIC_EVENT_BLE_TRAINING); MsgCenterSubscribeTopic(TOPIC_EVENT_BLE_TRANSMIT); MsgCenterSubscribeTopic(TOPIC_EVENT_GOAL_SHOW_VIEW); @@ -1151,91 +1151,96 @@ void MsgCenterNotifyCat1FailEProc(const Topic topic, Request* req) } - //每日训练数据刷新 - void MsgCenterNotifyActivityProc(const Topic topic, Request* req) - { - unused(topic); - cywee_activity_result_t* c_activity_result_t = (cywee_activity_result_t *) malloc(req->len); - if(c_activity_result_t==NULL) - { - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure"); - return; - } - int rets = memcpy_s(c_activity_result_t, req->len, (cywee_activity_result_t*)req->data, req->len); - if (rets != EOK) - { - free(c_activity_result_t); - c_activity_result_t = NULL; - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_t failed, ret = %d", rets); - return; - } - if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_NORMAL) - { - /*更新卡路里数据*/ - //if(c_activity_result_t->calories!=0) - { - set_calories_data(c_activity_result_t->calories); - #if DIALDATASET - uint32_t calories= OHOS::GoalModel::GetInstance().show_data_calories_refresh(); +#endif + +#ifdef SUPPORT_CYWEE_SERVICE + +// //每日训练数据刷新 +// void MsgCenterNotifyActivityProc(const Topic topic, Request* req) +// { +// unused(topic); +// cywee_activity_result_t* c_activity_result_t = (cywee_activity_result_t *) malloc(req->len); +// if(c_activity_result_t==NULL) +// { +// WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure"); +// return; +// } + +// int rets = memcpy_s(c_activity_result_t, req->len, (cywee_activity_result_t*)req->data, req->len); +// if (rets != EOK) +// { +// free(c_activity_result_t); +// c_activity_result_t = NULL; +// WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_t failed, ret = %d", rets); +// return; +// } +// if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_NORMAL) +// { +// /*更新卡路里数据*/ +// //if(c_activity_result_t->calories!=0) +// { +// set_calories_data(c_activity_result_t->calories); +// #if DIALDATASET +// uint32_t calories= OHOS::GoalModel::GetInstance().show_data_calories_refresh(); - DialModelCalorie::GetInstance()->UpdateCalorie(calories); - #endif - } - /*更新距离数据*/ - //if(c_activity_result_t->distance != 0) - { - set_distance_data(c_activity_result_t->distance); - #if DIALDATASET - float distance= OHOS::GoalModel::GetInstance().show_data_distance_refresh(); - DialModelDistance::GetInstance()->UpdateDistance(distance); - #endif - } - } - else if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_FREE_TRAINING && c_activity_result_t->MHR_zone >= 2) - { - /*更新燃脂时间数据*/ - set_fat_time_data(1); - } +// DialModelCalorie::GetInstance()->UpdateCalorie(calories); +// #endif +// } +// /*更新距离数据*/ +// //if(c_activity_result_t->distance != 0) +// { +// set_distance_data(c_activity_result_t->distance); +// #if DIALDATASET +// float distance= OHOS::GoalModel::GetInstance().show_data_distance_refresh(); +// DialModelDistance::GetInstance()->UpdateDistance(distance); +// #endif +// } +// } +// else if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_FREE_TRAINING && c_activity_result_t->MHR_zone >= 2) +// { +// /*更新燃脂时间数据*/ +// set_fat_time_data(1); +// } - free(c_activity_result_t); - c_activity_result_t = NULL; - } - static int train_fat_time = 0; - void MsgCenterNotifyActivityExtraInfoProc(const Topic topic, Request* req) - { - unused(topic); - cywee_activity_result_extre_info_t* c_activity_result_extre_info_t = (cywee_activity_result_extre_info_t *) malloc(req->len); - if(c_activity_result_extre_info_t==NULL) - { - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure"); - return; - } - - int rets = memcpy_s(c_activity_result_extre_info_t, req->len, (cywee_activity_result_extre_info_t*)req->data, req->len); - if (rets != EOK) - { - free(c_activity_result_extre_info_t); - c_activity_result_extre_info_t = NULL; - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_extre_info_t failed, ret = %d", rets); - return; - } - - if(uapi_dev_runtime_get_train_status() && c_activity_result_extre_info_t->ativity_zone_high_duration) - { - train_fat_time = c_activity_result_extre_info_t->ativity_zone_high_duration; - } - /*更新燃脂时间数据*/ - else if(uapi_dev_runtime_get_train_status() == 0 && train_fat_time) - { - set_fat_time_data(train_fat_time); - train_fat_time = 0; - } +// free(c_activity_result_t); +// c_activity_result_t = NULL; +// } +// static int train_fat_time = 0; +// void MsgCenterNotifyActivityExtraInfoProc(const Topic topic, Request* req) +// { +// unused(topic); +// cywee_activity_result_extre_info_t* c_activity_result_extre_info_t = (cywee_activity_result_extre_info_t *) malloc(req->len); +// if(c_activity_result_extre_info_t==NULL) +// { +// WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure"); +// return; +// } + +// int rets = memcpy_s(c_activity_result_extre_info_t, req->len, (cywee_activity_result_extre_info_t*)req->data, req->len); +// if (rets != EOK) +// { +// free(c_activity_result_extre_info_t); +// c_activity_result_extre_info_t = NULL; +// WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_extre_info_t failed, ret = %d", rets); +// return; +// } + +// if(uapi_dev_runtime_get_train_status() && c_activity_result_extre_info_t->ativity_zone_high_duration) +// { +// train_fat_time = c_activity_result_extre_info_t->ativity_zone_high_duration; +// } +// /*更新燃脂时间数据*/ +// else if(uapi_dev_runtime_get_train_status() == 0 && train_fat_time) +// { +// set_fat_time_data(train_fat_time); +// train_fat_time = 0; +// } + +// free(c_activity_result_extre_info_t); +// c_activity_result_extre_info_t = NULL; +// } - free(c_activity_result_extre_info_t); - c_activity_result_extre_info_t = NULL; - } -#endif /*运动识别*/ void MsgCenterNotifyArAlertProc(const Topic topic, Request* req) { @@ -1258,7 +1263,6 @@ void MsgCenterNotifyArAlertProc(const Topic topic, Request* req) void MsgCenterNotifyInactivityProc(const Topic topic, Request *req) { WEARABLE_LOGI(WEARABLE_LOG_MODULE_APP, "MsgCenterNotifyInactivityProc !"); -#ifdef SUPPORT_CYWEE_SERVICE inact_result_t *cywee_Inactivity_Info = (inact_result_t *)malloc(req->len); if (!cywee_Inactivity_Info) { @@ -1300,9 +1304,10 @@ void MsgCenterNotifyInactivityProc(const Topic topic, Request *req) free(cywee_Inactivity_Info); cywee_Inactivity_Info = NULL; -#endif } +#endif + //查找手表通知 void MsgCenterNotifyFindWatchProc(const Topic topic, Request* req) { @@ -1534,15 +1539,16 @@ static MsgCenterNotifyTable g_msgCenterNotifyTable[] = { {TOPIC_EVENT_HFP_PHONE_TO_WATCH, MsgCenterNotifyHfpWatchProc}, {TOPIC_EVENT_HFP_HINT, MsgCenterNotifyHfpWatchHintProc}, -#if 0 - {TOPIC_EVENT_ACTIVITY_UPDATE, MsgCenterNotifyActivityProc}, - {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, MsgCenterNotifyActivityExtraInfoProc}, +#ifdef SUPPORT_CYWEE_SERVICE + // {TOPIC_EVENT_ACTIVITY_UPDATE, MsgCenterNotifyActivityProc}, + // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, MsgCenterNotifyActivityExtraInfoProc}, {TOPIC_EVENT_AR_ALERT_TYPE_UPDATE, MsgCenterNotifyArAlertProc}, {TOPIC_EVENT_INACTIVITY_UPDATE, MsgCenterNotifyInactivityProc}, - {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, MsgCenterNotifyInactivityAccumulateTimeProc}, - {TOPIC_EVENT_BLE_TRAINING, MsgCenterNotifybleAPPtraining}, - {TOPIC_EVENT_GOAL_SHOW_VIEW, MsgCenterNotifygoalnotificationviewProc}, + // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, MsgCenterNotifyInactivityAccumulateTimeProc}, #endif + {TOPIC_EVENT_BLE_TRAINING, MsgCenterNotifybleAPPtraining}, + // {TOPIC_EVENT_GOAL_SHOW_VIEW, MsgCenterNotifygoalnotificationviewProc},//编译不过 + {TOPIC_EVENT_BLE_TRANSMIT, MsgCenterNotifybleTransmit}, {TOPIC_EVENT_CHARGE_PLUG, MsgCenterNotifyChargePlugProc}, diff --git a/code/sdk/application/wearable/n9/nativeapp/nativeui/traing/src/TraingModel.cpp b/code/sdk/application/wearable/n9/nativeapp/nativeui/traing/src/TraingModel.cpp index 6b989104c..c755e30d5 100644 --- a/code/sdk/application/wearable/n9/nativeapp/nativeui/traing/src/TraingModel.cpp +++ b/code/sdk/application/wearable/n9/nativeapp/nativeui/traing/src/TraingModel.cpp @@ -167,42 +167,42 @@ return; } //训练基本信息更新 - if (request->msgId == TOPIC_EVENT_ACTIVITY_UPDATE) { - act_result_t *cyweeInfo = new act_result_t(); - int rets = memcpy_s(cyweeInfo, sizeof(act_result_t), - (act_result_t *)request->data, request->len); - if (rets != EOK) { - delete cyweeInfo; // 处理内存分配失败的情况 - cyweeInfo = NULL; - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, - "memcpy_s act_result_t fail ret = %d", rets); - return; - } - TraingModel::GetInstance()->AnalysisData(cyweeInfo); - // 更新其他目标完成度 - TraingModel::GetInstance()->CheckSportTag(); - delete cyweeInfo; // 释放内存 - } - //训练额外信息 - if (request->msgId == TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE) { - act_ext_result_t *cyweeInfo_ext = new act_ext_result_t(); - int rets = memcpy_s(cyweeInfo_ext, sizeof(act_ext_result_t), - (act_ext_result_t *)request->data, request->len); - if (rets != EOK) { - delete cyweeInfo_ext; // 处理内存分配失败的情况 - cyweeInfo_ext = NULL; - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, - "memcpy_s act_ext_result_t fail ret = %d", rets); - return; - } - TraingModel::GetInstance()->AnalysisExtraData(cyweeInfo_ext); - delete cyweeInfo_ext; // 释放内存 - } - //训练心率 - if (request->msgId == TOPIC_EVENT_HEARTRATE_UPDATA) { - uint8_t heart = *((u_int8_t *)(request->data)); // 进行类型转换 - TraingModel::GetInstance()->AnalysisHeartData(heart); - } + // if (request->msgId == TOPIC_EVENT_ACTIVITY_UPDATE) { + // act_result_t *cyweeInfo = new act_result_t(); + // int rets = memcpy_s(cyweeInfo, sizeof(act_result_t), + // (act_result_t *)request->data, request->len); + // if (rets != EOK) { + // delete cyweeInfo; // 处理内存分配失败的情况 + // cyweeInfo = NULL; + // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, + // "memcpy_s act_result_t fail ret = %d", rets); + // return; + // } + // TraingModel::GetInstance()->AnalysisData(cyweeInfo); + // // 更新其他目标完成度 + // TraingModel::GetInstance()->CheckSportTag(); + // delete cyweeInfo; // 释放内存 + // } + // //训练额外信息 + // if (request->msgId == TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE) { + // act_ext_result_t *cyweeInfo_ext = new act_ext_result_t(); + // int rets = memcpy_s(cyweeInfo_ext, sizeof(act_ext_result_t), + // (act_ext_result_t *)request->data, request->len); + // if (rets != EOK) { + // delete cyweeInfo_ext; // 处理内存分配失败的情况 + // cyweeInfo_ext = NULL; + // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, + // "memcpy_s act_ext_result_t fail ret = %d", rets); + // return; + // } + // TraingModel::GetInstance()->AnalysisExtraData(cyweeInfo_ext); + // delete cyweeInfo_ext; // 释放内存 + // } + // //训练心率 + // if (request->msgId == TOPIC_EVENT_HEARTRATE_UPDATA) { + // uint8_t heart = *((u_int8_t *)(request->data)); // 进行类型转换 + // TraingModel::GetInstance()->AnalysisHeartData(heart); + // } #endif } #ifdef __cplusplus diff --git a/code/sdk/application/wearable/n9/service/broadcast/include/broadcast_feature.h b/code/sdk/application/wearable/n9/service/broadcast/include/broadcast_feature.h index ce6030c7b..42f1f9241 100644 --- a/code/sdk/application/wearable/n9/service/broadcast/include/broadcast_feature.h +++ b/code/sdk/application/wearable/n9/service/broadcast/include/broadcast_feature.h @@ -51,16 +51,16 @@ typedef enum { TOPIC_EVENT_SPORT_DISTANCE, TOPIC_EVENT_LOCATION, TOPIC_EVENT_HFP_HINT, -// #ifdef SUPPORT_CYWEE_SERVICE - TOPIC_EVENT_ACTIVITY_UPDATE, - TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, +#ifdef SUPPORT_CYWEE_SERVICE + // TOPIC_EVENT_ACTIVITY_UPDATE, + // TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, TOPIC_EVENT_AR_ALERT_TYPE_UPDATE, TOPIC_EVENT_INACTIVITY_UPDATE, - TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, + // TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, +#endif TOPIC_EVENT_BLE_TRAINING, TOPIC_EVENT_BLE_TRANSMIT, TOPIC_EVENT_GOAL_SHOW_VIEW, -// #endif TOPIC_EVENT_CHARGE_PLUG, TOPIC_EVENT_CHARGE_UNPLUG, TOPIC_EVENT_LOWPOWER_ALARM, diff --git a/code/sdk/application/wearable/n9/service/broadcast/src/broadcast_implement.c b/code/sdk/application/wearable/n9/service/broadcast/src/broadcast_implement.c index b7f5254e5..5ec2a32f4 100644 --- a/code/sdk/application/wearable/n9/service/broadcast/src/broadcast_implement.c +++ b/code/sdk/application/wearable/n9/service/broadcast/src/broadcast_implement.c @@ -30,14 +30,14 @@ static const TopicToCore topicToCoreArray[] = { {TOPIC_EVENT_STATIC_HEARTRATE_UPDATA, A_CORE_MASK, 1}, {TOPIC_EVENT_BLE_TRAINING,A_CORE_MASK,1}, {TOPIC_EVENT_BLE_TRANSMIT,A_CORE_MASK,1}, -#ifdef CYWEE_SPORT - {TOPIC_EVENT_ACTIVITY_UPDATE, A_CORE_MASK, 1}, - {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, A_CORE_MASK, 1}, +#ifdef SUPPORT_CYWEE_SERVICE + // {TOPIC_EVENT_ACTIVITY_UPDATE, A_CORE_MASK, 1}, + // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, A_CORE_MASK, 1}, {TOPIC_EVENT_AR_ALERT_TYPE_UPDATE, A_CORE_MASK, 1}, {TOPIC_EVENT_INACTIVITY_UPDATE, A_CORE_MASK, 1}, - {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, A_CORE_MASK, 1}, - {TOPIC_EVENT_GOAL_SHOW_VIEW,A_CORE_MASK,1}, + // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, A_CORE_MASK, 1}, #endif + {TOPIC_EVENT_GOAL_SHOW_VIEW,A_CORE_MASK,1}, #ifdef SUPPORT_SPO2_NOTIFICATION {TOPIC_EVENT_SPO2_UPDATE, A_CORE_MASK, 1}, {TOPIC_EVENT_START_HRS_MONITORING, A_CORE_MASK, 1}, diff --git a/code/sdk/application/wearable/n9/service/msg_center/src/msg_center_customer.cpp b/code/sdk/application/wearable/n9/service/msg_center/src/msg_center_customer.cpp index 4ddd2466f..a95b72a25 100644 --- a/code/sdk/application/wearable/n9/service/msg_center/src/msg_center_customer.cpp +++ b/code/sdk/application/wearable/n9/service/msg_center/src/msg_center_customer.cpp @@ -115,16 +115,15 @@ const PriorityMapper PRI_MAPPER[] = { #endif {TOPIC_EVENT_ON_TIME,PRIORITY_TWO}, -#if 0 - {TOPIC_EVENT_ACTIVITY_UPDATE,PRIORITY_TWO}, - {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,PRIORITY_TWO}, +#ifdef SUPPORT_CYWEE_SERVICE + // {TOPIC_EVENT_ACTIVITY_UPDATE,PRIORITY_TWO}, + // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE,PRIORITY_TWO}, {TOPIC_EVENT_AR_ALERT_TYPE_UPDATE,PRIORITY_TWO}, - {TOPIC_EVENT_STEPDATA_UPDATE,PRIORITY_TWO}, + // {TOPIC_EVENT_STEPDATA_UPDATE,PRIORITY_TWO}, {TOPIC_EVENT_INACTIVITY_UPDATE,PRIORITY_TWO}, - {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,PRIORITY_TWO}, - {TOPIC_EVENT_GOAL_SHOW_VIEW,PRIORITY_TWO}, + // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE,PRIORITY_TWO}, #endif - + {TOPIC_EVENT_GOAL_SHOW_VIEW,PRIORITY_TWO}, {TOPIC_EVENT_BLE_TRAINING,PRIORITY_TWO}, {TOPIC_EVENT_BLE_TRANSMIT,PRIORITY_ONE}, @@ -175,11 +174,11 @@ void MsgCenterSubscribe() MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_PHONE_TO_WATCH); MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_WATCH_TO_PHONE); MsgCenterSubscribeTopic(TOPIC_EVENT_HFP_HINT); - MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_UPDATE); - MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE); + // MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_UPDATE); + // MsgCenterSubscribeTopic(TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE); MsgCenterSubscribeTopic(TOPIC_EVENT_AR_ALERT_TYPE_UPDATE); - MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_UPDATE); - MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE); + // MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_UPDATE); + // MsgCenterSubscribeTopic(TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE); MsgCenterSubscribeTopic(TOPIC_EVENT_BLE_TRAINING); MsgCenterSubscribeTopic(TOPIC_EVENT_BLE_TRANSMIT); MsgCenterSubscribeTopic(TOPIC_EVENT_GOAL_SHOW_VIEW); @@ -1013,7 +1012,7 @@ void MsgCenterNotifyCat1FailEProc(const Topic topic, Request* req) -#if 0 +#if 0 //编译不过 //每日活动 void MsgCenterNotifygoalnotificationviewProc(const Topic topic, Request* req) { @@ -1148,94 +1147,98 @@ void MsgCenterNotifyCat1FailEProc(const Topic topic, Request* req) #endif } + } +#endif - } - //每日训练数据刷新 - void MsgCenterNotifyActivityProc(const Topic topic, Request* req) - { - unused(topic); - cywee_activity_result_t* c_activity_result_t = (cywee_activity_result_t *) malloc(req->len); - if(c_activity_result_t==NULL) - { - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure"); - return; - } +#ifdef SUPPORT_CYWEE_SERVICE - int rets = memcpy_s(c_activity_result_t, req->len, (cywee_activity_result_t*)req->data, req->len); - if (rets != EOK) - { - free(c_activity_result_t); - c_activity_result_t = NULL; - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_t failed, ret = %d", rets); - return; - } - if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_NORMAL) - { - /*更新卡路里数据*/ - //if(c_activity_result_t->calories!=0) - { - set_calories_data(c_activity_result_t->calories); - #if DIALDATASET - uint32_t calories= OHOS::GoalModel::GetInstance().show_data_calories_refresh(); + // //每日训练数据刷新 + // void MsgCenterNotifyActivityProc(const Topic topic, Request* req) + // { + // unused(topic); + // cywee_activity_result_t* c_activity_result_t = (cywee_activity_result_t *) malloc(req->len); + // if(c_activity_result_t==NULL) + // { + // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure"); + // return; + // } + + // int rets = memcpy_s(c_activity_result_t, req->len, (cywee_activity_result_t*)req->data, req->len); + // if (rets != EOK) + // { + // free(c_activity_result_t); + // c_activity_result_t = NULL; + // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_t failed, ret = %d", rets); + // return; + // } + // if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_NORMAL) + // { + // /*更新卡路里数据*/ + // //if(c_activity_result_t->calories!=0) + // { + // set_calories_data(c_activity_result_t->calories); + // #if DIALDATASET + // uint32_t calories= OHOS::GoalModel::GetInstance().show_data_calories_refresh(); - DialModelCalorie::GetInstance()->UpdateCalorie(calories); - #endif - } - /*更新距离数据*/ - //if(c_activity_result_t->distance != 0) - { - set_distance_data(c_activity_result_t->distance); - #if DIALDATASET - float distance= OHOS::GoalModel::GetInstance().show_data_distance_refresh(); - DialModelDistance::GetInstance()->UpdateDistance(distance); - #endif - } - } - else if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_FREE_TRAINING && c_activity_result_t->MHR_zone >= 2) - { - /*更新燃脂时间数据*/ - set_fat_time_data(1); - } + // DialModelCalorie::GetInstance()->UpdateCalorie(calories); + // #endif + // } + // /*更新距离数据*/ + // //if(c_activity_result_t->distance != 0) + // { + // set_distance_data(c_activity_result_t->distance); + // #if DIALDATASET + // float distance= OHOS::GoalModel::GetInstance().show_data_distance_refresh(); + // DialModelDistance::GetInstance()->UpdateDistance(distance); + // #endif + // } + // } + // else if(c_activity_result_t->activity_mode == SPORT_ACTIVE_MODE_FREE_TRAINING && c_activity_result_t->MHR_zone >= 2) + // { + // /*更新燃脂时间数据*/ + // set_fat_time_data(1); + // } - free(c_activity_result_t); - c_activity_result_t = NULL; - } - static int train_fat_time = 0; - void MsgCenterNotifyActivityExtraInfoProc(const Topic topic, Request* req) - { - unused(topic); - cywee_activity_result_extre_info_t* c_activity_result_extre_info_t = (cywee_activity_result_extre_info_t *) malloc(req->len); - if(c_activity_result_extre_info_t==NULL) - { - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure"); - return; - } - - int rets = memcpy_s(c_activity_result_extre_info_t, req->len, (cywee_activity_result_extre_info_t*)req->data, req->len); - if (rets != EOK) - { - free(c_activity_result_extre_info_t); - c_activity_result_extre_info_t = NULL; - WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_extre_info_t failed, ret = %d", rets); - return; - } + // free(c_activity_result_t); + // c_activity_result_t = NULL; + // } - if(uapi_dev_runtime_get_train_status() && c_activity_result_extre_info_t->ativity_zone_high_duration) - { - train_fat_time = c_activity_result_extre_info_t->ativity_zone_high_duration; - } - /*更新燃脂时间数据*/ - else if(uapi_dev_runtime_get_train_status() == 0 && train_fat_time) - { - set_fat_time_data(train_fat_time); - train_fat_time = 0; - } + // static int train_fat_time = 0; + // void MsgCenterNotifyActivityExtraInfoProc(const Topic topic, Request* req) + // { + // unused(topic); + // cywee_activity_result_extre_info_t* c_activity_result_extre_info_t = (cywee_activity_result_extre_info_t *) malloc(req->len); + // if(c_activity_result_extre_info_t==NULL) + // { + // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "Memory allocation failure"); + // return; + // } + + // int rets = memcpy_s(c_activity_result_extre_info_t, req->len, (cywee_activity_result_extre_info_t*)req->data, req->len); + // if (rets != EOK) + // { + // free(c_activity_result_extre_info_t); + // c_activity_result_extre_info_t = NULL; + // WEARABLE_LOGE(WEARABLE_LOG_MODULE_APP, "memcpy_s c_activity_result_extre_info_t failed, ret = %d", rets); + // return; + // } + + // if(uapi_dev_runtime_get_train_status() && c_activity_result_extre_info_t->ativity_zone_high_duration) + // { + // train_fat_time = c_activity_result_extre_info_t->ativity_zone_high_duration; + // } + // /*更新燃脂时间数据*/ + // else if(uapi_dev_runtime_get_train_status() == 0 && train_fat_time) + // { + // set_fat_time_data(train_fat_time); + // train_fat_time = 0; + // } + + // free(c_activity_result_extre_info_t); + // c_activity_result_extre_info_t = NULL; + // } - free(c_activity_result_extre_info_t); - c_activity_result_extre_info_t = NULL; - } -#endif /*运动识别*/ void MsgCenterNotifyArAlertProc(const Topic topic, Request* req) { @@ -1258,7 +1261,7 @@ void MsgCenterNotifyArAlertProc(const Topic topic, Request* req) void MsgCenterNotifyInactivityProc(const Topic topic, Request *req) { WEARABLE_LOGI(WEARABLE_LOG_MODULE_APP, "MsgCenterNotifyInactivityProc !"); -#ifdef SUPPORT_CYWEE_SERVICE + inact_result_t *cywee_Inactivity_Info = (inact_result_t *)malloc(req->len); if (!cywee_Inactivity_Info) { @@ -1300,9 +1303,10 @@ void MsgCenterNotifyInactivityProc(const Topic topic, Request *req) free(cywee_Inactivity_Info); cywee_Inactivity_Info = NULL; -#endif } +#endif + //查找手表通知 void MsgCenterNotifyFindWatchProc(const Topic topic, Request* req) { @@ -1534,14 +1538,16 @@ static MsgCenterNotifyTable g_msgCenterNotifyTable[] = { {TOPIC_EVENT_HFP_PHONE_TO_WATCH, MsgCenterNotifyHfpWatchProc}, {TOPIC_EVENT_HFP_HINT, MsgCenterNotifyHfpWatchHintProc}, -#if 0 - {TOPIC_EVENT_ACTIVITY_UPDATE, MsgCenterNotifyActivityProc}, - {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, MsgCenterNotifyActivityExtraInfoProc}, +#ifdef SUPPORT_CYWEE_SERVICE + // {TOPIC_EVENT_ACTIVITY_UPDATE, MsgCenterNotifyActivityProc}, + // {TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, MsgCenterNotifyActivityExtraInfoProc}, {TOPIC_EVENT_AR_ALERT_TYPE_UPDATE, MsgCenterNotifyArAlertProc}, {TOPIC_EVENT_INACTIVITY_UPDATE, MsgCenterNotifyInactivityProc}, - {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, MsgCenterNotifyInactivityAccumulateTimeProc}, - {TOPIC_EVENT_GOAL_SHOW_VIEW, MsgCenterNotifygoalnotificationviewProc}, + // {TOPIC_EVENT_INACTIVITY_ACCUMULATE_TIME_UPDATE, MsgCenterNotifyInactivityAccumulateTimeProc}, #endif + + // {TOPIC_EVENT_GOAL_SHOW_VIEW, MsgCenterNotifygoalnotificationviewProc}, //编译不过 + {TOPIC_EVENT_BLE_TRAINING, MsgCenterNotifybleAPPtraining}, {TOPIC_EVENT_BLE_TRANSMIT, MsgCenterNotifybleTransmit}, diff --git a/code/sdk/zhihui/drivers/cywee/dml/cywee_dml.c b/code/sdk/zhihui/drivers/cywee/dml/cywee_dml.c index b9a419d2d..8ad600027 100644 --- a/code/sdk/zhihui/drivers/cywee/dml/cywee_dml.c +++ b/code/sdk/zhihui/drivers/cywee/dml/cywee_dml.c @@ -67,6 +67,37 @@ static int new_fat=0; //存燃脂数据 static int history_fat=0; //历史数据 static int history_fat_=0; //一小时前燃脂数据 +// 燃脂时间计算相关变量 +static uint32_t last_fat_burn_timestamp = 0; // 上次燃脂状态更新的时间戳 +static int last_mhr_zone = -1; // 上次的心率区间状态 + +/** + * @brief 更新燃脂时间 + * @param current_mhr_zone 当前心率区间 (2表示燃脂区间) + */ +static void update_fat_burn_time(int current_mhr_zone) +{ + uint32_t current_timestamp = 0; + uapi_get_timestampe_ss(¤t_timestamp); + + // 如果上次时间戳有效且上次是燃脂状态 + if (last_fat_burn_timestamp > 0 && last_mhr_zone == 2) { + // 计算时间差 (秒) + uint32_t time_diff = current_timestamp - last_fat_burn_timestamp; + + // 防止异常时间跳跃 (超过10分钟认为异常) + if (time_diff > 0 && time_diff <= 600) { + new_fat += time_diff; + CWM_OS_dbgPrintf("Fat burn time updated: +%d seconds, total: %d seconds\n", + time_diff, new_fat); + } + } + + // 更新状态 + last_fat_burn_timestamp = current_timestamp; + last_mhr_zone = current_mhr_zone; +} + static char chipInfo[64] = {0}; static int sedentary_interval = 1; @@ -978,6 +1009,10 @@ void cywee_reset_history_daily_data(void) history_distances=0; history_fat=0; // new_fat = 0; //当前燃脂数据 + + // 重置燃脂时间计算相关状态 + last_fat_burn_timestamp = 0; + last_mhr_zone = -1; } void cywee_reset_daily_data(void) @@ -1587,6 +1622,9 @@ void CWM_AP_SensorListen(pSensorEVT_t sensorEVT) { c_act_ext_result_t.MHR_zone = (int)sensorEVT->fData[13]; c_act_ext_result_t.distance_motion = (int)sensorEVT->fData[14]; + // 燃脂时间计算：当MHR_zone = 2时表示燃脂状态 + update_fat_burn_time(c_act_ext_result_t.MHR_zone); + // cywee_func(CYWEE_MSG_TYPE_ACTIVITY_EXTRA_INFO_UPDATE,&c_act_ext_result_t,sizeof(act_ext_result_t)); //CustomEventPublish(TOPIC_EVENT_ACTIVITY_EXTRA_INFO_UPDATE, &c_act_ext_result_t, sizeof(act_ext_result_t)); // CWM_OS_dbgPrintf("PAH:avg_step_freq[%d], avg_step_len[%f],avg_pace[%d], max_step_freq[%d], max_pace[%d]\n", @@ -1601,6 +1639,10 @@ void CWM_AP_SensorListen(pSensorEVT_t sensorEVT) { c_act_result_t.calories = (int)sensorEVT->fData[1]; c_act_result_t.duration = (int)sensorEVT->fData[5]; c_act_result_t.MHR_zone = (int)sensorEVT->fData[6]; + + // 燃脂时间计算：当MHR_zone = 2时表示燃脂状态 + update_fat_burn_time(c_act_result_t.MHR_zone); + // c_act_result_t.hrs = hrs; // hrs = 0; //每次上报完 清除心率值 // cywee_func(CYWEE_MSG_TYPE_ACTIVITY_UPDATE,&c_act_result_t,sizeof(act_result_t)); diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/CMakeLists.txt b/code/sdk/zhihui/drivers/ppg/hx3695/CMakeLists.txt index 243189e8d..53bbac26b 100644 --- a/code/sdk/zhihui/drivers/ppg/hx3695/CMakeLists.txt +++ b/code/sdk/zhihui/drivers/ppg/hx3695/CMakeLists.txt @@ -7,13 +7,15 @@ set(COMPONENT_NAME "ppg_sensor_hx3695") if("PPG_HX3695" IN_LIST DEFINES) set(SOURCES ${SOURCES} ${CMAKE_CURRENT_SOURCE_DIR}/hx3695.c - ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_check_touch.c + # ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_check_touch.c ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_factory_test.c - ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_hrs_agc.c - ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_hrv_agc.c - ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_spo2_agc.c + # ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_hrs_agc.c + # ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_hrv_agc.c + # ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_spo2_agc.c #${CMAKE_CURRENT_SOURCE_DIR}/hx3695_hal.c ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_hrs_custom.c + ${CMAKE_CURRENT_SOURCE_DIR}/hx3695_agc.c + ) set(PUBLIC_HEADER ${CMAKE_CURRENT_SOURCE_DIR} @@ -55,7 +57,16 @@ set(MAIN_COMPONENT if("PPG_HX3695" IN_LIST DEFINES) find_library(LIB_PATH_HX3695 libhx3695.a ${CMAKE_CURRENT_SOURCE_DIR}) - target_link_libraries(${TARGET_NAME} PRIVATE -Wl,--whole-archive ${LIB_PATH_HX3695} PRIVATE -Wl,--whole-archive) + find_library(LIB_PATH_HX3695_HRV libHX3697_hs_20241230_103__01_hrv.a ${CMAKE_CURRENT_SOURCE_DIR}) + find_library(LIB_PATH_HX3695_HRS libHX3697_hs_20241230_3153__01_hrs.a ${CMAKE_CURRENT_SOURCE_DIR}) + find_library(LIB_PATH_HX3695_SPO libHX3697_hs_20240607_3333__02_spo.a ${CMAKE_CURRENT_SOURCE_DIR}) + + target_link_libraries(${TARGET_NAME} PRIVATE -Wl,--whole-archive + # ${LIB_PATH_HX3695} + ${LIB_PATH_HX3695_HRV} + ${LIB_PATH_HX3695_HRS} + ${LIB_PATH_HX3695_SPO} + PRIVATE -Wl,--whole-archive) endif() build_component() diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695.c b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695.c index f166ffbf5..03fd50a30 100644 --- a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695.c +++ b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695.c @@ -5,32 +5,28 @@ #include #include "tyhx_hrs_custom.h" -//#include "tyhx_mems.h" - -#ifdef CHIP_HX3695 #include "hx3695.h" -#ifdef HRS_ALG_LIB -#include "hx3695_hrs_agc.h" +#ifdef TYHX_DEMO +#include "demo_ctrl.h" +#include "twi_master.h" +#include "SEGGER_RTT.h" +#include "app_timer.h" +#include "nrf_delay.h" +#include "nrf_gpio.h" +#include "nrf_drv_gpiote.h" +#include "drv_oled.h" +#include "opr_oled.h" + +#include "oled_iic.h" +#include "word.h" +#include "iic.h" +#endif +#include "hx3695_agc.h" #include "tyhx_hrs_alg.h" -#endif -#ifdef SPO2_ALG_LIB -#include "hx3695_spo2_agc.h" -#include "tyhx_spo2_alg.h" -#endif -#ifdef HRV_ALG_LIB -#include "hx3695_hrv_agc.h" #include "tyhx_hrv_alg.h" -#endif -#ifdef CHECK_TOUCH_LIB -#include "hx3695_check_touch.h" -#endif +#include "tyhx_spo2_alg.h" #include "hx3695_factory_test.h" -//#include "app_ble_factory_test.h" -// #include "ui.h" -// #include "app_heart_rate.h" -// #include "lv_dev.h" -// #include "app_task.h" #ifdef SUPPORT_CYWEE_SERVICE #include "cywee_hal.h" @@ -41,140 +37,63 @@ #include "ppg_hal.h" +uint8_t read_fifo_first_flg = 0; +uint8_t s_ppg_state = 0; +uint8_t s_cal_state = 0; +uint8_t check_touch_cnt = 0; +static wear_msg_code_t wear_status = MSG_NO_WEAR; +static wear_msg_code_t wear_status_pre = MSG_NO_INIT; +WORK_MODE_T work_mode_flag = HRS_MODE; +ppg_sensor_data_t ppg_sensor_data; +int16_t gsen_data_x_fifo[64]; +int16_t gsen_data_y_fifo[64]; +int16_t gsen_data_z_fifo[64]; -FT_CUSTOM_RESULTS_t hrsresult ={0}; - -int16_t gsen_fifo_x[64]={0}; -int16_t gsen_fifo_y[64]={0}; -int16_t gsen_fifo_z[64]={0}; - +static uint8_t hrs_ble_falg = 0; +// static int history_wear_status = -1; +static uint8_t wear_result = 0; +static uint8_t spo2_ret = 0; +static int32_t factory_data = 0; +static uint8_t hx3695_chip_id = 0; #ifdef SUPPORT_CYWEE_SERVICE -gsenson_t gsensordata[32]; +static gsenson_t gsensordata[32]; #endif +// static uint8_t his_wear = 2; +// static uint8_t wear_cnt = 0; -static uint8_t msg_count = 0; - -#ifdef SPO2_VECTOR -#include "spo2_vec.h" -uint32_t spo2_send_cnt = 0; -uint32_t spo2_send_cnt1 = 0; -int32_t red_buf_vec[8]; -int32_t ir_buf_vec[8]; -int32_t green_buf_vec[8]; -#endif +uint8_t alg_ram[11 * 1024] __attribute__((aligned(4))); -#ifdef HR_VECTOR -#include "hr_vec.h" -uint32_t vec_send_cnt = 0; -int32_t PPG_buf_vec[8]; -#endif -#ifdef HRV_TESTVEC -#include "hrv_testvec.h" -#endif -// #include "sys_init.h" -// #include "cwm_api.h" +//////// spo2 para and switches +const uint8_t COUNT_BLOCK_NUM = 25; // delay the block of some single good signal after a series of bad signal +const uint8_t SPO2_LOW_XCORR_THRE = 30; //(64*xcorr)'s square below this threshold, means error signal +const uint8_t SPO2_CALI = 1; // spo2_result cali mode +const uint8_t XCORR_MODE = 1; // xcorr mode switch +const uint8_t QUICK_RESULT = 1; // come out the spo2 result quickly ;0 is normal,1 is quick +const uint16_t MEAN_NUM = 32; // the length of smooth-average ;the value of MEAN_NUM can be given only 256 and 512 +const uint8_t G_SENSOR = 0; // if =1, open the gsensor mode +const uint8_t SPO2_GSEN_POW_THRE = 150; // gsen pow judge move, range:0-200; +const uint32_t SPO2_BASE_LINE_INIT = 153000; // spo2 baseline init, = 103000 + ratio(a variable quantity,depends on different cases)*SPO2_SLOPE +const int32_t SOP2_DEGLITCH_THRE = 100000; // remove signal glitch over this threshold +const int32_t SPO2_REMOVE_JUMP_THRE = 50000; // remove signal jump over this threshold +const uint32_t SPO2_SLOPE = 50000; // increase this slope, spo2 reduce more +const uint16_t SPO2_LOW_CLIP_END_TIME = 1500; // low clip mode before this data_cnt, normal clip mode after this +const uint16_t SPO2_LOW_CLIP_DN = 150; // spo2 reduce 0.15/s at most in low clip mode +const uint16_t SPO2_NORMAL_CLIP_DN = 500; // spo2 reduce 0.5/s at most in normal clip mode +const uint8_t SPO2_LOW_SNR_THRE = 40; // snr below this threshold, means error signal +const uint16_t IR_AC_TOUCH_THRE = 200; // AC_min*0.3 +const uint16_t IR_FFT_POW_THRE = 500; // fft_pow_min +const uint8_t SLOPE_PARA_MAX = 28; +const uint8_t SLOPE_PARA_MIN = 3; -static uint8_t hrs_ble_falg = 0; -#define PPG_DATA_LEN_MAX 17 -int32_t s_buf[256]; -uint32_t cnt_num = 0; -uint32_t phase3_rdy_num = 0; -uint8_t fifo_data_buf[768]; -uint8_t hrs_phase_num= 3; -uint8_t spo2_phase_num= 4; -uint8_t hrv_phase_num = 4; -extern uint8_t data_count; -extern uint8_t hr_no_living_dur; -extern uint8_t spo2_no_living_dur; - -extern int tyhx_long_timer_tick; -//spo2 agc -const uint8_t hx3695_spo2_agc_red_idac = RED_AGC_OFFSET; -const uint8_t hx3695_spo2_agc_ir_idac = IR_AGC_OFFSET; -const uint8_t hx3695_spo2_agc_ir_idac1 = IR_AGC_OFFSET; -const uint8_t hx3695_spo2_agc_ir_idac2 = IR_AGC_OFFSET; -const uint8_t hx3695_spo2_agc_green_idac = GREEN_AGC_OFFSET; -//hrs agc -const uint8_t hx3695_hrs_agc_idac = HR_GREEN_AGC_OFFSET; -const uint8_t hx3695_hrs_g1_agc_idac = HR_GREEN1_AGC_OFFSET; -const uint8_t hx3695_hrs_g2_agc_idac = HR_GREEN2_AGC_OFFSET; -const uint8_t hx3695_hrs_g3_agc_idac = HR_GREEN3_AGC_OFFSET; -//hrv agc -const uint8_t hx3695_hrv_agc_idac = HR_GREEN_AGC_OFFSET; - -const uint8_t green_led_max_init = 255; -const uint8_t red_led_max_init = 255; -const uint8_t ir_led_max_init = 255; - -uint8_t low_vbat_flag =0; -WORK_MODE_T work_mode_flag = HRS_MODE; const uint16_t static_thre_val = 150; const uint8_t gsen_lv_val = 0; -uint8_t read_fifo_first_flg = 0; - -//HRS_INFRARED_THRES -const int32_t hrs_ir_unwear_thres = 10000; -const int32_t hrs_ir_wear_thres = 15000; -//HRV_INFRARED_THRES -const int32_t hrv_ir_unwear_thres = 8000; //demo143b 25000 -const int32_t hrv_ir_wear_thres = 10000; -//SPO2_INFRARED_THRES -const int32_t spo2_ir_unwear_thres = 8000; //demo143b 25000 30000 -const int32_t spo2_ir_wear_thres = 10000; -const uint8_t spo2_ir_wear_offset = 15; -//CHECK_WEAR_MODE_THRES -const int32_t check_mode_unwear_thre = 20000; -const int32_t check_mode_wear_thre = 22000; - - -uint8_t alg_ram[11 * 1024] __attribute__((aligned(4))); -//uint8_t alg_ram[10] = {0}; -ppg_sensor_data_t ppg_s_data; - -static int history_wear_status = -1; -static uint8_t wear_status = 0; -static uint8_t spo2_result = 0; -static int32_t factory_data = 0; -static uint8_t hx3695_chip_id = 0; -// static int timeout = 0; - -//////// spo2 para and switches -const uint8_t COUNT_BLOCK_NUM = 25; //delay the block of some single good signal after a series of bad signal -const uint8_t SPO2_LOW_XCORR_THRE = 30; //(64*xcorr)'s square below this threshold, means error signal -const uint8_t SPO2_CALI = 1; //spo2_result cali mode -const uint8_t XCORR_MODE = 1; //xcorr mode switch -const uint8_t QUICK_RESULT = 1; //come out the spo2 result quickly ;0 is normal,1 is quick -const uint16_t MEAN_NUM = 32; //the length of smooth-average ;the value of MEAN_NUM can be given only 256 and 512 -const uint8_t G_SENSOR = 0; //if =1, open the gsensor mode -const uint8_t SPO2_GSEN_POW_THRE = 150; //gsen pow judge move, range:0-200; -const uint32_t SPO2_BASE_LINE_INIT = 138000; //spo2 baseline init, = 103000 + ratio(a variable quantity,depends on different cases)*SPO2_SLOPE -const int32_t SOP2_DEGLITCH_THRE = 100000; //remove signal glitch over this threshold -const int32_t SPO2_REMOVE_JUMP_THRE = 50000; //remove signal jump over this threshold -const uint32_t SPO2_SLOPE = 50000; //increase this slope, spo2 reduce more -const uint16_t SPO2_LOW_CLIP_END_TIME = 1500; //low clip mode before this data_cnt, normal clip mode after this -const uint16_t SPO2_LOW_CLIP_DN = 150; //spo2 reduce 0.15/s at most in low clip mode -const uint16_t SPO2_NORMAL_CLIP_DN = 500; //spo2 reduce 0.5/s at most in normal clip mode -const uint8_t SPO2_LOW_SNR_THRE = 40; //snr below this threshold, means error signal -const uint16_t IR_AC_TOUCH_THRE = 200; //AC_min*0.3 -const uint16_t IR_FFT_POW_THRE = 500; //fft_pow_min -const uint8_t SLOPE_PARA_MAX = 28; -const uint8_t SLOPE_PARA_MIN = 3; - -#ifdef SPO2_DATA_CALI -static int32_t red_data_fifo[4] = {0}; -static int32_t ir_data_fifo[4] = {0}; -static int32_t red_dc_temp = 0; -static int32_t ir_dc_temp = 0; -static int32_t red_data_pre = 0; -static int32_t ir_data_pre = 0; -static int32_t red_jump_delta = 0; -static int32_t ir_jump_delta = 0; -static int32_t cali_data_cnt = 0; -#endif - -// us 延时函数， 客户需填写 +void hx3695_spi_bus_init(void) +{ + +} +// us ��ʱ������ �ͻ�����д void hx3695_delay_us(uint32_t us) { tyhx_delay_us(us); @@ -183,17 +102,16 @@ void hx3695_delay_us(uint32_t us) void hx3695_delay_ms(uint32_t ms) { - tyhx_delay_ms(ms); + tyhx_delay_ms(ms); } // i2c 写函数， 客户需填写, 地址0x44(7bit) bool hx3695_write_reg(uint8_t addr, uint8_t data) { - custom_i2c_write_reg(HX3695_I2C_DEV_8ADDR,addr,1,&data,1,I2C_BUS_2); + custom_i2c_write_reg(HX3695_I2C_DEV_8ADDR,addr,1,&data,1,I2C_BUS_2); return true; } -// i2c 读函数， 客户需填写 uint8_t hx3695_read_reg(uint8_t addr) { uint8_t data_buf = 0; @@ -203,79 +121,10 @@ uint8_t hx3695_read_reg(uint8_t addr) } // i2c 连读函数， 客户需填写 -bool hx3695_brust_read_reg(uint8_t addr, uint8_t *buf, uint16_t length) +void hx3695_brust_read_reg(uint8_t addr, uint8_t *buf, uint16_t length) { //TYHX_LOG("brust read\r\n"); custom_i2c_read_regs(HX3695_I2C_DEV_8ADDR,addr,1,buf,length,I2C_BUS_2); - return true; -} - -void Efuse_Mode_Check(void) -{ -#if 1//def TEST_RELEASE_USE - PRINT("@@@@@@@@@ Efuse_Mode_Check\r\n"); - uint8_t REG_50_E, REG_51_E, REG_52_E, REG_53_E; - - hx3695_write_reg(0x5c, 0x08) ; //0x5c - hx3695_write_reg(0x5d, 0x02) ; //0x5d - hx3695_delay_us(10); - - hx3695_write_reg(0x5a,0x10); //0x5A - - hx3695_write_reg(0x5b,0x04); - hx3695_write_reg(0x5b,0x00); - hx3695_delay_us(10); - hx3695_write_reg(0x5b,0x44); - hx3695_write_reg(0x5b,0x40); - - REG_50_E = hx3695_read_reg(0x50); - REG_51_E = hx3695_read_reg(0x51); - REG_52_E = hx3695_read_reg(0x52); - REG_53_E = hx3695_read_reg(0x53); - - hx3695_write_reg(0x5a,0x20); //0x5A - hx3695_write_reg(0x50,REG_50_E); - hx3695_write_reg(0x51,REG_51_E); - hx3695_write_reg(0x52,REG_52_E); - hx3695_write_reg(0x53,REG_53_E); - - TYHX_LOG("EFUSE MC2: 0x50=0x%2x 0x51= 0x%2x 0x52= 0x%2x 0x53= 0x%2x \r\n",REG_50_E,REG_51_E,REG_52_E,REG_53_E); - - hx3695_write_reg(0x5a,0x00); - hx3695_write_reg(0x5c,0x00); //0x5c - hx3695_write_reg(0x5d,0x00); //0x5d -#endif -} -bool Efuse_judge(void) -{ - uint8_t REG_50, REG_51, REG_52, REG_53,REG_50_A; - - REG_50 = hx3695_read_reg(0x50); //32k - REG_51 = hx3695_read_reg(0x51); - REG_52 = hx3695_read_reg(0x52); - REG_53 = hx3695_read_reg(0x53); //bit<7> efuse trim flg ==1 - -// hx3695_write_reg(0x5d,0x00); -// hx3695_write_reg(0x5a,0x20); -// REG_50_A=REG_50+1; -// hx3695_write_reg(0x50,REG_50_A); // REG_50+1 -// TYHX_LOG("EFUSE 0x50=%x \r\n",REG_50_A); -// hx3695_write_reg(0x50,REG_51); -// hx3695_write_reg(0x50,REG_52); -// hx3695_write_reg(0x50,REG_53); - - //TYHX_LOG("EFUSE MC1 :0x50=0x%2x 0x51= 0x%2x 0x52= 0x%2x 0x53= 0x%2x \r\n",REG_50,REG_51,REG_52,REG_53); - if ((REG_50 == 0x40) && (REG_51 ==0x50) && (REG_52 ==0x10) && (REG_53 ==0x22)) - { - Efuse_Mode_Check(); - //TYHX_LOG("this chip is before MC \r\n"); - } - else - { - //TYHX_LOG("EFUSE MC3 :0x50=0x%2x 0x51= 0x%2x 0x52= 0x%2x 0x53= 0x%2x \r\n",REG_50,REG_51,REG_52,REG_53); - //TYHX_LOG("this chip is after MC \r\n"); - } - return true; } uint32_t hx3695_wear_mode_timers_start(void) @@ -312,9 +161,8 @@ uint32_t gsen_read_timers_stop(void) } -/* 完成读取PPG数据定时器接口， 循环调用， 默认320ms -void heart_rate_meas_timeout_handler(void * p_context) -*/ +/* ��ɶ�ȡPPG���ݶ�ʱ���ӿڣ� ѭ�����ã� Ĭ��320ms*/ +// void heart_rate_meas_timeout_handler(void *p_context) void hx3695_320ms_timer_cfg(bool en) { if(en) @@ -354,22 +202,52 @@ void hx3695_5000ms_timer_cfg(bool en) } -#if defined(INT_MODE) -/* 如采用中断模式， 如完成中断开启和关闭接口 -void hx3695_ppg_Int_handle(void) -*/ void hx3695_gpioint_cfg(bool en) { - if(en) - { - hx3695_gpioint_enable(); - } - else - { - hx3695_gpioint_disable(); - } + // if (en) + // { + // hx3695_gpioint_enable(); + // } + // else + // { + // hx3695_gpioint_disable(); + // } +} + +void Efuse_Mode_Check(void) +{ + uint8_t REG_50_E, REG_51_E, REG_52_E, REG_53_E; + + hx3695_write_reg(0x5c, 0x08); + hx3695_write_reg(0x5d, 0x02); + hx3695_delay_us(10); + + hx3695_write_reg(0x5a,0x10); + + hx3695_write_reg(0x5b,0x04); + hx3695_write_reg(0x5b,0x00); + hx3695_delay_us(10); + hx3695_write_reg(0x5b,0x44); + hx3695_write_reg(0x5b,0x40); + + REG_50_E = hx3695_read_reg(0x50); + REG_51_E = hx3695_read_reg(0x51); + REG_52_E = hx3695_read_reg(0x52); + REG_53_E = hx3695_read_reg(0x53); + + hx3695_write_reg(0x5a,0x20); + hx3695_write_reg(0x50,REG_50_E); + hx3695_write_reg(0x51,REG_51_E); + hx3695_write_reg(0x52,REG_52_E); + hx3695_write_reg(0x53,REG_53_E); + +// DEBUG_PRINTF("EFUSE MC2: 0x50=0x%2x 0x51= 0x%2x 0x52= 0x%2x 0x53= 0x%2x \r\n",REG_50_E,REG_51_E,REG_52_E,REG_53_E); + + hx3695_write_reg(0x5a,0x00); + hx3695_write_reg(0x5c,0x00); //0x5c + hx3695_write_reg(0x5d,0x00); //0x5d + } -#endif uint8_t hx3695_chip_check(void) { @@ -396,121 +274,154 @@ uint8_t hx3695_chip_check(void) return chip_id; } -void hx3695_get_id(uint8_t *ppg_id) -{ - *ppg_id = hx3695_chip_id; -} - uint8_t hx3695_read_fifo_size(void) { - uint8_t data_len_h,data_len_l; - uint16_t fifo_data_length; - data_len_h = hx3695_read_reg(0x21); - data_len_l = hx3695_read_reg(0x20); - fifo_data_length = (((data_len_h&0x01)<<8)|data_len_l); - + uint8_t data_len_h, data_len_l; + uint16_t fifo_data_length; + data_len_h = hx3695_read_reg(0x21); + data_len_l = hx3695_read_reg(0x20); + fifo_data_length = (((data_len_h & 0x01) << 8) | data_len_l); return fifo_data_length; } +uint16_t hx3695_led_data_analysis(ppg_sensor_data_t *ppg_sensor_dat, uint16_t fifo_read_length, uint8_t sig) +{ + int32_t data_temp = 0; + uint8_t fifo_data_flag = 0; + uint16_t count = 0; + uint32_t ii = 0; + for(ii=0; iis_buf[ii*3+2]>>5; + count = ii/ppg_sensor_dat->led_activated; + if(sig==0) + { + data_temp = (int32_t)(ppg_sensor_dat->s_buf[ii*3]|(ppg_sensor_dat->s_buf[ii*3+1]<<8)|((ppg_sensor_dat->s_buf[ii*3+2]&0x1f)<<16)); + } + else + { + if((ppg_sensor_dat->s_buf[ii*3+2]&0x10)!=0) + { + data_temp = (int32_t)(ppg_sensor_dat->s_buf[ii*3]|(ppg_sensor_dat->s_buf[ii*3+1]<<8)|((ppg_sensor_dat->s_buf[ii*3+2]&0x0f)<<16))-1048576; + } + else + { + data_temp = (int32_t)(ppg_sensor_dat->s_buf[ii*3]|(ppg_sensor_dat->s_buf[ii*3+1]<<8)|((ppg_sensor_dat->s_buf[ii*3+2]&0x1f)<<16)); + } + } + //DEBUG_PRINTF("fifo_data: %d %d\r\n", ii, data_temp); + ppg_sensor_dat->led_data[fifo_data_flag].data_val[count] = data_temp; + } + for(ii=0;ii<4;ii++) + { + if(ppg_sensor_dat->led_data[ii].led_state == Activated) + { + ppg_sensor_dat->led_data[ii].data_count = count+1; + } + } + return count+1; +} -uint16_t hx3695_read_fifo_data(int32_t *buf, uint8_t phase_num, uint8_t sig) +void hx3695_get_led_para(ppg_sensor_data_t *ppg_sensor_dat) { - uint8_t data_flg_start = 0; - uint8_t data_flg_end = 0; -// int32_t data; - uint8_t databuf[3]; - uint32_t ii=0; - uint16_t data_len_h = 0; - uint16_t data_len_l = 0; - uint16_t fifo_data_length = 0; - uint16_t fifo_read_length = 0; - uint16_t fifo_read_bytes = 0; - uint16_t fifo_out_length = 0; - uint16_t fifo_out_count = 0; - - data_len_h = hx3695_read_reg(0x21); - data_len_l = hx3695_read_reg(0x20); - fifo_data_length = (((data_len_h&0x01)<<8)|data_len_l); -// SEGGER_RTT_printf(0,"fifo_data_length = %d\r\n", fifo_data_length); - if(fifo_data_length<2*phase_num) - { - return 0; - } - fifo_read_length = ((fifo_data_length-phase_num)/phase_num)*phase_num; -// SEGGER_RTT_printf(0,"fifo_data_length_change = %d\r\n", fifo_read_length); - fifo_read_bytes = fifo_read_length*3; - if(read_fifo_first_flg == 1) - { - hx3695_brust_read_reg(0x22, databuf, 3); - read_fifo_first_flg = 0; - } - hx3695_brust_read_reg(0x22, fifo_data_buf, fifo_read_bytes); - // for(ii=0; ii>5); - } - data_flg_start = fifo_data_buf[2]>>5; - data_flg_end = fifo_data_buf[fifo_read_bytes-1]>>5; - fifo_out_length = fifo_read_length; - if(data_flg_start>0) - { - fifo_out_length = fifo_read_length-phase_num + data_flg_start; - for(ii=0; iiled_data[led_index].led_state == Activated) { -// SEGGER_RTT_printf(0,"fifo_buf %d/%d, %d\r\n", ii+1,fifo_out_length,buf[ii]); + hx3695_write_reg(0X43, led_index*2+1); + ppg_sensor_dat->led_data[led_index].led_current = hx3695_read_reg(0x45); + ppg_sensor_dat->led_data[led_index].offset_idac = hx3695_read_reg(0x48); + ppg_sensor_dat->led_data[led_index].tia_rf = hx3695_read_reg(0x44)&0x0f; } - fifo_out_length = fifo_out_length+phase_num-data_flg_end - 1; - fifo_out_count = fifo_out_length/phase_num; - return fifo_out_count; + } } -void hx3695_vin_check(uint16_t led_vin) +uint16_t hx3695_read_fifo_data(ppg_sensor_data_t *ppg_sensor_dat) { - low_vbat_flag = 0; - if(led_vin < 3700) + uint8_t databuf[3]; +// uint32_t ii=0; + uint16_t data_len_h = 0; + uint16_t data_len_l = 0; + uint16_t fifo_data_length = 0; + uint16_t fifo_read_length = 0; + uint16_t fifo_read_bytes = 0; + uint16_t fifo_out_count = 0; + + data_len_h = hx3695_read_reg(0x21); + data_len_l = hx3695_read_reg(0x20); + fifo_data_length = (((data_len_h&0x01)<<8)|data_len_l); + + DEBUG_PRINTF("fifo_data_length: %d\r\n", fifo_data_length); + + if (fifo_data_length>FIFO_DATA_LENGTH) + { + fifo_data_length = FIFO_DATA_LENGTH; + } + + if(fifo_data_length<2*ppg_sensor_dat->led_activated) + { + return 0; + } + fifo_read_length = ((fifo_data_length-ppg_sensor_dat->led_activated)/ppg_sensor_dat->led_activated)*ppg_sensor_dat->led_activated; + fifo_read_bytes = fifo_read_length*3; + if(read_fifo_first_flg == 1) { - low_vbat_flag = 1; + hx3695_brust_read_reg(0x22, databuf, 3); + read_fifo_first_flg = 0; } + hx3695_brust_read_reg(0x22, ppg_sensor_dat->s_buf, fifo_read_bytes); + fifo_out_count = hx3695_led_data_analysis(ppg_sensor_dat,fifo_read_length,1); + + hx3695_get_led_para(ppg_sensor_dat); + + return fifo_out_count; } -void hx3695_ppg_off(void) +void hx3695_read_phase_data(int32_t *s_buf) { + uint8_t databuf1[6] = {0}; + uint8_t databuf2[6] = {0}; + uint8_t databuf3[6] = {0}; + uint8_t databuf4[6] = {0}; + + hx3695_brust_read_reg(0x03, databuf1, 6); + hx3695_brust_read_reg(0x09, databuf2, 6); + hx3695_brust_read_reg(0x0f, databuf3, 6); + hx3695_brust_read_reg(0x15, databuf4, 6); + + s_buf[0] = ((databuf1[0])|(databuf1[1]<<8)|(databuf1[2]<<16)); + s_buf[1] = ((databuf1[3])|(databuf1[4]<<8)|(databuf1[5]<<16)); + s_buf[2] = ((databuf2[0])|(databuf2[1]<<8)|(databuf2[2]<<16)); + s_buf[3] = ((databuf2[3])|(databuf2[4]<<8)|(databuf2[5]<<16)); + s_buf[4] = ((databuf3[0])|(databuf3[1]<<8)|(databuf3[2]<<16)); + s_buf[5] = ((databuf3[3])|(databuf3[4]<<8)|(databuf3[5]<<16)); + s_buf[6] = ((databuf4[0])|(databuf4[1]<<8)|(databuf4[2]<<16)); + s_buf[7] = ((databuf4[3])|(databuf4[4]<<8)|(databuf4[5]<<16)); + DEBUG_PRINTF("phase_buf = %d,%d,%d,%d,%d,%d,%d,%d \r\n", s_buf[0],s_buf[1],s_buf[2],s_buf[3],s_buf[4],s_buf[5],s_buf[6],s_buf[7]); +} - hx3695_delay_ms(5); +void hx3695_read_led_data(int32_t *s_buf) +{ + uint8_t databuf1[3] = {0}; + uint8_t databuf2[3] = {0}; + uint8_t databuf3[3] = {0}; + uint8_t databuf4[3] = {0}; + + hx3695_brust_read_reg(0x06, databuf1, 3); + hx3695_brust_read_reg(0x0c, databuf2, 3); + hx3695_brust_read_reg(0x12, databuf3, 3); + hx3695_brust_read_reg(0x18, databuf4, 3); + + s_buf[0] = ((databuf1[0])|(databuf1[1]<<8)|(databuf1[2]<<16)); + s_buf[1] = ((databuf2[0])|(databuf2[1]<<8)|(databuf2[2]<<16)); + s_buf[2] = ((databuf3[0])|(databuf3[1]<<8)|(databuf3[2]<<16)); + s_buf[3] = ((databuf4[0])|(databuf4[1]<<8)|(databuf4[2]<<16)); +// DEBUG_PRINTF("led_buf = %d,%d,%d,%d\r\n", s_buf[0],s_buf[1],s_buf[2],s_buf[3]); +} + +void hx3695_ppg_off(void) +{ hx3695_write_reg(0x02, 0x01); } @@ -520,3353 +431,1099 @@ void hx3695_ppg_on(void) hx3695_delay_ms(5); } -void hx3695_data_reset(void) +void hx3695_software_reset(void) { -#if defined(TIMMER_MODE) - hx3695_320ms_timer_cfg(false); - hx3695_40ms_timer_cfg(false); -#elif defined(INT_MODE) - hx3695_gpioint_cfg(false); -#endif -#if defined(HRS_ALG_LIB) - hx3695_hrs_data_reset(); -#endif -#if defined(SPO2_ALG_LIB) - hx3695_spo2_data_reset(); -#endif -#if defined(HRV_ALG_LIB) - hx3695_hrv_data_reset(); -#endif - AGC_LOG("hx3695 data reset!\r\n"); + uint8_t ii = 0; + ppg_sensor_data.mode = NULL_MODE; + ppg_sensor_data.fs = 25; + ppg_sensor_data.watermark = 0; + ppg_sensor_data.led_activated = 0; + for(ii=0;ii<4;ii++) + { + ppg_sensor_data.led_data[ii].isneed_cal_start = false; + ppg_sensor_data.led_data[ii].led_current = 0; + ppg_sensor_data.led_data[ii].offset_idac = 0; + ppg_sensor_data.led_data[ii].tia_rf = 0; + ppg_sensor_data.led_data[ii].led_state = InActivated; + } + read_fifo_first_flg = 0; + s_ppg_state = 0; + s_cal_state = 0; + check_touch_cnt = 0; + hx3695_agc_reset(); + #if defined(INT_MODE) + hx3695_gpioint_cfg(false); + #else + hx3695_320ms_timer_cfg(false); + hx3695_40ms_timer_cfg(false); + #endif } -#ifdef HRS_ALG_LIB -// 心率模式下ppg 初始化配置 -void hx3695_hrs_ppg_init(void) // ppg fs=25hz, phase conversion ready interupt en +bool hx3695_check_wear(ppg_sensor_data_t *ppg_sensor_dat) { - uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/ - uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */ - - uint16_t fifo_watermark= 81 ; - uint8_t adc_rst_post_num=0; /* 00=16,01=32,10=64,11=128*/ - uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ - uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/ - uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/ - uint8_t phase7_8_internal = 0; /* phase7 and phase8 prf internal cfg */ - - uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase5_enable = 1; /*phase5_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase6_enable = 1; /*phase6_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase7_enable = 1; /*phase7_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ - - uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - - uint8_t phase1_mux_sel = 0; /* sel phase1*/ - uint8_t phase2_mux_sel = 1; /* sel phase2*/ - uint8_t phase3_mux_sel = 2; /* sel phase3*/ - uint8_t phase4_mux_sel = 3; /* sel phase4*/ - uint8_t phase5_mux_sel = 4; /* sel phase5*/ - uint8_t phase6_mux_sel = 5; /* sel phase6*/ - uint8_t phase7_mux_sel = 6; /* sel phase7*/ - uint8_t phase8_mux_sel = 7; /* sel phase8*/ - + uint8_t ii = 0; + + for(ii=0;iiled_data[3].data_count;ii++) + { + if(ppg_sensor_dat->led_data[3].data_val[ii] > CHECK_WEAR_THRE) + { + if(check_touch_cnt < CHECK_TOUCH_NUM) + { + check_touch_cnt++; + } + if(check_touch_cnt >= CHECK_TOUCH_NUM) + { + wear_status = MSG_WEAR; + } + } + else if(ppg_sensor_dat->led_data[3].data_val[ii] < CHECK_UNWEAR_THRE) + { + if(check_touch_cnt>0) + { + check_touch_cnt--; + } + if(check_touch_cnt == 0) + { + wear_status = MSG_NO_WEAR; + } + } + + DEBUG_PRINTF("data:%d, wear_status_pre:%d, wear_status:%d \r\n",ppg_sensor_dat->led_data[3].data_val[ii],wear_status_pre, wear_status); + + if(wear_status_pre != wear_status) + { + // printf("wear_status:%d\n",wear_status); + wear_status_pre = wear_status; +#ifdef SUPPORT_CYWEE_SERVICE + cywee_wear_status_update(&wear_status); +#endif + // if(wear_status == MSG_NO_WEAR) + // { + // hx3695_wear_low_power(ppg_sensor_dat); + // } + // else if(wear_status == MSG_WEAR) + // { + // hx3695_init(work_mode_flag); + // } + } + } + return 1; +} - uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase1_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */ - uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */ - uint8_t phase1_pd_sel = HRS_PD; //0x03 /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase1_ldr2_cur = 0; +void hx3695_ppg_para_init(ppg_sensor_data_t *ppg_sensor_dat) +{ + uint16_t sample_rate = 25; + uint32_t prf_clk_num = 32000/sample_rate; +// uint16_t watermark = 40; + + uint8_t adc_rst_post_num=0; + uint8_t samp_delay_leden_num = 0; + uint8_t samp_copy_avg = 0; + uint8_t data_avg_num = 0; + uint8_t phase7_8_internal = 0; + + uint8_t phase1_enable = 0; + uint8_t phase2_enable = 0; + uint8_t phase3_enable = 0; + uint8_t phase4_enable = 0; + uint8_t phase5_enable = 0; + uint8_t phase6_enable = 0; + uint8_t phase7_enable = 0; + uint8_t phase8_enable = 0; + + uint8_t phase1_adc_osr = 3; + uint8_t phase2_adc_osr = 3; + uint8_t phase3_adc_osr = 3; + uint8_t phase4_adc_osr = 3; + uint8_t phase5_adc_osr = 3; + uint8_t phase6_adc_osr = 3; + uint8_t phase7_adc_osr = 3; + uint8_t phase8_adc_osr = 3; + + uint8_t phase1_mux_sel = 0; + uint8_t phase2_mux_sel = 1; + uint8_t phase3_mux_sel = 2; + uint8_t phase4_mux_sel = 3; + uint8_t phase5_mux_sel = 4; + uint8_t phase6_mux_sel = 5; + uint8_t phase7_mux_sel = 6; + uint8_t phase8_mux_sel = 7; + + uint8_t phase1_inner_avg = 0; + uint8_t phase1_tia_res = 0; + uint8_t phase1_tia_cap = 4; + uint8_t phase1_led_drv1_cha_sel = 0; + uint8_t phase1_led_drv2_cha_sel = 0; + uint8_t phase1_pd_sel = LED0_PD_SEL; + uint8_t phase1_als_offset_idac = 0; + uint8_t phase1_led_offset_idac = 0; + uint8_t phase1_ldr1_cur = 0; + uint8_t phase1_ldr2_cur = 0; uint8_t phase1_ad_inr_ctrl = 3; uint8_t phase1_ad_of_idac_ctrl = 0; - uint8_t phase1_led_en = 1; /* phase1 led enable*/ - uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - - - uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase2_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase2_led_drv1_cha_sel = GREEN_LED_SLE; //0x10 //GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase2_led_drv2_cha_sel = 0; - uint8_t phase2_pd_sel = HRS_PD; //0x0C //0x03 /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase2_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase2_ldr2_cur = 0; + uint8_t phase1_led_en = 1; + uint8_t phase1_dsp_mov_avg_num = 0; + uint8_t phase1_dsp_iir_lp_coeff = 0; + + uint8_t phase2_inner_avg = 0; + uint8_t phase2_tia_res = 0; + uint8_t phase2_tia_cap = 4; + uint8_t phase2_led_drv1_cha_sel = LED0_LDR_SEL; + uint8_t phase2_led_drv2_cha_sel = LED0_LDR_SEL; + uint8_t phase2_pd_sel = LED0_PD_SEL; + uint8_t phase2_als_offset_idac = 0; + uint8_t phase2_led_offset_idac = 0; + uint8_t phase2_ldr1_cur = 0; + uint8_t phase2_ldr2_cur = 0; uint8_t phase2_ad_inr_ctrl = 3; uint8_t phase2_ad_of_idac_ctrl = 0; - uint8_t phase2_led_en = 1; /* phase1 led enable*/ - uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - - uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase3_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase3_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase2_led_en = 1; + uint8_t phase2_dsp_mov_avg_num = 0; + uint8_t phase2_dsp_iir_lp_coeff = 0; + + uint8_t phase3_inner_avg = 0; + uint8_t phase3_tia_res = 0; + uint8_t phase3_tia_cap = 4; + uint8_t phase3_led_drv1_cha_sel = 0; uint8_t phase3_led_drv2_cha_sel = 0; - uint8_t phase3_pd_sel = HRS_PD; //0x03 /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase3_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase3_ldr2_cur = 0; + uint8_t phase3_pd_sel = LED1_PD_SEL; + uint8_t phase3_als_offset_idac = 0; + uint8_t phase3_led_offset_idac = 0; + uint8_t phase3_ldr1_cur = 0; + uint8_t phase3_ldr2_cur = 0; uint8_t phase3_ad_inr_ctrl = 3; uint8_t phase3_ad_of_idac_ctrl = 0; - uint8_t phase3_led_en = 1; /* phase1 led enable*/ - uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - - uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase4_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase4_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase4_led_drv2_cha_sel = 0; - uint8_t phase4_pd_sel = HRS_PD; //0x0C /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase4_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase4_ldr2_cur = 0; -// uint8_t phase4_of_idac1_cur = 0; -// uint8_t phase4_of_idac2_cur = 0; + uint8_t phase3_led_en = 1; + uint8_t phase3_dsp_mov_avg_num = 0; + uint8_t phase3_dsp_iir_lp_coeff = 0; + + uint8_t phase4_inner_avg = 0; + uint8_t phase4_tia_res = 0; + uint8_t phase4_tia_cap = 4; + uint8_t phase4_led_drv1_cha_sel = LED1_LDR_SEL; + uint8_t phase4_led_drv2_cha_sel = LED1_LDR_SEL; + uint8_t phase4_pd_sel = LED1_PD_SEL; + #ifdef DOUBLE_GREEN + if(ppg_sensor_dat->mode == HRS_MODE) + { + phase4_led_drv1_cha_sel = LED1N_LDR_SEL; + phase4_led_drv2_cha_sel = LED1N_LDR_SEL; + phase4_pd_sel = LED1N_PD_SEL; + } + #endif + uint8_t phase4_als_offset_idac = 0; + uint8_t phase4_led_offset_idac = 0; + uint8_t phase4_ldr1_cur = 0; + uint8_t phase4_ldr2_cur = 0; uint8_t phase4_ad_inr_ctrl = 3; uint8_t phase4_ad_of_idac_ctrl = 0; -// uint8_t phase4_afe_offset = 0; - uint8_t phase4_led_en = 1; /* phase1 led enable*/ - - uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase5_led_drv1_cha_sel = 0; //0x10 /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase4_led_en = 1; + uint8_t phase4_dsp_mov_avg_num = 0; + uint8_t phase4_dsp_iir_lp_coeff = 0; + + uint8_t phase5_inner_avg = 0; + uint8_t phase5_tia_res = 0; + uint8_t phase5_tia_cap = 4; + uint8_t phase5_led_drv1_cha_sel = 0; uint8_t phase5_led_drv2_cha_sel = 0; - uint8_t phase5_pd_sel = HRS_PD; //0x0C /* 1 = pd1; 2 = pd2; */ - uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase5_ldr2_cur = 0; -// uint8_t phase5_of_idac1_cur = 0; -// uint8_t phase5_of_idac2_cur = 0; + uint8_t phase5_pd_sel = LED2_PD_SEL; + uint8_t phase5_als_offset_idac = 0; + uint8_t phase5_led_offset_idac = 0; + uint8_t phase5_ldr1_cur = 0; + uint8_t phase5_ldr2_cur = 0; uint8_t phase5_ad_inr_ctrl = 3; uint8_t phase5_ad_of_idac_ctrl = 0; -// uint8_t phase5_afe_offset = 0; - uint8_t phase5_led_en = 1; /* phase1 led enable*/ - - uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase6_led_drv2_cha_sel = 0; - uint8_t phase6_pd_sel = HRS_PD; //0x0C /* 1 = pd1; 2 = pd2; */ - uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase6_ldr2_cur = 0; -// uint8_t phase6_of_idac1_cur = 0; -// uint8_t phase6_of_idac2_cur = 0; + uint8_t phase5_led_en = 1; + uint8_t phase5_dsp_mov_avg_num = 0; + uint8_t phase5_dsp_iir_lp_coeff = 0; + + uint8_t phase6_inner_avg = 0; + uint8_t phase6_tia_res = 0; + uint8_t phase6_tia_cap = 4; + uint8_t phase6_led_drv1_cha_sel = LED2_LDR_SEL; + uint8_t phase6_led_drv2_cha_sel = LED2_LDR_SEL; + uint8_t phase6_pd_sel = LED2_PD_SEL; + uint8_t phase6_als_offset_idac = 0; + uint8_t phase6_led_offset_idac = 0; + uint8_t phase6_ldr1_cur = 0; + uint8_t phase6_ldr2_cur = 0; uint8_t phase6_ad_inr_ctrl = 3; uint8_t phase6_ad_of_idac_ctrl = 0; -// uint8_t phase6_afe_offset = 0; - uint8_t phase6_led_en = 1; /* phase1 led enable*/ - - uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase6_led_en = 1; + uint8_t phase6_dsp_mov_avg_num = 0; + uint8_t phase6_dsp_iir_lp_coeff = 0; + + uint8_t phase7_inner_avg = 0; + uint8_t phase7_tia_res = 1; + uint8_t phase7_tia_cap = 4; + uint8_t phase7_led_drv1_cha_sel = 0; uint8_t phase7_led_drv2_cha_sel = 0; - uint8_t phase7_pd_sel = SPO2_PD; //0x0C /* 1 = pd1; 2 = pd2; */ - uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase7_ldr2_cur = 0; -// uint8_t phase7_of_idac1_cur = 0; -// uint8_t phase7_of_idac2_cur = 0; + uint8_t phase7_pd_sel = LED3_PD_SEL; + uint8_t phase7_als_offset_idac = 0; + uint8_t phase7_led_offset_idac = 0; + uint8_t phase7_ldr1_cur = 0; + uint8_t phase7_ldr2_cur = 0; uint8_t phase7_ad_inr_ctrl = 3; uint8_t phase7_ad_of_idac_ctrl = 0; -// uint8_t phase7_afe_offset = 0; - uint8_t phase7_led_en = 1; /* phase1 led enable*/ - - uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase8_led_drv1_cha_sel = IR_LED_SLE; //0x40 //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase8_led_drv2_cha_sel = 0; - uint8_t phase8_pd_sel = SPO2_PD; //0x0C /* 1 = pd1; 2 = pd2; */ - uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase8_ldr1_cur = 32; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase8_ldr2_cur = 0; -// uint8_t phase8_of_idac1_cur = 0; -// uint8_t phase8_of_idac2_cur = 0; + uint8_t phase7_led_en = 1; + uint8_t phase7_dsp_mov_avg_num = 0; + uint8_t phase7_dsp_iir_lp_coeff = 0; + + uint8_t phase8_inner_avg = 0; + uint8_t phase8_tia_res = 1; + uint8_t phase8_tia_cap = 4; + uint8_t phase8_led_drv1_cha_sel = LED3_LDR_SEL; + uint8_t phase8_led_drv2_cha_sel = LED3_LDR_SEL; + uint8_t phase8_pd_sel = LED3_PD_SEL; + uint8_t phase8_als_offset_idac = 0; + uint8_t phase8_led_offset_idac = 0; + uint8_t phase8_ldr1_cur = 20; + uint8_t phase8_ldr2_cur = 0; uint8_t phase8_ad_inr_ctrl = 3; uint8_t phase8_ad_of_idac_ctrl = 0; -// uint8_t phase8_afe_offset = 0; - uint8_t phase8_led_en = 1; /* phase1 led enable*/ - - uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t init_wait_delay = 5 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ; - 4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ - - uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ; - 4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */ - - uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/ - - uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ - - uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ - - uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ; - 4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */ - - hx3695_delay_ms(10); - - hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6 - hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8> - hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> - - hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); - hx3695_write_reg(0X2d, phase7_8_internal); - hx3695_write_reg(0X2e, 0x33);// gpio ctrl + uint8_t phase8_led_en = 1; + uint8_t phase8_dsp_mov_avg_num = 0; + uint8_t phase8_dsp_iir_lp_coeff = 0; + + uint8_t init_wait_delay = 5; + uint8_t afe_reset = 3; + uint8_t afe_rst_cnvt = 1; + uint8_t led_en_idac_pre = 2; + uint8_t led_en_idac = 1; + uint8_t led_on_time = 3; + + hx3695_write_reg(0x02,0x00); + hx3695_delay_ms(10); + + hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); + hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); + hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); + + hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); + hx3695_write_reg(0X2d, phase7_8_internal); + hx3695_write_reg(0X2e, 0x33); hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay)); - hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); + hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); - - hx3695_write_reg(0X31, (led_on_time<<4| 0x00)); - hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置； - hx3695_write_reg(0X34, 0x00);// 中断特殊配置； - hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置； - hx3695_write_reg(0X38, 0x00); - - hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); - hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); - hx3695_write_reg(0X3c, (phase5_inner_avg | (phase6_inner_avg<<4))); - hx3695_write_reg(0X3d, (phase7_inner_avg | (phase8_inner_avg<<4))); - hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); + hx3695_write_reg(0X31, led_on_time<<4); + hx3695_write_reg(0X33, 0x83); + hx3695_write_reg(0X34, 0x00); + hx3695_write_reg(0X36, 0x00); + hx3695_write_reg(0X38, 0x00); + + hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); + hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); + hx3695_write_reg(0X3c, (phase5_inner_avg | (phase6_inner_avg<<4))); + hx3695_write_reg(0X3d, (phase7_inner_avg | (phase8_inner_avg<<4))); + hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num ); hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num ); - - hx3695_write_reg(0X43, phase1_mux_sel); - hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); - hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase1_als_offset_idac); - hx3695_write_reg(0X48, phase1_led_offset_idac); - - hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4); - -// hx3695_write_reg(0X4e, thred_value); -// hx3695_write_reg(0X4f, thred_value>>5); - - hx3695_write_reg(0X43, phase2_mux_sel); - hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); - hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase2_als_offset_idac); - hx3695_write_reg(0X48, phase2_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4); - -//phase3 sel - - hx3695_write_reg(0X43, phase3_mux_sel); - hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); - hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase3_als_offset_idac); - hx3695_write_reg(0X48, phase3_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4); - -//phase4 sel - - hx3695_write_reg(0X43, phase4_mux_sel); - hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); - hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase4_als_offset_idac); - hx3695_write_reg(0X48, phase4_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4); - - hx3695_write_reg(0X43, phase5_mux_sel); - hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); - hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase5_als_offset_idac); - hx3695_write_reg(0X48, phase5_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase6_mux_sel); - hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); - hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase6_als_offset_idac); - hx3695_write_reg(0X48, phase6_led_offset_idac); -// hx3695_write_reg(0X48, phase6_led_offset_idac); - hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase7_mux_sel); - hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); - hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase7_als_offset_idac); - hx3695_write_reg(0X48, phase7_led_offset_idac); -// hx3695_write_reg(0X48, phase7_led_offset_idac); - hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase8_mux_sel); - hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); - hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase8_als_offset_idac); - hx3695_write_reg(0X48, phase8_led_offset_idac); -// hx3695_write_reg(0X48, phas8_led_offset_idac); - hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4); - - -// analog circuit cfg - hx3695_write_reg(0X60, 0x14); // - hx3695_write_reg(0X61, 0xf0); - hx3695_write_reg(0X62, 0x22); - hx3695_write_reg(0X63, 0x15); - - hx3695_write_reg(0X64, 0x08); - hx3695_write_reg(0X65, 0x88); //bug - - hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30 - hx3695_write_reg(0X67, 0x23); - hx3695_write_reg(0X68, 0x46); - hx3695_write_reg(0X69, 0x42); - - hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg - hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable - - hx3695_write_reg(0X6a, 0X0f); - hx3695_write_reg(0X6b, 0X22); - hx3695_write_reg(0X6c, 0X00); - hx3695_write_reg(0X6d, 0X37); - hx3695_write_reg(0X6e, 0X82); + hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num ); + hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num ); + + hx3695_write_reg(0X43, phase1_mux_sel); + hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); + hx3695_write_reg(0X45, phase1_ldr1_cur); + hx3695_write_reg(0x70, phase1_ldr2_cur); + hx3695_write_reg(0X46, phase1_pd_sel<<4); + hx3695_write_reg(0X47, phase1_als_offset_idac); + hx3695_write_reg(0X48, phase1_led_offset_idac); + hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); + hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4); + + hx3695_write_reg(0X43, phase2_mux_sel); + hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); + hx3695_write_reg(0X45, phase2_ldr1_cur); + hx3695_write_reg(0x70, phase2_ldr2_cur); + hx3695_write_reg(0X46, phase2_pd_sel<<4); + hx3695_write_reg(0X47, phase2_als_offset_idac); + hx3695_write_reg(0X48, phase2_led_offset_idac); + hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); + hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4); + + hx3695_write_reg(0X43, phase3_mux_sel); + hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); + hx3695_write_reg(0X45, phase3_ldr1_cur); + hx3695_write_reg(0x70, phase3_ldr2_cur); + hx3695_write_reg(0X46, phase3_pd_sel<<4); + hx3695_write_reg(0X47, phase3_als_offset_idac); + hx3695_write_reg(0X48, phase3_led_offset_idac); + hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); + hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4); + + hx3695_write_reg(0X43, phase4_mux_sel); + hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); + hx3695_write_reg(0X45, phase4_ldr1_cur); + hx3695_write_reg(0x70, phase4_ldr2_cur); + hx3695_write_reg(0X46, phase4_pd_sel<<4); + hx3695_write_reg(0X47, phase4_als_offset_idac); + hx3695_write_reg(0X48, phase4_led_offset_idac); + hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); + hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4); + + hx3695_write_reg(0X43, phase5_mux_sel); + hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); + hx3695_write_reg(0X45, phase5_ldr1_cur); + hx3695_write_reg(0x70, phase5_ldr2_cur); + hx3695_write_reg(0X46, phase5_pd_sel<<4); + hx3695_write_reg(0X47, phase5_als_offset_idac); + hx3695_write_reg(0X48, phase5_led_offset_idac); + hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); + hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4); + + hx3695_write_reg(0X43, phase6_mux_sel); + hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); + hx3695_write_reg(0X45, phase6_ldr1_cur); + hx3695_write_reg(0x70, phase6_ldr2_cur); + hx3695_write_reg(0X46, phase6_pd_sel<<4); + hx3695_write_reg(0X47, phase6_als_offset_idac); + hx3695_write_reg(0X48, phase6_led_offset_idac); + hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); + hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4); + + hx3695_write_reg(0X43, phase7_mux_sel); + hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); + hx3695_write_reg(0X45, phase7_ldr1_cur); + hx3695_write_reg(0x70, phase7_ldr2_cur); + hx3695_write_reg(0X46, phase7_pd_sel<<4); + hx3695_write_reg(0X47, phase7_als_offset_idac); + hx3695_write_reg(0X48, phase7_led_offset_idac); + hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); + hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4); + + hx3695_write_reg(0X43, phase8_mux_sel); + hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); + hx3695_write_reg(0X45, phase8_ldr1_cur); + hx3695_write_reg(0x70, phase8_ldr2_cur); + hx3695_write_reg(0X46, phase8_pd_sel<<4); + hx3695_write_reg(0X47, phase8_als_offset_idac); + hx3695_write_reg(0X48, phase8_led_offset_idac); + hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); + hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4); + + hx3695_write_reg(0X60, 0x14); + hx3695_write_reg(0X61, 0xf0); + hx3695_write_reg(0X62, 0x22); + hx3695_write_reg(0X63, 0x15); + hx3695_write_reg(0X64, 0x08); + hx3695_write_reg(0X65, 0x88); + hx3695_write_reg(0X66, 0x30); + hx3695_write_reg(0X67, 0x23); + hx3695_write_reg(0X68, 0x46); + hx3695_write_reg(0X69, 0x42); + hx3695_write_reg(0X39, 0xff); + hx3695_write_reg(0x73, 0xff); + hx3695_write_reg(0X6a, 0X0f); + hx3695_write_reg(0X6b, 0X22); + hx3695_write_reg(0X6c, 0X00); + hx3695_write_reg(0X6d, 0X37); + hx3695_write_reg(0X6e, 0X82); hx3695_write_reg(0X6f, 0X00); -/////////FIFO and adc conversion ready config//////// -/////////FIFO and adc conversion ready config//////// -#if defined(PPG_INT_MODE) - hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ bits<7> fifo enble - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int -#elif defined(INT_MODE) //FIFO_ALL_MOST_FULL) - hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ - bits<7> fifo enble - hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark - hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int +#if defined(INT_MODE) + hx3695_write_reg(0X1b, 0x91); + hx3695_write_reg(0X1c, watermark); + hx3695_write_reg(0X33, 0x83); + hx3695_write_reg(0X21, 0x00); + hx3695_write_reg(0X38, 0x04); #else - hx3695_write_reg(0X1b, 0x92); - - hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int - + hx3695_write_reg(0X1b, 0x91); + hx3695_write_reg(0X38, 0x01); #endif - - hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); - hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); + hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); + hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) ); - hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); - -// hx3695_write_reg(0X5c, 0x02);//soft reset - hx3695_delay_ms(5); - hx3695_write_reg(0X5c, 0x00);//release + hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); + + hx3695_write_reg(0X5c, 0x02); + hx3695_delay_ms(1); + hx3695_write_reg(0X1b, 0x10); + hx3695_delay_ms(1); + hx3695_write_reg(0X1b, 0x91); + hx3695_write_reg(0X5c, 0x00); read_fifo_first_flg = 1; return ; } -#endif -#ifdef SPO2_ALG_LIB -// 血氧模式下 初始化配置 -void hx3695_spo2_ppg_init(void) //20200615 ericy ppg fs=25hz, phase3 conversion ready interupt en +void hx3695_set_fs(ppg_sensor_data_t *ppg_sensor_dat) { - uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/ - uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */ - - uint16_t fifo_watermark= 250 ; - uint8_t adc_rst_post_num=0; /* 00=16,01=32,10=64,11=128*/ - uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ - uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/ - uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/ - uint8_t phase7_8_internal = 0; /* phase7 and phase8 prf internal cfg */ - -// uint16_t thred_value = 32500; - - uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase5_enable = 1; /*phase5_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase6_enable = 1; /*phase6_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase7_enable = 1; /*phase7_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ - - uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - - uint8_t phase1_mux_sel = 0; /* sel phase1*/ - uint8_t phase2_mux_sel = 1; /* sel phase2*/ - uint8_t phase3_mux_sel = 2; /* sel phase3*/ - uint8_t phase4_mux_sel = 3; /* sel phase4*/ - uint8_t phase5_mux_sel = 4; /* sel phase5*/ - uint8_t phase6_mux_sel = 5; /* sel phase6*/ - uint8_t phase7_mux_sel = 6; /* sel phase7*/ - uint8_t phase8_mux_sel = 7; /* sel phase8*/ - + uint32_t prf_clk_num = 32000/ppg_sensor_dat->fs; - uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase1_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */ - uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */ - uint8_t phase1_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase1_ldr2_cur = 0; -// uint8_t phase1_of_idac1_cur = 0; -// uint8_t phase1_of_idac2_cur = 0; - uint8_t phase1_ad_inr_ctrl = 3; - uint8_t phase1_ad_of_idac_ctrl = 0; -// uint8_t afe_offset = 0; - uint8_t phase1_led_en = 1; /* phase1 led enable*/ - - uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - - - uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase2_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase2_led_drv1_cha_sel = GREEN_LED_SLE; //GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase2_led_drv2_cha_sel = 0x00; - uint8_t phase2_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase2_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase2_ldr2_cur = 0; -// uint8_t phase2_of_idac1_cur = 0; -// uint8_t phase2_of_idac2_cur = 0; - uint8_t phase2_ad_inr_ctrl = 3; - uint8_t phase2_ad_of_idac_ctrl = 0; -// uint8_t phase2_afe_offset = 0; - uint8_t phase2_led_en = 1; /* phase1 led enable*/ - - uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ + hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); + hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); + hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); - - uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase3_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase3_led_drv1_cha_sel = 0; //RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase3_led_drv2_cha_sel = 0; - uint8_t phase3_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase3_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase3_ldr2_cur = 0; -// uint8_t phase3_of_idac1_cur = 0; -// uint8_t phase3_of_idac2_cur = 0; - uint8_t phase3_ad_inr_ctrl = 3; - uint8_t phase3_ad_of_idac_ctrl = 0; -// uint8_t phase3_afe_offset = 0; - uint8_t phase3_led_en = 1; /* phase1 led enable*/ - - uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ + hx3695_write_reg(0X5c, 0x02); + hx3695_delay_ms(1); + hx3695_write_reg(0X5c, 0x00); +} - - uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase4_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase4_led_drv1_cha_sel = RED_LED_SLE; //0x20 //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase4_led_drv2_cha_sel = 0; - uint8_t phase4_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase4_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase4_ldr2_cur = 0; -// uint8_t phase4_of_idac1_cur = 0; -// uint8_t phase4_of_idac2_cur = 0; - uint8_t phase4_ad_inr_ctrl = 3; - uint8_t phase4_ad_of_idac_ctrl = 0; -// uint8_t phase4_afe_offset = 0; - uint8_t phase4_led_en = 1; /* phase1 led enable*/ - - uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase5_led_drv1_cha_sel = 0x00; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase5_led_drv2_cha_sel = 0; - uint8_t phase5_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */ - uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase5_ldr2_cur = 0; -// uint8_t phase5_of_idac1_cur = 0; -// uint8_t phase5_of_idac2_cur = 0; - uint8_t phase5_ad_inr_ctrl = 3; - uint8_t phase5_ad_of_idac_ctrl = 0; -// uint8_t phase5_afe_offset = 0; - uint8_t phase5_led_en = 1; /* phase1 led enable*/ - - uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase6_led_drv1_cha_sel = IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase6_led_drv2_cha_sel = 0; - uint8_t phase6_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */ - uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase6_ldr2_cur = 0; -// uint8_t phase6_of_idac1_cur = 0; -// uint8_t phase6_of_idac2_cur = 0; - uint8_t phase6_ad_inr_ctrl = 3; - uint8_t phase6_ad_of_idac_ctrl = 0; -// uint8_t phase6_afe_offset = 0; - uint8_t phase6_led_en = 1; /* phase1 led enable*/ - - uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase7_led_drv2_cha_sel = 0; - uint8_t phase7_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */ - uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase7_ldr2_cur = 0; -// uint8_t phase7_of_idac1_cur = 0; -// uint8_t phase7_of_idac2_cur = 0; - uint8_t phase7_ad_inr_ctrl = 3; - uint8_t phase7_ad_of_idac_ctrl = 0; -// uint8_t phase7_afe_offset = 0; - uint8_t phase7_led_en = 1; /* phase1 led enable*/ - - uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase8_led_drv1_cha_sel = IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase8_led_drv2_cha_sel = 0; - uint8_t phase8_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */ - uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase8_ldr1_cur = 32; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase8_ldr2_cur = 0; -// uint8_t phase8_of_idac1_cur = 0; -// uint8_t phase8_of_idac2_cur = 0; - uint8_t phase8_ad_inr_ctrl = 3; - uint8_t phase8_ad_of_idac_ctrl = 0; -// uint8_t phase8_afe_offset = 0; - uint8_t phase8_led_en = 1; /* phase1 led enable*/ - - uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ; - 4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ - - uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ; - 4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */ - - uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/ - - uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ - - uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ - - uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ; - 4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */ - - hx3695_delay_ms(10); - - hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6 - hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8> - hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> - - hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); - hx3695_write_reg(0X2d, phase7_8_internal); - hx3695_write_reg(0X2e, 0x33);// gpio ctrl - hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay)); - hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); - hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); - - - hx3695_write_reg(0X31, (led_on_time<<4| 0x00)); - hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置； - hx3695_write_reg(0X34, 0x00);// 中断特殊配置； - hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置； - hx3695_write_reg(0X38, 0x00); - - hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); - hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); - hx3695_write_reg(0X3c, (phase5_inner_avg | (phase6_inner_avg<<4))); - hx3695_write_reg(0X3d, (phase7_inner_avg | (phase8_inner_avg<<4))); - hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); - hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num ); - - hx3695_write_reg(0X43, phase1_mux_sel); - hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); - hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase1_als_offset_idac); - hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase2_mux_sel); - hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); - hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase2_als_offset_idac); - hx3695_write_reg(0X48, phase2_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4); - -//phase3 sel - - hx3695_write_reg(0X43, phase3_mux_sel); - hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); - hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase3_als_offset_idac); - hx3695_write_reg(0X48, phase3_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4); - -//phase4 sel - - hx3695_write_reg(0X43, phase4_mux_sel); - hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); - hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase4_als_offset_idac); - hx3695_write_reg(0X48, phase4_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4); - - hx3695_write_reg(0X43, phase5_mux_sel); - hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); - hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase5_als_offset_idac); - hx3695_write_reg(0X48, phase5_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase6_mux_sel); - hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); - hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase6_als_offset_idac); - hx3695_write_reg(0X48, phase6_led_offset_idac); -// hx3695_write_reg(0X48, phase6_led_offset_idac); - hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase7_mux_sel); - hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); - hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase7_als_offset_idac); - hx3695_write_reg(0X48, phase7_led_offset_idac); -// hx3695_write_reg(0X48, phase7_led_offset_idac); - hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase8_mux_sel); - hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); - hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase8_als_offset_idac); - hx3695_write_reg(0X48, phase8_led_offset_idac); -// hx3695_write_reg(0X48, phas8_led_offset_idac); - hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4); - - -// analog circuit cfg - hx3695_write_reg(0X60, 0x14); // - hx3695_write_reg(0X61, 0xf0); - hx3695_write_reg(0X62, 0x22); - hx3695_write_reg(0X63, 0x15); - - hx3695_write_reg(0X64, 0x08); - hx3695_write_reg(0X65, 0x88); //bug - - hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30 - hx3695_write_reg(0X67, 0x23); - hx3695_write_reg(0X68, 0x46); - hx3695_write_reg(0X69, 0x42); - - hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg - hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable - - hx3695_write_reg(0X6a, 0X0f); - hx3695_write_reg(0X6b, 0X22); - hx3695_write_reg(0X6c, 0X00); - hx3695_write_reg(0X6d, 0X37); - hx3695_write_reg(0X6e, 0X82); - hx3695_write_reg(0X6f, 0X00); -/////////FIFO and adc conversion ready config//////// -/////////FIFO and adc conversion ready config//////// -#if defined(PPG_INT_MODE) - hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ bits<7> fifo enble - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X38, 0x08); // int sel,00=close almost full int,04=enable almost full int -#elif defined(INT_MODE) //(FIFO_ALL_MOST_FULL) - hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ - bits<7> fifo enble - hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark - hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int - -#else - hx3695_write_reg(0X1b, 0x91); - hx3695_write_reg(0X36, 0x00); - - hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int - -#endif - - - hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); - hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); - hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) ); - hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); - - hx3695_write_reg(0X5c, 0x02);//soft reset - hx3695_delay_ms(5); - hx3695_write_reg(0X5c, 0x00);//release -// uint8_t fifo_data_temp[3] = {0}; -// hx3695_brust_read_reg(0x22, fifo_data_temp, 3); - read_fifo_first_flg = 1; - return ; - -} -#endif - -#ifdef HRV_ALG_LIB -// HRV模式下 初始化配置 -void hx3695_hrv_ppg_init(void) //20200615 ericy ppg fs=25hz, phase3 conversion ready interupt en -{ - uint16_t sample_rate = 125; /*config the data rate of chip alps2_fm ,uint is Hz*/ - uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */ - - uint8_t adc_rst_post_num=0; /* 00=16,01=32,10=64,11=128*/ - uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ - uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/ - uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/ - uint8_t phase7_8_internal = 0; /* phase7 and phase8 prf internal cfg */ - - uint16_t fifo_watermark= 164 ; - uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase5_enable = 0; /*phase5_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase6_enable = 0; /*phase6_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase7_enable = 0; /*phase7_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase8_enable = 0; /*phase8_enable , 1 mean enable ; 0 mean disable */ - - uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - - uint8_t phase1_mux_sel = 0; /* sel phase1*/ - uint8_t phase2_mux_sel = 1; /* sel phase2*/ - uint8_t phase3_mux_sel = 2; /* sel phase3*/ - uint8_t phase4_mux_sel = 3; /* sel phase4*/ - uint8_t phase5_mux_sel = 4; /* sel phase5*/ - uint8_t phase6_mux_sel = 5; /* sel phase6*/ - uint8_t phase7_mux_sel = 6; /* sel phase7*/ - uint8_t phase8_mux_sel = 7; /* sel phase8*/ - - - uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase1_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase1_led_drv1_cha_sel = 0X10; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */ - uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */ - uint8_t phase1_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase1_ldr2_cur = 0; -// uint8_t phase1_of_idac1_cur = 0; -// uint8_t phase1_of_idac2_cur = 0; - uint8_t phase1_ad_inr_ctrl = 3; - uint8_t phase1_ad_of_idac_ctrl = 0; -// uint8_t afe_offset = 0; - uint8_t phase1_led_en = 1; /* phase1 led enable*/ - - uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - - - uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase2_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase2_led_drv1_cha_sel = 0; //GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase2_led_drv2_cha_sel = 0; - uint8_t phase2_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase2_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase2_ldr2_cur = 0; -// uint8_t phase2_of_idac1_cur = 0; -// uint8_t phase2_of_idac2_cur = 0; - uint8_t phase2_ad_inr_ctrl = 3; - uint8_t phase2_ad_of_idac_ctrl = 0; -// uint8_t phase2_afe_offset = 0; - uint8_t phase2_led_en = 1; /* phase1 led enable*/ - - uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - - uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase3_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase3_led_drv1_cha_sel = 0x08; //0x40 //RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase3_led_drv2_cha_sel = 0; - uint8_t phase3_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase3_ldr1_cur = 15; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase3_ldr2_cur = 0; -// uint8_t phase3_of_idac1_cur = 0; -// uint8_t phase3_of_idac2_cur = 0; - uint8_t phase3_ad_inr_ctrl = 3; - uint8_t phase3_ad_of_idac_ctrl = 0; -// uint8_t phase3_afe_offset = 0; - uint8_t phase3_led_en = 1; /* phase1 led enable*/ - - uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - - uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase4_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase4_led_drv1_cha_sel = 0; //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase4_led_drv2_cha_sel = 0; - uint8_t phase4_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase4_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase4_ldr2_cur = 0; -// uint8_t phase4_of_idac1_cur = 0; -// uint8_t phase4_of_idac2_cur = 0; - uint8_t phase4_ad_inr_ctrl = 3; - uint8_t phase4_ad_of_idac_ctrl = 0; -// uint8_t phase4_afe_offset = 0; - uint8_t phase4_led_en = 1; /* phase1 led enable*/ - - uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase5_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase5_led_drv2_cha_sel = 0; - uint8_t phase5_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; */ - uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase5_ldr2_cur = 0; -// uint8_t phase5_of_idac1_cur = 0; -// uint8_t phase5_of_idac2_cur = 0; - uint8_t phase5_ad_inr_ctrl = 3; - uint8_t phase5_ad_of_idac_ctrl = 0; -// uint8_t phase5_afe_offset = 0; - uint8_t phase5_led_en = 1; /* phase1 led enable*/ - - uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase6_led_drv2_cha_sel = 0; - uint8_t phase6_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; */ - uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase6_ldr2_cur = 0; -// uint8_t phase6_of_idac1_cur = 0; -// uint8_t phase6_of_idac2_cur = 0; - uint8_t phase6_ad_inr_ctrl = 3; - uint8_t phase6_ad_of_idac_ctrl = 0; -// uint8_t phase6_afe_offset = 0; - uint8_t phase6_led_en = 1; /* phase1 led enable*/ - - uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase7_led_drv2_cha_sel = 0; - uint8_t phase7_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; */ - uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase7_ldr2_cur = 0; -// uint8_t phase7_of_idac1_cur = 0; -// uint8_t phase7_of_idac2_cur = 0; - uint8_t phase7_ad_inr_ctrl = 3; - uint8_t phase7_ad_of_idac_ctrl = 0; -// uint8_t phase7_afe_offset = 0; - uint8_t phase7_led_en = 1; /* phase1 led enable*/ - - uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase8_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase8_led_drv2_cha_sel = 0; - uint8_t phase8_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; */ - uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase8_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase8_ldr2_cur = 0; -// uint8_t phase8_of_idac1_cur = 0; -// uint8_t phase8_of_idac2_cur = 0; - uint8_t phase8_ad_inr_ctrl = 3; - uint8_t phase8_ad_of_idac_ctrl = 0; -// uint8_t phase8_afe_offset = 0; - uint8_t phase8_led_en = 1; /* phase1 led enable*/ - - uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ; - 4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ - - uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ; - 4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */ - - uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/ - - uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ - - uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ - - uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ; - 4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */ - - hx3695_delay_ms(10); - - hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6 - hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8> - hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> - - hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); - hx3695_write_reg(0X2d, phase7_8_internal); - hx3695_write_reg(0X2e, 0x33);// gpio ctrl - hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay)); - hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); - hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); - - - hx3695_write_reg(0X31, (led_on_time<<4| 0x00)); - hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置； - hx3695_write_reg(0X34, 0x00);// 中断特殊配置； - hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置； - hx3695_write_reg(0X38, 0x00); - - hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); - hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); - hx3695_write_reg(0X3c, (phase5_inner_avg | (phase6_inner_avg<<4))); - hx3695_write_reg(0X3d, (phase7_inner_avg | (phase8_inner_avg<<4))); - hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); - hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num ); - - hx3695_write_reg(0X43, phase1_mux_sel); - hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); - hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase1_als_offset_idac); - hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase2_mux_sel); - hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); - hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase2_als_offset_idac); - hx3695_write_reg(0X48, phase2_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4); - -//phase3 sel - - hx3695_write_reg(0X43, phase3_mux_sel); - hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); - hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase3_als_offset_idac); - hx3695_write_reg(0X48, phase3_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4); - -//phase4 sel - - hx3695_write_reg(0X43, phase4_mux_sel); - hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); - hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase4_als_offset_idac); - hx3695_write_reg(0X48, phase4_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4); - - hx3695_write_reg(0X43, phase5_mux_sel); - hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); - hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase5_als_offset_idac); - hx3695_write_reg(0X48, phase5_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase6_mux_sel); - hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); - hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase6_als_offset_idac); - hx3695_write_reg(0X48, phase6_led_offset_idac); -// hx3695_write_reg(0X48, phase6_led_offset_idac); - hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase7_mux_sel); - hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); - hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase7_als_offset_idac); - hx3695_write_reg(0X48, phase7_led_offset_idac); -// hx3695_write_reg(0X48, phase7_led_offset_idac); - hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase8_mux_sel); - hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); - hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase8_als_offset_idac); - hx3695_write_reg(0X48, phase8_led_offset_idac); -// hx3695_write_reg(0X48, phas8_led_offset_idac); - hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4); - - -// analog circuit cfg - hx3695_write_reg(0X60, 0x14); // - hx3695_write_reg(0X61, 0xf0); - hx3695_write_reg(0X62, 0x22); - hx3695_write_reg(0X63, 0x15); - - hx3695_write_reg(0X64, 0x08); - hx3695_write_reg(0X65, 0x88); //bug - - hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30 - hx3695_write_reg(0X67, 0x23); - hx3695_write_reg(0X68, 0x46); - hx3695_write_reg(0X69, 0x42); - - hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg - hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable - - hx3695_write_reg(0X6a, 0X0f); - hx3695_write_reg(0X6b, 0X22); - hx3695_write_reg(0X6c, 0X00); - hx3695_write_reg(0X6d, 0X37); - hx3695_write_reg(0X6e, 0X82); - hx3695_write_reg(0X6f, 0X00); -/////////FIFO and adc conversion ready config//////// -/////////FIFO and adc conversion ready config//////// -#if defined(PPG_INT_MODE) - hx3695_write_reg(0X1b, 0x00);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ - bits<7> fifo enble - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X38, 0x08); // int sel,00=close almost full int,04=enable almost full int -#elif defined(INT_MODE) //(FIFO_ALL_MOST_FULL) - hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ - bits<7> fifo enble - hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark - hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int - -#else - hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ - bits<7> fifo enble - hx3695_write_reg(0X36, 0x00); - - hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int - -#endif - - - hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); - hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); - hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) ); - hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); - - hx3695_write_reg(0X5c, 0x02);//soft reset - hx3695_delay_ms(5); - hx3695_write_reg(0X5c, 0x00);//release -// uint8_t fifo_data_temp[3] = {0}; -// hx3695_brust_read_reg(0x22, fifo_data_temp, 3); - read_fifo_first_flg = 1; - return ; -} -#endif - -#ifdef CHECK_TOUCH_LIB -void hx3695_check_touch_init(void) // -{ - uint16_t sample_rate = 5; /*config the data rate of chip alps2_fm ,uint is Hz*/ - uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */ - - uint16_t fifo_watermark= 250 ; - uint8_t adc_rst_post_num= 0; /* 00=16,01=32,10=64,11=128*/ - uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ - uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/ - uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/ - uint8_t phase7_8_internal = 0; //0x18; /* phase7 and phase8 prf internal cfg */ - -// uint16_t thred_value = 32500; - - uint8_t phase1_enable = 0; /*phase1_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase2_enable = 0; /*phase2_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase3_enable = 0; /*phase3_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase4_enable = 0; /*phase4_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase5_enable = 0; /*phase5_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase6_enable = 0; /*phase6_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase7_enable = 1; /*phase7_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ - - uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - - uint8_t phase1_mux_sel = 0; /* sel phase1*/ - uint8_t phase2_mux_sel = 1; /* sel phase2*/ - uint8_t phase3_mux_sel = 2; /* sel phase3*/ - uint8_t phase4_mux_sel = 3; /* sel phase4*/ - uint8_t phase5_mux_sel = 4; /* sel phase5*/ - uint8_t phase6_mux_sel = 5; /* sel phase6*/ - uint8_t phase7_mux_sel = 6; /* sel phase7*/ - uint8_t phase8_mux_sel = 7; /* sel phase8*/ - - - uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase1_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */ - uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */ - uint8_t phase1_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase1_ldr2_cur = 0; -// uint8_t phase1_of_idac1_cur = 0; -// uint8_t phase1_of_idac2_cur = 0; - uint8_t phase1_ad_inr_ctrl = 3; - uint8_t phase1_ad_of_idac_ctrl = 0; -// uint8_t afe_offset = 0; - uint8_t phase1_led_en = 1; /* phase1 led enable*/ - - uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - - - uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase2_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase2_led_drv1_cha_sel = 0; //GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase2_led_drv2_cha_sel = 0; - uint8_t phase2_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase2_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase2_ldr2_cur = 0; -// uint8_t phase2_of_idac1_cur = 0; -// uint8_t phase2_of_idac2_cur = 0; - uint8_t phase2_ad_inr_ctrl = 3; - uint8_t phase2_ad_of_idac_ctrl = 0; -// uint8_t phase2_afe_offset = 0; - uint8_t phase2_led_en = 1; /* phase1 led enable*/ - - uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - - uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase3_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase3_led_drv1_cha_sel = 0; //RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase3_led_drv2_cha_sel = 0; - uint8_t phase3_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase3_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase3_ldr2_cur = 0; -// uint8_t phase3_of_idac1_cur = 0; -// uint8_t phase3_of_idac2_cur = 0; - uint8_t phase3_ad_inr_ctrl = 3; - uint8_t phase3_ad_of_idac_ctrl = 0; -// uint8_t phase3_afe_offset = 0; - uint8_t phase3_led_en = 1; /* phase1 led enable*/ - - uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - - uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase4_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase4_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase4_led_drv2_cha_sel = 0; - uint8_t phase4_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase4_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase4_ldr2_cur = 0; -// uint8_t phase4_of_idac1_cur = 0; -// uint8_t phase4_of_idac2_cur = 0; - uint8_t phase4_ad_inr_ctrl = 3; - uint8_t phase4_ad_of_idac_ctrl = 0; -// uint8_t phase4_afe_offset = 0; - uint8_t phase4_led_en = 1; /* phase1 led enable*/ - - uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase5_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase5_led_drv2_cha_sel = 0; - uint8_t phase5_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */ - uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase5_ldr2_cur = 0; -// uint8_t phase5_of_idac1_cur = 0; -// uint8_t phase5_of_idac2_cur = 0; - uint8_t phase5_ad_inr_ctrl = 3; - uint8_t phase5_ad_of_idac_ctrl = 0; -// uint8_t phase5_afe_offset = 0; - uint8_t phase5_led_en = 1; /* phase1 led enable*/ - - uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase6_tia_cap = SPO2_PD; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase6_led_drv2_cha_sel = 0; - uint8_t phase6_pd_sel = 4; /* 1 = pd1; 2 = pd2; */ - uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase6_ldr2_cur = 0; -// uint8_t phase6_of_idac1_cur = 0; -// uint8_t phase6_of_idac2_cur = 0; - uint8_t phase6_ad_inr_ctrl = 3; - uint8_t phase6_ad_of_idac_ctrl = 0; -// uint8_t phase6_afe_offset = 0; - uint8_t phase6_led_en = 1; /* phase1 led enable*/ - - uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase7_led_drv2_cha_sel = 0; - uint8_t phase7_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */ - uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase7_ldr2_cur = 0; -// uint8_t phase7_of_idac1_cur = 0; -// uint8_t phase7_of_idac2_cur = 0; - uint8_t phase7_ad_inr_ctrl = 3; - uint8_t phase7_ad_of_idac_ctrl = 0; -// uint8_t phase7_afe_offset = 0; - uint8_t phase7_led_en = 1; /* phase1 led enable*/ - - uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase8_led_drv1_cha_sel = IR_LED_SLE;//0x40; //IR_LED_SLE /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase8_led_drv2_cha_sel = 0; - uint8_t phase8_pd_sel = SPO2_PD; /* 1 = pd1; 2 = pd2; */ - uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase8_ldr1_cur = 32; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase8_ldr2_cur = 0; -// uint8_t phase8_of_idac1_cur = 0; -// uint8_t phase8_of_idac2_cur = 0; - uint8_t phase8_ad_inr_ctrl = 3; - uint8_t phase8_ad_of_idac_ctrl = 0; -// uint8_t phase8_afe_offset = 0; - uint8_t phase8_led_en = 1; /* phase1 led enable*/ - - uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ; - 4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ - - uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ; - 4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */ - - uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/ - - uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ - - uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ - - uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ; - 4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */ - - hx3695_delay_ms(10); - - hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6 - hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8> - hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> - - hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); - hx3695_write_reg(0X2d, phase7_8_internal); - hx3695_write_reg(0X2e, 0x33);// gpio ctrl - hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay)); - hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); - hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); - - - hx3695_write_reg(0X31, (led_on_time<<4| 0x00)); - hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置； - hx3695_write_reg(0X34, 0x00);// 中断特殊配置； - hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置； - hx3695_write_reg(0X38, 0x00); - - hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); - hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); - hx3695_write_reg(0X3c, (phase5_inner_avg | (phase6_inner_avg<<4))); - hx3695_write_reg(0X3d, (phase7_inner_avg | (phase8_inner_avg<<4))); - hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); - hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num ); - - hx3695_write_reg(0X43, phase1_mux_sel); - hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); - hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase1_als_offset_idac); - hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase2_mux_sel); - hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); - hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase2_als_offset_idac); - hx3695_write_reg(0X48, phase2_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4); - -//phase3 sel - - hx3695_write_reg(0X43, phase3_mux_sel); - hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); - hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase3_als_offset_idac); - hx3695_write_reg(0X48, phase3_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4); - -//phase4 sel - - hx3695_write_reg(0X43, phase4_mux_sel); - hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); - hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase4_als_offset_idac); - hx3695_write_reg(0X48, phase4_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4); - - hx3695_write_reg(0X43, phase5_mux_sel); - hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); - hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase5_als_offset_idac); - hx3695_write_reg(0X48, phase5_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase6_mux_sel); - hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); - hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase6_als_offset_idac); - hx3695_write_reg(0X48, phase6_led_offset_idac); -// hx3695_write_reg(0X48, phase6_led_offset_idac); - hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase7_mux_sel); - hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); - hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase7_als_offset_idac); - hx3695_write_reg(0X48, phase7_led_offset_idac); -// hx3695_write_reg(0X48, phase7_led_offset_idac); - hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase8_mux_sel); - hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); - hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase8_als_offset_idac); - hx3695_write_reg(0X48, phase8_led_offset_idac); -// hx3695_write_reg(0X48, phas8_led_offset_idac); - hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4); - - -// analog circuit cfg - hx3695_write_reg(0X60, 0x14); // - hx3695_write_reg(0X61, 0xf0); - hx3695_write_reg(0X62, 0x22); - hx3695_write_reg(0X63, 0x15); - - hx3695_write_reg(0X64, 0x08); - hx3695_write_reg(0X65, 0x88); //bug - - hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30 - hx3695_write_reg(0X67, 0x23); - hx3695_write_reg(0X68, 0x46); - hx3695_write_reg(0X69, 0x42); - - hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg - hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable - - hx3695_write_reg(0X6a, 0X0f); - hx3695_write_reg(0X6b, 0X22); - hx3695_write_reg(0X6c, 0X00); - hx3695_write_reg(0X6d, 0X37); - hx3695_write_reg(0X6e, 0X82); - hx3695_write_reg(0X6f, 0X00); -/////////FIFO and adc conversion ready config//////// -/////////FIFO and adc conversion ready config//////// -#if defined(PPG_INT_MODE) - hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ - bits<7> fifo enble - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int -#elif defined(INT_MODE) //(FIFO_ALL_MOST_FULL) - hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ - bits<7> fifo enble - hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark - hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int - -#else - hx3695_write_reg(0X1b, 0x92); - - hx3695_write_reg(0X36, 0x00); - - hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int - -#endif - - - hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); - hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); - hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) ); - hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); - - hx3695_write_reg(0X5c, 0x02);//soft reset - hx3695_delay_ms(5); - hx3695_write_reg(0X5c, 0x00);//release -// uint8_t fifo_data_temp[3] = {0}; -// hx3695_brust_read_reg(0x22, fifo_data_temp, 3); - read_fifo_first_flg = 1; - return ; -} -#endif - -// 初始化调用入口函数 -bool hx3695_init(WORK_MODE_T mode) -{ - // hx3695_msg_callback_t func; - - - //TYHX_LOG("this chip hx3695_init mode: %d !! \r\n", mode); - - hx3695_ppg_on(); - - Efuse_judge(); //MC前后芯片判断 - // Efuse_Mode_Check(); - work_mode_flag = mode; - hx3695_data_reset(); - hx3695_vin_check(3800); - switch (work_mode_flag) - { - case HRS_MODE: - //TYHX_LOG(" hx3695_init mode : HRS_MODE \n"); -#ifdef HRS_ALG_LIB - tyhx_hrs_set_living(1, 15, 30); - if(hx3695_hrs_enable()== SENSOR_OP_FAILED) - { - return false; - } -#endif - break; - - case LIVING_MODE: -#ifdef CHECK_LIVING_LIB - if(hx3695_hrs_enable()== SENSOR_OP_FAILED) - { - return false; - } -#endif - break; - - case SPO2_MODE: -#ifdef SPO2_DATA_CALI -// hx3695_spo2_data_cali_init(); -#endif - -#ifdef SPO2_ALG_LIB - tyhx_spo2_para_usuallyadjust(SPO2_LOW_XCORR_THRE,SPO2_LOW_SNR_THRE,COUNT_BLOCK_NUM,SPO2_BASE_LINE_INIT,SPO2_SLOPE,SPO2_GSEN_POW_THRE); - tyhx_spo2_para_barelychange(MEAN_NUM,SOP2_DEGLITCH_THRE,SPO2_REMOVE_JUMP_THRE, \ - SPO2_LOW_CLIP_END_TIME,SPO2_LOW_CLIP_DN,SPO2_NORMAL_CLIP_DN, \ - IR_AC_TOUCH_THRE,IR_FFT_POW_THRE,SPO2_CALI,SLOPE_PARA_MAX,SLOPE_PARA_MIN); - tyhx_spo2_set_living(1, 7, 20); - if(hx3695_spo2_enable()== SENSOR_OP_FAILED) - { - return false; - } -#endif - break; - - case HRSPO2_MODE: -#if defined(HRS_ALG_LIB) && defined (SPO2_ALG_LIB) - tyhx_spo2_para_usuallyadjust(SPO2_LOW_XCORR_THRE,SPO2_LOW_SNR_THRE,COUNT_BLOCK_NUM,SPO2_BASE_LINE_INIT,SPO2_SLOPE,SPO2_GSEN_POW_THRE); - tyhx_spo2_para_barelychange(MEAN_NUM,SOP2_DEGLITCH_THRE,SPO2_REMOVE_JUMP_THRE, \ - SPO2_LOW_CLIP_END_TIME,SPO2_LOW_CLIP_DN,SPO2_NORMAL_CLIP_DN, \ - IR_AC_TOUCH_THRE,IR_FFT_POW_THRE,SPO2_CALI,SLOPE_PARA_MAX,SLOPE_PARA_MIN); - if(hx3695_spo2_enable()== SENSOR_OP_FAILED) - { - return false; - } -#endif - - case HRV_MODE: -#ifdef HRV_ALG_LIB - if(hx3695_hrv_enable()== SENSOR_OP_FAILED) - { - return false; - } -#endif - break; - - case WEAR_MODE: -#ifdef CHECK_TOUCH_LIB - if(hx3695_check_touch_enable()== SENSOR_OP_FAILED) - { - return false; - } -#endif - break; - - case FT_LEAK_LIGHT_MODE: - if (!hx3695_chip_check()) - { - AGC_LOG("hx3695 check id failed!\r\n"); - return false; - } - //TYHX_LOG(" hx3695_init mode : LEAK_LIGHT_MODE \n"); - hx3695_factroy_test(LEAK_LIGHT_TEST); - - // func = hx3695_get_send_msg_callback_func(); - // if(func != NULL) - // { - // func(HX3695_MSG_TYPE_LEAKLIGHT_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t)); - // } - break; - - case FT_GRAY_CARD_MODE: - if (!hx3695_chip_check()) - { - AGC_LOG("hx3695 check id failed!\r\n"); - return false; - } - //TYHX_LOG(" hx3695_init mode : GRAY_CARD_MODE \n"); - hx3695_factroy_test(GRAY_CARD_TEST); - - // func = hx3695_get_send_msg_callback_func(); - // if(func != NULL) - // { - // func(HX3695_MSG_TYPE_GRAYCARD_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t)); - // } - break; - - case FT_INT_TEST_MODE: - hx3695_factroy_test(FT_INT_TEST); - break; - - case FT_SINGLE_CHECK_MODE: - if (!hx3695_chip_check()) - { - AGC_LOG("hx3695 check id failed!\r\n"); - return false; - } - hx3695_factroy_test(SINGLE_CHECK_TEST); - break; - - case FT_LED_OFF_MODE: - //TYHX_LOG(" hx3695_init mode : FT_LED_OFF_MODE \n"); - hx3695_factroy_test(LED_OFF_TEST); - break; - - case FT_WEAR_MODE: - hx3695_factroy_test(WEAR_MODE_TEST); - break; - // case NEW_PPG_TEST_MODE: - // hx3695_factroy_test(NEW_PPG_TEST); - // break; - case LAB_TEST_MODE: -#ifdef LAB_TEST - if(hx3695_lab_test_enable()== SENSOR_OP_FAILED) - { - return false; - } -#endif - break; - - default: - break; - } - return true; -} - -void hx3695_agc_Int_handle(void) -{ - //TYHX_LOG(" hx3695_init mode : HRS_MODE \n"); - switch (work_mode_flag) - { - case HRS_MODE: -#ifdef HRS_ALG_LIB - PPG_hrs_agc(); -#endif - break; - - case LIVING_MODE: -#ifdef HRS_ALG_LIB - PPG_hrs_agc(); -#endif - break; - - case HRV_MODE: -#ifdef HRV_ALG_LIB - PPG_hrv_agc(); -#endif - break; - - case SPO2_MODE: -#ifdef SPO2_ALG_LIB - PPG_spo2_agc(); -#endif - break; - - case HRSPO2_MODE: -#if defined(HRS_ALG_LIB) && defined (SPO2_ALG_LIB) - PPG_spo2_agc(); -#endif - - case LAB_TEST_MODE: -#ifdef LAB_TEST - hx3695_lab_test_Int_handle(); -#endif - - default: - break; - } -} - -void agc_timeout_handler(void * p_context) -{ - hx3695_agc_Int_handle(); - -#if defined(GSEN_40MS_TIMMER) - hx3695_gesensor_Int_handle(); -#endif -} - -static uint32_t ft_ppg_green = 0; -static uint32_t ft_ppg_iir = 0; - -void hx3695_factory_test_process(uint8_t data[], uint8_t mode, uint8_t* ppg_src) -{ - extern bool factory_test_flag; - extern bool factory_test_sensor_on; - extern bool factory_test_aging; - - if(factory_test_flag == false) return; - if(factory_test_sensor_on == true ) return; - - static uint8_t ppg_data[15] = {0}; - uint32_t test = 0; -// uint32_t green = 0; -// uint32_t red = 0; -// uint32_t iir = 0; - - if(data != NULL && ppg_src == NULL) - { - memcpy(ppg_data, data, 3); - return; - } -// switch(mode) -// { -// case APP_FACTORY_TEST_HR_START: -// ppg_data[3] = *(ppg_src + 3); -// ppg_data[4] = *(ppg_src + 2); -// ppg_data[5] = *(ppg_src + 1); -// ppg_data[6] = *(ppg_src + 0); - -// ppg_data[7] = *(ppg_src + 7); -// ppg_data[8] = *(ppg_src + 6); -// ppg_data[9] = *(ppg_src + 5); -// ppg_data[10] = *(ppg_src + 4); - -// ppg_data[11] = *(ppg_src + 11); -// ppg_data[12] = *(ppg_src + 10); -// ppg_data[13] = *(ppg_src + 9); -// ppg_data[14] = *(ppg_src + 8); - -// factory_test_send_data(ppg_data, 15); -// break; -// case APP_FACTORY_TEST_SPO2_START: -// ppg_data[3] = *(ppg_src + 3); -// ppg_data[4] = *(ppg_src + 2); -// ppg_data[5] = *(ppg_src + 1); -// ppg_data[6] = *(ppg_src + 0); - -// ppg_data[7] = *(ppg_src + 7); -// ppg_data[8] = *(ppg_src + 6); -// ppg_data[9] = *(ppg_src + 5); -// ppg_data[10] = *(ppg_src + 4); - -// ppg_data[11] = *(ppg_src + 11); -// ppg_data[12] = *(ppg_src + 10); -// ppg_data[13] = *(ppg_src + 9); -// ppg_data[14] = *(ppg_src + 8); - -// factory_test_send_data(ppg_data, 15); -// break; -// case APP_FACTORY_TEST_LEAKING_START: -// // memcpy((void *)&ppg_data[3], ppg_src, 12); - -// ppg_data[3] = *(ppg_src + 3); -// ppg_data[4] = *(ppg_src + 2); -// ppg_data[5] = *(ppg_src + 1); -// ppg_data[6] = *(ppg_src + 0); - -// ppg_data[7] = *(ppg_src + 7); -// ppg_data[8] = *(ppg_src + 6); -// ppg_data[9] = *(ppg_src + 5); -// ppg_data[10] = *(ppg_src + 4); - -// ppg_data[11] = *(ppg_src + 11); -// ppg_data[12] = *(ppg_src + 10); -// ppg_data[13] = *(ppg_src + 9); -// ppg_data[14] = *(ppg_src + 8); - - -// gui_send_message_by_data(MSG_FACTORY_TEST_UPDATE_HR, ppg_src, 12); -// if(factory_test_aging) break; -// factory_test_send_data(ppg_data, 15); -// break; -// case APP_FACTORY_TEST_GRAY_CARD: -// { -// // memcpy((void *)&ppg_data[3], ppg_src, 12); -// ppg_data[3] = *(ppg_src + 3); -// ppg_data[4] = *(ppg_src + 2); -// ppg_data[5] = *(ppg_src + 1); -// ppg_data[6] = *(ppg_src + 0); - -// ppg_data[7] = *(ppg_src + 7); -// ppg_data[8] = *(ppg_src + 6); -// ppg_data[9] = *(ppg_src + 5); -// ppg_data[10] = *(ppg_src + 4); - -// ppg_data[11] = *(ppg_src + 11); -// ppg_data[12] = *(ppg_src + 10); -// ppg_data[13] = *(ppg_src + 9); -// ppg_data[14] = *(ppg_src + 8); - -// gui_send_message_by_data(MSG_FACTORY_TEST_UPDATE_HR, ppg_src, 12); -// if(factory_test_aging) break; -// factory_test_send_data(ppg_data, 15); -// } -// break; -// default: -// break; -// } -} - - -typedef struct { - int32_t gr_data_final; - int32_t red_data_final; - int32_t ir_data_final; -} ft_test_result_t; - -void wear_mode_timeout_handler(void * p_context) -{ - if(work_mode_flag == WEAR_MODE) - { - #ifdef CHECK_TOUCH_LIB - hx3695_wear_ppg_Int_handle(); - #endif - } -} - - -void heart_rate_meas_timeout_handler(void * p_context) -{ - //TYHX_LOG(" heart_rate_meas_timeout_handler mode: %d \n", work_mode_flag); - - switch(work_mode_flag) - { - case HRS_MODE: -#ifdef HRS_ALG_LIB - hx3695_hrs_ppg_Int_handle(); -#endif - break; - - case HRV_MODE: -#ifdef HRV_ALG_LIB - hx3695_hrv_ppg_Int_handle(); -#endif - break; - - case SPO2_MODE: -#ifdef SPO2_ALG_LIB - hx3695_spo2_ppg_Int_handle(); -#endif - break; - - case LIVING_MODE: -#ifdef CHECK_LIVING_LIB - hx3695_living_Int_handle(); -#endif - break; - - case HRSPO2_MODE: -#if defined(HRS_ALG_LIB) && defined (SPO2_ALG_LIB) - hx3695_hrspo2_ppg_Int_handle(); -#endif - - case FT_LEAK_LIGHT_MODE: - { - hx3695_factroy_test(LEAK_LIGHT_TEST); - break; - } - break; - - case FT_GRAY_CARD_MODE: - { - FT_RESULTS_t ft_result = hx3695_factroy_test(GRAY_CARD_TEST); - uint8_t data[12] = {0}; - memcpy(data, (void *)&ft_result.gr_data_final, 12); - - // hx3695_factory_test_process(NULL, APP_FACTORY_TEST_GRAY_CARD, data); - } - break; - - default: - break; - } -} - -void hx3695_ppg_Int_handle(void) -{ - hx3695_agc_Int_handle(); -#if defined(INT_MODE) - switch(work_mode_flag) - { - case HRS_MODE: -#ifdef HRS_ALG_LIB - hx3695_hrs_ppg_Int_handle(); -#endif - break; - - case SPO2_MODE: -#ifdef SPO2_ALG_LIB - hx3695_spo2_ppg_Int_handle(); -#endif - break; - - case HRV_MODE: -#ifdef HRV_ALG_LIB - hx3695_hrv_ppg_Int_handle(); -#endif - break; - - case WEAR_MODE: -#ifdef CHECK_TOUCH_LIB - hx3695_wear_ppg_Int_handle(); -#endif - break; - - case LAB_TEST_MODE: -#ifdef LAB_TEST - hx3695_lab_test_Int_handle(); -#endif - - default: - break; - } -#endif -} - -#define HRS_WINDOW_SIZE 5 -static uint8_t hrs_num = 0; -static int32_t sum_hrs = 0; -static int32_t hrs_data[7] = {0}; -static uint8_t left = 0; -static uint8_t right = 0; -static uint8_t avg_hrs = 0; - -static void get_avg_hrs(uint8_t hrs) -{ - - - if (hrs_num >= HRS_WINDOW_SIZE) { - sum_hrs -= hrs_data[left]; - left = (left + 1) % HRS_WINDOW_SIZE; - hrs_num--; - } - - hrs_data[right] = hrs; - sum_hrs += hrs; - right = (right + 1) % HRS_WINDOW_SIZE; - hrs_num++; - - - if (hrs_num > 2) - { - - uint8_t first_idx = left; - int32_t min_hrs = hrs_data[first_idx]; - int32_t max_hrs = hrs_data[first_idx]; - - - for (uint8_t i = 0; i < hrs_num; i++) { - uint8_t current_idx = (left + i) % HRS_WINDOW_SIZE; - uint8_t current_hrs = hrs_data[current_idx]; - - if (current_hrs < min_hrs) { - min_hrs = current_hrs; - } - if (current_hrs > max_hrs) { - max_hrs = current_hrs; - } - } - - uint8_t valid_count = hrs_num - 2; - avg_hrs = (sum_hrs - max_hrs - min_hrs) / valid_count; - - // printf("max_hrs[%d],min_hrs[%d],avg_hrs[%d]\n",max_hrs,min_hrs,avg_hrs); - } -} - - -uint8_t hx3695_get_hrs(void) -{ - return avg_hrs; -} - -uint8_t hx3695_get_spo2(void) -{ - return spo2_result; -} - - -uint8_t hx3695_get_wear_status(void) +void hx3695_set_watermark(ppg_sensor_data_t *ppg_sensor_dat) { - return wear_status; + uint8_t watermark = ppg_sensor_dat->watermark + ppg_sensor_dat->led_activated; + hx3695_write_reg(0X1c, watermark); + hx3695_write_reg(0X5c, 0x02); + hx3695_delay_ms(1); + hx3695_write_reg(0X1b, 0x10); + hx3695_delay_ms(1); + hx3695_write_reg(0X1b, 0x91); + hx3695_write_reg(0X5c, 0x00); + read_fifo_first_flg = 1; } -void hx3695_set_hrs_ble_swtich(uint8_t cmd) +void hx3695_led_control(ppg_sensor_data_t *ppg_sensor_dat, uint8_t index) { - hrs_ble_falg = cmd; - // PRINT("hrs_ble_falg : %d \n",hrs_ble_falg); + if(ppg_sensor_dat->led_data[index].led_state == Activating) + { + hx3695_write_reg(0X26+index,0xbb); + ppg_sensor_dat->led_data[index].led_state = Activated; + } + else if(ppg_sensor_dat->led_data[index].led_state == InActivating) + { + hx3695_write_reg(0X26+index,0x33); + ppg_sensor_dat->led_data[index].led_state = InActivated; + } } -uint8_t hx3695_get_hrs_ble_swtich(void) +void hx3695_updata_sensor(ppg_sensor_data_t *ppg_sensor_dat) { - uint8_t cmd = hrs_ble_falg; - return cmd; + uint8_t ii; + hx3695_set_fs(ppg_sensor_dat); + for(ii=0;ii<4;ii++) + { + hx3695_led_control(ppg_sensor_dat, ii); + } + hx3695_set_watermark(ppg_sensor_dat); } -void hx3695_wearstatus_update(void) +void hx3695_hrs_enable(ppg_sensor_data_t *ppg_sensor_dat) { - if(history_wear_status != wear_status) - { - history_wear_status = wear_status; -#ifdef SUPPORT_CYWEE_SERVICE - // do_cywee_service_check_msg(CYWEE_SERVICE_CMD_WEAR_STATUS_CHANGE,&wear_status); - cywee_wear_status_update(&wear_status); -#endif - } + printf("hx3695_hrs_enable\r\n"); + tyhx_hrs_alg_open(); + ppg_sensor_data.mode = HRS_MODE; + hx3695_ppg_set_mode(PPG_INIT); + #ifdef DOUBLE_GREEN + ppg_sensor_dat->led_activated = 3; + ppg_sensor_dat->fs = 25; + ppg_sensor_dat->watermark = 30; + ppg_sensor_dat->led_data[0].led_state = Activating; + ppg_sensor_dat->led_data[1].led_state = Activating; + ppg_sensor_dat->led_data[2].led_state = InActivating; + ppg_sensor_dat->led_data[3].led_state = Activating; + ppg_sensor_dat->led_data[0].isneed_cal_start = true; + ppg_sensor_dat->led_data[1].isneed_cal_start = true; + ppg_sensor_dat->led_data[2].isneed_cal_start = false; + ppg_sensor_dat->led_data[3].isneed_cal_start = false; + #else + ppg_sensor_dat->led_activated = 2; + ppg_sensor_dat->fs = 25; + ppg_sensor_dat->watermark = 20; + ppg_sensor_dat->led_data[0].led_state = Activating; + ppg_sensor_dat->led_data[1].led_state = InActivating; + ppg_sensor_dat->led_data[2].led_state = InActivating; + ppg_sensor_dat->led_data[3].led_state = Activating; + ppg_sensor_dat->led_data[0].isneed_cal_start = true; + ppg_sensor_dat->led_data[1].isneed_cal_start = false; + ppg_sensor_dat->led_data[2].isneed_cal_start = false; + ppg_sensor_dat->led_data[3].isneed_cal_start = false; + #endif + hx3695_updata_sensor(ppg_sensor_dat); } - //脱腕上报未佩戴信息 -void hx3695_unwearstatus_update(void) -{ - // hx3695_msg_callback_t func = hx3695_get_send_msg_callback_func(); - // if(func != NULL && !uapi_dev_runtime_get_train_status()) - // { - // hrsresult.lastesthrs = 0; - // hrsresult.wearstatus = 0; - // //为了主界面脱腕灵敏；需要增加未佩戴 - // func(HX3695_MSG_TYPE_HRS_UPDATE, &hrsresult, sizeof(FT_CUSTOM_RESULTS_t)); - // func(HX3695_MSG_TYPE_WEARSTAT_UPDATE, &hrsresult,sizeof(FT_CUSTOM_RESULTS_t)); - // func(HX3695_MSG_TYPE_WEARSTAT_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t)); - // func(HX3695_MSG_TYPE_WEARSTAT_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t)); - // } - - if(uapi_dev_runtime_get_train_status()) - { - wear_status = 0; - hx3695_wearstatus_update(); - avg_hrs = 0; - - } -} - - -#ifdef HRS_ALG_LIB -/*TYHX 心率模式下 读取PPG， 默认320ms*/ -hrs_sensor_data_t hrs_s_dat; -//hx3695_results_t alg_results_pre; - -static uint8_t his_wear = 2; -static uint8_t wear_cnt = 0; -// static uint8_t acc_restart_flag = 0; -void hx3695_hrs_ppg_Int_handle(void) +void hx3695_hrsdaily_enable(ppg_sensor_data_t *ppg_sensor_dat) { - uint8_t ii=0; - hrs_results_t alg_results = {MSG_HRS_ALG_NOT_OPEN,0,0,0,0,0,0}; - hrs_wear_msg_code_t hrs_wear_status = MSG_HRS_NO_WEAR; - int32_t *PPG_buf = &(hrs_s_dat.green_data[0]); - int32_t *ir_buf = &(hrs_s_dat.ir_data[0]); - uint8_t *count = &(hrs_s_dat.count); - //int32_t *s_buf = &(ppg_s_data.s_buf[0]); - int16_t gsen_fifo_x_send[32]= {0}; - int16_t gsen_fifo_y_send[32]= {0}; - int16_t gsen_fifo_z_send[32]= {0}; - - HRS_CAL_SET_T cal; - cal = get_hrs_agc_status(); - -#ifdef HR_VECTOR - for(ii=0; ii<8; ii++) - { - PPG_buf_vec[ii] = hrm_input_data[vec_send_cnt+ii]; - gsen_fifo_x_send[ii] = gsen_input_data_x[vec_send_cnt+ii]; - gsen_fifo_y_send[ii] = gsen_input_data_y[vec_send_cnt+ii]; - gsen_fifo_z_send[ii] = gsen_input_data_z[vec_send_cnt+ii]; - } - vec_send_cnt = vec_send_cnt+8; - *count = 8; - tyhx_hrs_alg_send_data(PPG_buf_vec,*count, gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send); - -#else - - if(hx3695_hrs_read(&hrs_s_dat) == 0) - { - return; - } - -#ifndef GSEN_40MS_TIMMER - //readFifoByHrsModule(); -#endif -// DEBUG_PRINTF("\r\nsend jlink cnt=%d\r\n",*count); -/* gsensor 屏蔽 */ -// for(ii=0; ii<*count; ii++) -// { -// #if 0 -// gsen_fifo_x_send[ii] = gsen_fifo_x[32-*count+ii]; -// gsen_fifo_y_send[ii] = gsen_fifo_y[32-*count+ii]; -// gsen_fifo_z_send[ii] = gsen_fifo_z[32-*count+ii]; - -// PRINT("hx3695 gr,ir,gsen:%d/%d %d %d %d %d %d %d\r\n" , -// 1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x[ii],gsen_fifo_y[ii],gsen_fifo_z[ii],cal.Group1_Cur); -// #else -// accel_data_struct_t accel_raw_data = {0}; -// queue_output(&accel_raw_data); -// gsen_fifo_x_send[ii] = accel_raw_data.x; -// gsen_fifo_y_send[ii] = accel_raw_data.y; -// gsen_fifo_z_send[ii] = accel_raw_data.z; -// // PRINT("hx3695 gr,ir,gsen:%d/%d %d %d %d %d %d %d\r\n" , -// // 1+ii,*count,PPG_buf[ii], ir_buf[0], gsen_fifo_x_send[ii], gsen_fifo_y_send[ii], gsen_fifo_z_send[ii], cal.Group1_Cur); -// printf("FFF==> hr PPG_buf : %d, %d, PPG_buf: %d, ir_buf: %d \n", 1+ii, *count, PPG_buf[ii], ir_buf[0]); - -// #endif -// } -// ft_ppg_green = hrs_s_dat.green_data[0]; - // ft_test_result_t result = {0}; - // result.gr_data_final = hrs_s_dat.green_data[0]; - // result.ir_data_final = hrs_s_dat.ir_data[0]; - // hx3695_factory_test_process(NULL, APP_FACTORY_TEST_HR_START, &result); - //PRINT("*count : %d \r\n",*count); - - //count7-9 为捕捉到的绿光值正常数据数量范围,不在此范围,心率数据不准,直接返回. - // if(*count < 7 || *count > 9) - // { - // return; - // } - #ifdef SUPPORT_CYWEE_SERVICE - memset(gsensordata,0.0f,sizeof(gsenson_t) * *count); - - cywee_get_gsensor_data(*count,gsensordata); - - for(ii=0; ii<*count; ii++) - { - // if(gsensordata[ii].x == 0.0f && gsensordata[ii].y == 0.0f && gsensordata[ii].z == 0.0f) - // { - // timeout++; - // if(timeout > 20 && !acc_restart_flag) //避免重复开关gsensor - // { - // do_cywee_service_check_msg(CYWEE_SERVICE_CMD_RESTART_ACC,NULL); - // acc_restart_flag = 1; - // } - // } - // else - // { - // timeout = 0; - // acc_restart_flag = 0; - // } - - if(gsensordata[ii].x == 0 && gsensordata[ii].y == 0 && gsensordata[ii].z == 0) - { - gsen_fifo_x_send[ii] = gsen_fifo_x_send[ii - 1]; - gsen_fifo_y_send[ii] = gsen_fifo_y_send[ii - 1]; - gsen_fifo_z_send[ii] = gsen_fifo_z_send[ii - 1]; - } - else - { - gsen_fifo_x_send[ii] = gsensordata[ii].x * 4096 / 10; - gsen_fifo_y_send[ii] = gsensordata[ii].y * 4096 / 10; - gsen_fifo_z_send[ii] = gsensordata[ii].z * 4096 / 10; - } - factory_data = PPG_buf[ii]; - // cywee_get_gsensor_data(8,gsensordata); - // for(ii=0; ii<*count; ii++) - // { - // if(gsensordata[ii].x == 0.0f && gsensordata[ii].y == 0.0f && gsensordata[ii].z == 0.0f) - // { - // timeout++; - // if(timeout > 20) - // { - // do_cywee_service_check_msg(CYWEE_SERVICE_CMD_RESTART_ACC,NULL); - // } - // } - // else - // { - // timeout = 0; - // } - // // if(ii == 8) - // // { - // // gsen_fifo_x_send[ii] = gsen_fifo_x_send[ii - 1]; - // // gsen_fifo_y_send[ii] = gsen_fifo_y_send[ii - 1]; - // // gsen_fifo_z_send[ii] = gsen_fifo_z_send[ii - 1]; - // // } - // // else - // // { - // if(ii < 9) - // { - // gsen_fifo_x_send[ii] = gsensordata[ii].x * 4096 / 10; - // gsen_fifo_y_send[ii] = gsensordata[ii].y * 4096 / 10; - // gsen_fifo_z_send[ii] = gsensordata[ii].z * 4096 / 10; - // } - - // } - // PRINT("hxdata:%d/%d %d %d %.3f %.3f %.3f %d\r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsensordata[ii].x,gsensordata[ii].y,gsensordata[ii].z,ppg_s_data.green_cur); - //PRINT("hxdata:%d/%d %d %d %.3f %.3f %.3f %d\r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x_send[ii],gsen_fifo_y_send[ii],gsen_fifo_z_send[ii],ppg_s_data.green_cur); - //PRINT("hxdata:%d/%d %d %d %d %d %d %d\r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x_send[ii],gsen_fifo_y_send[ii],gsen_fifo_z_send[ii],ppg_s_data.green_cur); - //PRINT("hxdata:%d/%d %d %d %.3f %.3f %.3f %d\r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsensordata[ii].x,gsensordata[ii].y,gsensordata[ii].z,ppg_s_data.green_cur); - - } -#endif - hrs_wear_status = hx3695_hrs_get_wear_status(); - //PRINT("hrs_wear_status: %d !!\r\n", hrs_wear_status); - - if(hrs_wear_status == MSG_HRS_WEAR) - { - tyhx_hrs_alg_send_data(PPG_buf, *count, gsen_fifo_x_send, gsen_fifo_y_send, - gsen_fifo_z_send, cal.Group1_Ledidac); - } -#endif - - -/*屏蔽*/ -// for(ii=0; ii<*count; ii++) -// { -// #if 0 -// gsen_fifo_x_send[ii] = gsen_fifo_x[32-*count+ii]; -// gsen_fifo_y_send[ii] = gsen_fifo_y[32-*count+ii]; -// gsen_fifo_z_send[ii] = gsen_fifo_z[32-*count+ii]; - -// PRINT("hx3695 gr,ir,gsen:%d/%d %d %d %d %d %d %d\r\n" , -// 1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x[ii],gsen_fifo_y[ii],gsen_fifo_z[ii],cal.Group1_Cur); -// #else -// // accel_data_struct_t accel_raw_data = {0}; -// // queue_output(&accel_raw_data); -// // gsen_fifo_x_send[ii] = accel_raw_data.x; -// // gsen_fifo_y_send[ii] = accel_raw_data.y; -// // gsen_fifo_z_send[ii] = accel_raw_data.z; -// // PRINT("hx3695 gr,ir,gsen:%d/%d %d %d %d %d %d %d hr==%d\r\n" , -// // 1+ii,*count,PPG_buf[ii], ir_buf[0], gsen_fifo_x_send[ii], gsen_fifo_y_send[ii], gsen_fifo_z_send[ii], cal.Group1_Cur,alg_results.hr_result); -// #endif -// } - - uint8_t curr_wear = 1; - //uint8_t last_wear = cwm_get_wear_status(); - - alg_results = tyhx_hrs_alg_get_results(); - hrsresult.lastesthrs = alg_results.hr_result; - hrsresult.hr_living = alg_results.living_status; - hrsresult.hr_living_qu = alg_results.hr_result_qual; - hrsresult.hr_living_std = alg_results.hr_result_std; - hrsresult.wearstatus = hrs_wear_status; - - if(hrsresult.wearstatus == MSG_HRS_WEAR) - { - wear_status = 1; - if(hrsresult.lastesthrs > 30 && hrsresult.lastesthrs < 220) - get_avg_hrs(hrsresult.lastesthrs); - } - else if(hrsresult.wearstatus == MSG_HRS_NO_WEAR || hrsresult.hr_living == MSG_LIVING_FAIL) - { - hrsresult.wearstatus = MSG_HRS_NO_WEAR; - hrsresult.lastesthrs = 0; - wear_status = 0; - } - + printf("hx3695_hrsdaily_enable\r\n"); + tyhx_hrs_alg_open(); + ppg_sensor_data.mode = HRSDAILY_MODE; + hx3695_ppg_set_mode(PPG_INIT); - // hx3695_msg_callback_t func = hx3695_get_send_msg_callback_func(); - - // if(func != NULL) - // { - // if(his_wear == hrsresult.wearstatus) - // { - // wear_cnt++; - // if(wear_cnt >= 2 && !his_wear) //未佩戴超过2次 上报未佩戴信息 - // { - // func(HX3695_MSG_TYPE_WEARSTAT_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t)); - // wear_cnt = 0; - // } - // } - // else - // { - // his_wear = hrsresult.wearstatus; - // wear_cnt = 0; - // } - // } - //PRINT("hrsresult.wearstatus : %d , his_wear : %d , wear_cnt : %d \n",hrsresult.wearstatus,his_wear,wear_cnt); - // PRINT("hrsresult.wearstatus : %d , wear_status : %d , hr_living : %d \n",hrsresult.wearstatus,wear_status,hrsresult.hr_living); - // if(hrs_wear_status == MSG_HRS_WEAR && hrsresult.hr_living == MSG_LIVING_TRUE) - // { - // if(hrsresult.lastesthrs > 30 && hrsresult.lastesthrs < 220) - // get_avg_hrs(hrsresult.lastesthrs); - - // hrsresult.wearstatus = MSG_HRS_WEAR; - // } - // else - // { - // hrsresult.wearstatus = MSG_HRS_NO_WEAR; - // hrsresult.lastesthrs = 0; - // } - - // PRINT("hrs : %d , wear_status : %d \n",hrsresult.lastesthrs,wear_status); - avg_hrs = hrsresult.lastesthrs; - - msg_count++; - if(msg_count >= 3) - { - -#ifdef SUPPORT_PPG_BLE_SERVICE - if(uapi_dev_runtime_get_hrs_ble_status()) - { - ble_ppgtest_server_send_input_report(&avg_hrs,1); - } -#endif - - msg_count = 0; - // if(func != NULL) - // { - // //PRINT("hrsresult.lastesthrs : %d \n",hrsresult.lastesthrs); - // func(HX3695_MSG_TYPE_HRS_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t)); - // if(uapi_get_cywee_static_state()) - // { - // func(HX3695_MSG_TYPE_STATIC_HRS_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t)); - // } - // } - - if(uapi_dev_runtime_get_train_status()) - { - hx3695_wearstatus_update(); - // avg_hrs = hrsresult.lastesthrs; - // do_cywee_service_check_msg(CYWEE_SERVICE_CMD_HRS_CHANGE,&cywee_data); - } - } - - // PRINT("hrsresult.wearstatus: %d, hr_living: %d, hr_result:%d \r\n",hrsresult.wearstatus,hrsresult.hr_living,hrsresult.lastesthrs); - - // PRINT("hx3695 data_cnt: %d, hr_living: %d, hr_living_qu: %d, hr_living_std: %d, hr_result:%d \r\n",alg_results.data_cnt, hrsresult.hr_living, hrsresult.hr_living_qu, hrsresult.hr_living_std, hrsresult.lastesthrs); - - if(hrs_wear_status == MSG_HRS_WEAR && hrsresult.hr_living == MSG_LIVING_TRUE) - { -// app_hr_reset_stop_timer(); - if(alg_results.hr_result) - { - - //app_hr_cal_hr_values(alg_results.hr_result); - //PRINT("app_hr_cal_hr_values tick:%d hr:%d", xTaskGetTickCount(), alg_results.hr_result); - //cwm_hr_input(alg_results.hr_result); - //hr_sensor_notify_factory_test(); - } - hr_no_living_dur = 0; - curr_wear = 1; - } - else if(hrs_wear_status == MSG_HRS_WEAR && hrsresult.hr_living != MSG_LIVING_TRUE) - { - if (++hr_no_living_dur > 12 * 1000 / tyhx_long_timer_tick) - { - //hr_stop_detect(); - //PRINT("MSG_HRS_WEAR:%d liv:%d", hrs_wear_status, hrsresult.hr_living); - hr_no_living_dur = 0; - curr_wear = 0; - } - } - else if(hrs_wear_status == MSG_HRS_NO_WEAR || hrsresult.hr_living == MSG_LIVING_FAIL) - { - //hr_stop_detect(); - //PRINT("MSG_HRS_NO_WEAR:%d liv:%d", hrs_wear_status, hrsresult.hr_living); - hr_no_living_dur = 0; - curr_wear = 0; - } - - //cwm_off_body_detect(curr_wear); - - #if defined(GSENSOR_LOG_NOTIFY) && GSENSOR_LOG_NOTIFY == 1 || defined(HRS_BLE_APP) - - if (last_wear!=curr_wear) - { - gui_send_message_by_data(MSG_HR_WEAR_STATUS_UPDATE, &curr_wear, 1); - } - #endif - -#ifdef BP_CUSTDOWN_ALG_LIB - bp_results_t bp_alg_results; - bp_alg_results = tyhx_alg_get_bp_results(); -#endif - -////////////////////////////////////////BLE+DISPLAY///////////////////////////////// - - -#ifdef HRS_BLE_APP - { - rawdata_vector_t rawdata; - for(ii=0; ii<*count; ii++) - { - rawdata.vector_flag = HRS_VECTOR_FLAG; - rawdata.data_cnt = alg_results.data_cnt-*count+ii; - rawdata.hr_result = alg_results.hr_result; - rawdata.red_raw_data = PPG_buf[ii]; - rawdata.ir_raw_data = ir_buf[ii]; - rawdata.gsensor_x = gsen_fifo_x_send[ii]; - rawdata.gsensor_y = gsen_fifo_y_send[ii]; - rawdata.gsensor_z = gsen_fifo_z_send[ii]; - rawdata.red_cur = cal.Group1_Cur; - rawdata.ir_cur = cal.Group1_Ledidac; -// PRINT("@@@@@@@@@ HRS_BLE_APP gsen:%d %d %d\r\n", rawdata.gsensor_x, rawdata.gsensor_y, rawdata.gsensor_z); - ble_rawdata_vector_push(rawdata); - } - } - ble_rawdata_send_handler(); -#endif - - if(hrs_ble_falg) - { - uint8_t encoded_hrm[PPG_DATA_LEN_MAX] = {0};//PPG_DATA_LEN_MAX>17会导致APP连接提示定义设备与所选类型不匹配 - uint8_t red_bit = 0; - uint8_t ir_bit = 0; - uint8_t green_bit = 0; - HRS_CAL_SET_T cal= get_hrs_agc_status(); - - for(ii=0; ii<*count; ii++) - { - if(PPG_buf[ii]<0) - { - red_bit = 0x80; - PPG_buf[ii] = -PPG_buf[ii]; - } - if(ir_buf[ii]<0) - { - ir_bit = 0x80; - ir_buf[ii] = -ir_buf[ii]; - } - - encoded_hrm[0] = 0x55;//心率标志位，一定要设置正确 - encoded_hrm[1] = (uint8_t)(alg_results.data_cnt - *count + ii) % 256;//原始data_cnt会一直自加，但是这里只有一个字节，0-255循环 - encoded_hrm[2] = (uint8_t)(alg_results.hr_result & 0xFF);//心率值 - - encoded_hrm[3] = (uint8_t)((PPG_buf[ii] & 0xFF0000) >> 16) | red_bit; //绿灯原始数据 - encoded_hrm[4] = (uint8_t)((PPG_buf[ii] & 0xFF00) >> 8); //绿灯原始数据 - encoded_hrm[5] = (uint8_t)(PPG_buf[ii] & 0xFF); //绿灯原始数据 - - encoded_hrm[6] = (uint8_t)((ir_buf[ii] & 0xFF0000) >> 16) | ir_bit; //ir原始数据 - encoded_hrm[7] = (uint8_t)((ir_buf[ii] & 0xFF00) >> 8); //ir原始数据 - encoded_hrm[8] = (uint8_t)(ir_buf[ii] & 0xFF); //ir原始数据 - - encoded_hrm[9] = (uint8_t)((gsen_fifo_x_send[ii]&0xFF00)>>8);//模拟x，1234换成填入自己的x数据 - encoded_hrm[10] = (uint8_t)(gsen_fifo_x_send[ii]&0xFF); - encoded_hrm[11] = (uint8_t)((gsen_fifo_y_send[ii]&0xFF00)>>8);//模拟y，-1234换成填入自己的y数据 - encoded_hrm[12] = (uint8_t)(gsen_fifo_y_send[ii]&0xFF); - encoded_hrm[13] = (uint8_t)((gsen_fifo_z_send[ii]&0xFF00)>>8);//模拟z,3987换成填入自己的z数据 - encoded_hrm[14] = (uint8_t)(gsen_fifo_z_send[ii]&0xFF); - - encoded_hrm[15] = ppg_s_data.green_cur;//绿灯电流 - encoded_hrm[16] = ppg_s_data.ir_cur;//红外电流 - -#ifdef SUPPORT_PPG_BLE_SERVICE - if(cm_custom_ble_service_on_flag()) - ble_ppgtest_server_send_input_report(encoded_hrm,PPG_DATA_LEN_MAX); -#endif - // ble_op_att_send_data(ATT_CHARACTERISTIC_2a37_01_VALUE_HANDLE,encoded_hrm, \ - // sizeof(encoded_hrm)/sizeof(encoded_hrm[0]), ATT_OP_NOTIFY);//heartrate - } - } - - -//////////////////////////////////////////////////////////////////////////////////// + ppg_sensor_dat->led_activated = 2; + ppg_sensor_dat->fs = 25; + ppg_sensor_dat->watermark = 20; + ppg_sensor_dat->led_data[0].led_state = Activating; + ppg_sensor_dat->led_data[1].led_state = InActivating; + ppg_sensor_dat->led_data[2].led_state = InActivating; + ppg_sensor_dat->led_data[3].led_state = Activating; + ppg_sensor_dat->led_data[0].isneed_cal_start = true; + ppg_sensor_dat->led_data[1].isneed_cal_start = false; + ppg_sensor_dat->led_data[2].isneed_cal_start = false; + ppg_sensor_dat->led_data[3].isneed_cal_start = false; + + hx3695_updata_sensor(ppg_sensor_dat); + DEBUG_PRINTF("hx3695_hrs_enable\n"); } -#endif -#ifdef CHECK_LIVING_LIB -hrs_sensor_data_t hrs_s_dat; - -void hx3695_living_Int_handle(void) +void hx3695_spo2_enable(ppg_sensor_data_t *ppg_sensor_dat) { - uint8_t ii=0; - hx3695_living_results_t living_alg_results = {MSG_LIVING_NO_WEAR,0,0,0}; - int32_t *PPG_buf = &(hrs_s_dat.green_data[0]); - int32_t *ir_buf = &(hrs_s_dat.ir_data[0]); - uint8_t *count = &(hrs_s_dat.count); - hrs_wear_msg_code_t hrs_wear_status = MSG_HRS_NO_WEAR; - int16_t gsen_fifo_x_send[32]= {0}; - int16_t gsen_fifo_y_send[32]= {0}; - int16_t gsen_fifo_z_send[32]= {0}; - - if(hx3695_hrs_read(&hrs_s_dat) == 0) - { - return; - } - -#ifndef GSEN_40MS_TIMMER -// readFifoByHrsModule(); -#endif - DEBUG_PRINTF("\r\nsend jlink cnt=%d\r\n",*count); - - - for(ii=0; ii<*count; ii++) - { - gsen_fifo_x_send[ii] = gsen_fifo_x[32-*count+ii]; - gsen_fifo_y_send[ii] = gsen_fifo_y[32-*count+ii]; - gsen_fifo_z_send[ii] = gsen_fifo_z[32-*count+ii]; - - DEBUG_PRINTF("ger:%d/%d %d %d %d %d %d %d\r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x[ii],gsen_fifo_y[ii],gsen_fifo_z[ii],ppg_s_data.green_cur); - } - hrs_wear_status = hx3695_hrs_get_wear_status(); - if(hrs_wear_status == MSG_HRS_WEAR) - { - hx3695_living_send_data(PPG_buf, *count, gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send); - } - living_alg_results = hx3695_living_get_results(); - DEBUG_PRINTF("res:%d %d %d %d\r\n",living_alg_results.data_cnt,living_alg_results.motion_status,living_alg_results.signal_quality,hrs_wear_status); + printf("hx3695_spo2_enable\r\n"); + tyhx_spo2_alg_open(); + ppg_sensor_data.mode = SPO2_MODE; + hx3695_ppg_set_mode(PPG_INIT); + ppg_sensor_dat->led_activated = 4; + ppg_sensor_dat->fs = 25; + ppg_sensor_dat->watermark = 40; + ppg_sensor_dat->led_data[0].led_state = Activating; + ppg_sensor_dat->led_data[1].led_state = Activating; + ppg_sensor_dat->led_data[2].led_state = Activating; + ppg_sensor_dat->led_data[3].led_state = Activating; + ppg_sensor_dat->led_data[0].isneed_cal_start = true; + ppg_sensor_dat->led_data[1].isneed_cal_start = true; + ppg_sensor_dat->led_data[2].isneed_cal_start = true; + ppg_sensor_dat->led_data[3].isneed_cal_start = false; + hx3695_updata_sensor(ppg_sensor_dat); } -#endif - - -#ifdef SPO2_ALG_LIB -#ifdef SPO2_DATA_CALI -void hx3695_spo2_data_cali_init(void) +void hx3695_hrv_enable(ppg_sensor_data_t *ppg_sensor_dat) { - uint8_t ii; - for(ii=0; ii<4; ii++) - { - red_data_fifo[ii] = 0; - ir_data_fifo[ii] = 0; - } - red_dc_temp = 0; - ir_dc_temp = 0; - red_data_pre = 0; - ir_data_pre = 0; - red_jump_delta = 0; - ir_jump_delta = 0; - cali_data_cnt = 0; + printf("hx3695_hrv_enable\r\n"); + tyhx_hrv_alg_open(); + ppg_sensor_data.mode = HRV_MODE; + hx3695_ppg_set_mode(PPG_INIT); + ppg_sensor_dat->led_activated = 2; + ppg_sensor_dat->fs = 100; + ppg_sensor_dat->watermark = 50; + ppg_sensor_dat->led_data[0].led_state = Activating; + ppg_sensor_dat->led_data[1].led_state = InActivating; + ppg_sensor_dat->led_data[2].led_state = InActivating; + ppg_sensor_dat->led_data[3].led_state = Activating; + ppg_sensor_dat->led_data[0].isneed_cal_start = true; + ppg_sensor_dat->led_data[1].isneed_cal_start = false; + ppg_sensor_dat->led_data[2].isneed_cal_start = false; + ppg_sensor_dat->led_data[3].isneed_cal_start = false; + hx3695_updata_sensor(ppg_sensor_dat); } -int32_t hx3695_red_data_cali(int32_t red_new_raw_data) +void hx3695_wear_low_power(ppg_sensor_data_t *ppg_sensor_dat) { - uint8_t ii; - int32_t red_data_final; - int32_t red_data_cali; - spo2_wear_msg_code_t touch_status; - touch_status = hx3695_spo2_get_wear_status(); - if(touch_status == MSG_SPO2_NO_WEAR) - { - cali_data_cnt = 0; - red_data_cali = red_new_raw_data; - for(ii=0; ii<4; ii++) - { - red_data_fifo[ii] = 0; - } - red_dc_temp = 0; - } - else - { - for(ii=3; ii>0; ii--) - { - red_data_fifo[ii] = red_data_fifo[ii-1]; - } - red_data_fifo[0] = red_new_raw_data; - if(cali_data_cnt>=25) - { - if ((((red_data_fifo[1] - red_data_fifo[2]) > SOP2_DEGLITCH_THRE) && ((red_data_fifo[1] - red_new_raw_data) > SOP2_DEGLITCH_THRE)) || \ - (((red_data_fifo[1] - red_data_fifo[2]) < -SOP2_DEGLITCH_THRE) && ((red_data_fifo[1] - red_new_raw_data) < -SOP2_DEGLITCH_THRE))) - { - red_new_raw_data = red_data_fifo[2]; - red_data_fifo[1] = red_data_fifo[2]; - } - else - { - red_new_raw_data = red_data_fifo[1]; - } - if ((abs((red_new_raw_data - red_jump_delta) - red_data_pre) > SPO2_REMOVE_JUMP_THRE)) - { - red_jump_delta = red_new_raw_data - red_data_pre; - } - red_data_cali = red_new_raw_data - red_jump_delta; - red_data_pre = red_data_cali; - } - else - { - red_data_cali = red_data_fifo[1]; - red_data_pre = red_data_fifo[1]; - } - } - if(cali_data_cnt<=30) - { - red_dc_temp = red_data_cali; - red_data_final = red_new_raw_data; - } - else - { - //red_dc_temp = (red_dc_temp*31 + red_data_cali)>>5; - red_dc_temp = 0; - red_data_final = red_data_cali - red_dc_temp + 2608*50*hx3695_spo2_agc_red_idac; - } - //DEBUG_PRINTF("%d %d %d %d %d %d\r\n", cali_data_cnt, red_new_raw_data, red_data_final, red_data_cali, red_dc_temp, hx3695_spo2_agc_red_idac); - return red_data_final; + printf("hx3695_wear_low_power\r\n"); + ppg_sensor_data.mode = WEAR_MODE; + hx3695_ppg_set_mode(PPG_INIT); + ppg_sensor_dat->led_activated = 1; + ppg_sensor_dat->fs = 5; + ppg_sensor_dat->watermark = 5; + ppg_sensor_dat->led_data[0].led_state = InActivating; + ppg_sensor_dat->led_data[1].led_state = InActivating; + ppg_sensor_dat->led_data[2].led_state = InActivating; + ppg_sensor_dat->led_data[3].led_state = Activating; + ppg_sensor_dat->led_data[0].isneed_cal_start = false; + ppg_sensor_dat->led_data[1].isneed_cal_start = false; + ppg_sensor_dat->led_data[2].isneed_cal_start = false; + ppg_sensor_dat->led_data[3].isneed_cal_start = false; + hx3695_updata_sensor(ppg_sensor_dat); } -int32_t hx3695_ir_data_cali(int32_t ir_new_raw_data) + +void hx3695_ppg_set_mode(uint8_t mode_cmd) { - uint8_t ii; - int32_t ir_data_final; - int32_t ir_data_cali; - spo2_wear_msg_code_t touch_status; - touch_status = hx3695_spo2_get_wear_status(); - if(touch_status == MSG_SPO2_NO_WEAR) - { - cali_data_cnt = 0; - ir_data_cali = ir_new_raw_data; - for(ii=0; ii<4; ii++) - { - ir_data_fifo[ii] = 0; - } - ir_dc_temp = 0; - } - else + DEBUG_PRINTF("hx3695_ppg_set_mode %d \r\n", mode_cmd); + switch (mode_cmd) { - for(ii=3; ii>0; ii--) - { - ir_data_fifo[ii] = ir_data_fifo[ii-1]; - } - ir_data_fifo[0] = ir_new_raw_data; - cali_data_cnt++; - if(cali_data_cnt>=25) - { - if ((((ir_data_fifo[1] - ir_data_fifo[2]) > SOP2_DEGLITCH_THRE) && ((ir_data_fifo[1] - ir_new_raw_data) > SOP2_DEGLITCH_THRE)) || \ - (((ir_data_fifo[1] - ir_data_fifo[2]) < -SOP2_DEGLITCH_THRE) && ((ir_data_fifo[1] - ir_new_raw_data) < -SOP2_DEGLITCH_THRE))) - { - ir_new_raw_data = ir_data_fifo[2]; - ir_data_fifo[1] = ir_data_fifo[2]; - } - else + case PPG_INIT: + hx3695_ppg_para_init(&ppg_sensor_data); + s_ppg_state = 1; + s_cal_state = 0; + if(work_mode_flag == HRS_MODE) { - ir_new_raw_data = ir_data_fifo[1]; + #if defined(TIMMER_MODE) + hx3695_320ms_timer_cfg(true); + #else + hx3695_gpioint_cfg(true); + #endif } - if ((abs((ir_new_raw_data - ir_jump_delta) - ir_data_pre) > SPO2_REMOVE_JUMP_THRE)) - { - ir_jump_delta = ir_new_raw_data - ir_data_pre; - } - ir_data_cali = ir_new_raw_data - ir_jump_delta; - ir_data_pre = ir_data_cali; - } - else - { - ir_data_cali = ir_data_fifo[1]; - ir_data_pre = ir_data_fifo[1]; - } - } - if(cali_data_cnt<=30) - { - ir_dc_temp = ir_data_cali; - ir_data_final = ir_new_raw_data; - } - else - { - //ir_dc_temp = (ir_dc_temp*31 + ir_data_cali)>>5; - ir_dc_temp = 0; - ir_data_final = ir_data_cali - ir_dc_temp + 2608*50*hx3695_spo2_agc_ir_idac; + + DEBUG_PRINTF("ppg init mode\r\n"); + break; + + case PPG_OFF: + #if defined(TIMMER_MODE) + hx3695_320ms_timer_cfg(false); + hx3695_40ms_timer_cfg(false); + hx3695_5000ms_timer_cfg(false); + #elif defined(INT_MODE) + hx3695_gpioint_cfg(false); + #endif + hx3695_ppg_off(); + s_ppg_state = 0; + s_cal_state = 0; + DEBUG_PRINTF("ppg off mode\r\n"); + break; + + case PPG_LED_OFF: + hx3695_wear_low_power(&ppg_sensor_data); + #if defined(TIMMER_MODE) + hx3695_5000ms_timer_cfg(true); + #endif + s_ppg_state = 1; + s_cal_state = 0; + DEBUG_PRINTF("ppg led off mode\r\n"); + break; + + case CAL_INIT: + hx3695_cal_init(); + s_ppg_state = 0; + s_cal_state = 1; + #if defined(TIMMER_MODE) + hx3695_320ms_timer_cfg(false); + hx3695_40ms_timer_cfg(true); + #endif + DEBUG_PRINTF("cal init mode\r\n"); + break; + + case RECAL_INIT: + hx3695_recal_init(); + s_ppg_state = 0; + s_cal_state = 1; + #if defined(TIMMER_MODE) + hx3695_320ms_timer_cfg(false); + hx3695_40ms_timer_cfg(true); + #endif + DEBUG_PRINTF("recal init mode\r\n"); + break; + + case CAL_OFF: + #if defined(TIMMER_MODE) + hx3695_320ms_timer_cfg(true); + hx3695_40ms_timer_cfg(false); + #endif + hx3695_cal_off(); + s_ppg_state = 1; + s_cal_state = 0; + DEBUG_PRINTF("cal off mode\r\n"); + break; + + default: + break; } - //DEBUG_PRINTF("%d %d %d %d %d %d\r\n", cali_data_cnt, ir_new_raw_data, ir_data_final, ir_data_cali, ir_dc_temp, hx3695_spo2_agc_ir_idac); - return ir_data_final; } -#endif //SPO2_DATA_CALI -//#ifdef SPO2_ALG_LIB -spo2_sensor_data_t spo2_s_dat; - -/*TYHX 血氧模式下 读取PPG， 默认320ms*/ -void hx3695_spo2_ppg_Int_handle(void) +bool hx3695_init(WORK_MODE_T mode) { - uint8_t ii=0; - spo2_results_t spo2_alg_results = {MSG_SPO2_ALG_NOT_OPEN,0,0,0,0,0,0,1,0,0,0,0,0}; - spo2_wear_msg_code_t spo2_wear_status = MSG_SPO2_NO_WEAR; - SPO2_CAL_SET_T cal = get_spo2_agc_status(); - int32_t *red_buf = &(spo2_s_dat.red_data[0]); - int32_t *ir_buf = &(spo2_s_dat.ir_data1[0]); - int32_t *green_buf = &(spo2_s_dat.green_data[0]); - uint8_t *count = &(spo2_s_dat.count); - int16_t gsen_fifo_x_send[32]= {0}; - int16_t gsen_fifo_y_send[32]= {0}; - int16_t gsen_fifo_z_send[32]= {0}; -#ifdef SPO2_DATA_CALI - int32_t red_data_cali, ir_data_cali; -#endif - -#ifdef SPO2_VECTOR - for(ii=0; ii<8; ii++) + work_mode_flag = mode; + hx3695_software_reset(); + hx3695_ppg_on(); + if (hx3695_chip_check() != 0x65) + { + return false; + } + switch (work_mode_flag) { - red_buf_vec[ii] = vec_red_data[spo2_send_cnt+ii]; - ir_buf_vec[ii] = vec_ir_data[spo2_send_cnt+ii]; - green_buf_vec[ii] = vec_green_data[spo2_send_cnt+ii]; - } - spo2_send_cnt = spo2_send_cnt+8; - *count = 8; - tyhx_spo2_alg_send_data(red_buf, ir_buf, green_buf, cal.R_LEDDAC, cal.IR_LEDDAC1, cal.R_LEDDAC, gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send, *count); + case HRS_MODE: + hx3695_hrs_enable(&ppg_sensor_data); + break; + + case HRSDAILY_MODE: + hx3695_hrsdaily_enable(&ppg_sensor_data); + break; -#else - if(hx3695_spo2_read(&spo2_s_dat) == 0) - { - return; - } - -#ifndef GSEN_40MS_TIMMER -// readFifoByHrsModule(); -#endif - //DEBUG_PRINTF("\r\n send1 jlink cnt=%d\r\n",*count); - - /*屏蔽*/ - //("*count[%d] \r\n",*count); + case LIVING_MODE: - //count7-9 为捕捉到的红光值正常数据数量范围,不在此范围,血氧数据不准,直接返回. - if(*count < 7 || *count > 9) - { - return; - } - //cywee_get_gsensor_data(8,gsensordata); - for(ii=0; ii<*count; ii++) - { + break; - // if(ii == 8) - // { - // gsen_fifo_x_send[ii] = gsen_fifo_x_send[ii - 1]; - // gsen_fifo_y_send[ii] = gsen_fifo_y_send[ii - 1]; - // gsen_fifo_z_send[ii] = gsen_fifo_z_send[ii - 1]; - // } - // else - // { - // gsen_fifo_x_send[ii] = gsensordata[ii].x * 2048; - // gsen_fifo_y_send[ii] = gsensordata[ii].y * 2048; - // gsen_fifo_z_send[ii] = gsensordata[ii].z * 2048; - // } - //("hxdata:%d/%d %d %d %d %d %d %d\r\n", - //1+ii,*count,red_buf[ii],ir_buf[ii],green_buf[ii],gsen_fifo_x_send[ii],gsen_fifo_y_send[ii],gsen_fifo_z_send[ii]); - //printf("FFF==>spo2 red_buf : %d, %d, %d, %d \n", 1+ii, *count, red_buf[ii], ir_buf[0]); - factory_data = red_buf[ii]; - } + case SPO2_MODE: + hx3695_spo2_enable(&ppg_sensor_data); + tyhx_spo2_para_usuallyadjust(SPO2_LOW_XCORR_THRE, SPO2_LOW_SNR_THRE, COUNT_BLOCK_NUM, SPO2_BASE_LINE_INIT, SPO2_SLOPE, SPO2_GSEN_POW_THRE); + tyhx_spo2_para_barelychange(MEAN_NUM, SOP2_DEGLITCH_THRE, SPO2_REMOVE_JUMP_THRE, SPO2_LOW_CLIP_END_TIME, SPO2_LOW_CLIP_DN, SPO2_NORMAL_CLIP_DN, + IR_AC_TOUCH_THRE, IR_FFT_POW_THRE, SPO2_CALI, SLOPE_PARA_MAX, SLOPE_PARA_MIN); - // ft_ppg_iir = spo2_s_dat.red_data[0]; - // hx3695_factory_test_process(NULL, APP_FACTORY_TEST_SPO2_START, &ft_ppg_iir); + break; - ft_test_result_t result = {0}; - result.gr_data_final = spo2_s_dat.green_data[0]; - result.red_data_final = spo2_s_dat.red_data[0]; - result.ir_data_final = spo2_s_dat.ir_data1[0]; - //hx3695_factory_test_process(NULL, APP_FACTORY_TEST_SPO2_START, &result); + case HRV_MODE: + hx3695_hrv_enable(&ppg_sensor_data); + break; + case WEAR_MODE: + hx3695_ppg_set_mode(PPG_LED_OFF); + break; - //("hx3695 current value: %d %d %d %d %d %d\r\n", cal.R_LED, cal.IR_LED1, cal.G_LED, cal.R_LEDDAC, cal.IR_LEDDAC1, cal.G_LEDDAC); - spo2_wear_status = hx3695_spo2_get_wear_status(); - //PRINT("spo2_wear_status : %d\r\n",spo2_wear_status); - if(spo2_wear_status == MSG_SPO2_WEAR) - { - tyhx_spo2_alg_send_data(red_buf, ir_buf, green_buf, cal.R_LEDDAC, cal.IR_LEDDAC1, cal.G_LEDDAC, - gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send, *count); - } - -#endif + case FT_LEAK_LIGHT_MODE: + if (hx3695_chip_check() != 0x65) + { + return false; + } + hx3695_factroy_test(LEAK_LIGHT_TEST); + return true; + break; - spo2_alg_results = tyhx_spo2_alg_get_results(); -//------------------------adjust------------------- -// DEBUG_PRINTF("block_cnt: %d, data_cnt:%d, hr_result:%d,ir_quality:%d,motion:%d,poor_signal:%d,reliable_score_result:%d,screen_up:%d,spo2_result:%d\r\n",spo2_alg_results.block_cnt,spo2_alg_results.data_cnt,spo2_alg_results.hr_result,spo2_alg_results.ir_quality,spo2_alg_results.motion,spo2_alg_results.poor_signal,spo2_alg_results.reliable_score_result,spo2_alg_results.screen_up,spo2_alg_results.spo2_result); + case FT_GRAY_CARD_MODE: + if (hx3695_chip_check() != 0x65) + { + return false; + } + hx3695_factroy_test(GRAY_CARD_TEST); + return true; + break; - hrsresult.lastestspo2 = spo2_alg_results.spo2_result; - hrsresult.lastesthrs = spo2_alg_results.hr_result; - uint8_t curr_wear = 1; + case FT_INT_TEST_MODE: + //hx3695_factroy_test(FT_INT_TEST); + break; - if(spo2_wear_status == MSG_SPO2_WEAR) - { - wear_status = 1; - } - else if(spo2_wear_status == MSG_SPO2_NO_WEAR || spo2_alg_results.spo2_living_status == MSG_SPO2_LIVING_FAIL) - { - wear_status = 0; - } + case AGING_CHECK_MODE: + hx3695_factroy_test(AGING_CHECK_TEST); + return true; + break; - // printf("spo2:%d wear:%d\n",spo2_alg_results.spo2_result,wear_status); + case FT_LED_OFF_MODE: + //hx3695_factroy_test(LED_OFF_TEST); + break; - //uint8_t last_wear = cwm_get_wear_status(); - if(spo2_wear_status == MSG_SPO2_WEAR && spo2_alg_results.spo2_living_status == MSG_SPO2_LIVING_TRUE) - { - //store_latest_spo2(hrsresult.lastestspo2); - //app_hr_cal_hr_values(hrsresult.lastesthrs); - //cwm_hr_input(hrsresult.lastesthrs); - spo2_no_living_dur = 0; - curr_wear = 1; + case FT_WEAR_MODE: + //hx3695_factroy_test(WEAR_MODE_TEST); + break; + + default: + break; } - else if(spo2_wear_status == MSG_SPO2_WEAR && spo2_alg_results.spo2_living_status != MSG_SPO2_LIVING_TRUE) + hx3695_agc_Int_handle(&ppg_sensor_data); + return true; +} + +void hx3695_agc_Int_handle(ppg_sensor_data_t *ppg_sensor_dat) +{ + uint8_t ii = 0; + if(s_ppg_state==1 && s_cal_state==0) { - if (++spo2_no_living_dur > 12 * 1000 / tyhx_long_timer_tick) + for(ii=0;ii<4;ii++) { - //gui_send_msg_by_evt(MSG_SPO2_MEASURE_CANCEL); - //("MSG_SPO2_WEAR:%d liv:%d", spo2_wear_status, spo2_alg_results.spo2_living_status); - spo2_no_living_dur = 0; - curr_wear = 0; + if(ppg_sensor_dat->led_data[ii].isneed_cal_start == true) + { + hx3695_ppg_set_mode(CAL_INIT); + return; + } } } - else if(spo2_wear_status == MSG_SPO2_NO_WEAR || spo2_alg_results.spo2_living_status == MSG_SPO2_LIVING_FAIL) - { - //gui_send_msg_by_evt(MSG_SPO2_MEASURE_CANCEL); - //PRINT("MSG_SPO2_NO_WEAR:%d liv:%d", spo2_wear_status, spo2_alg_results.spo2_living_status); - spo2_no_living_dur = 0; - curr_wear = 0; - } - //cwm_off_body_detect(curr_wear); - #if defined(GSENSOR_LOG_NOTIFY) && GSENSOR_LOG_NOTIFY == 1 || defined(HRS_BLE_APP) - if (last_wear!=curr_wear) - { - gui_send_message_by_data(MSG_HR_WEAR_STATUS_UPDATE, &curr_wear, 1); - } - #endif -/////////////////////////////////////////BLE+DISPLAY////////////////////////////////////////// - spo2_alg_results = tyhx_spo2_alg_get_results(); -//------------------------adjust------------------- - DEBUG_PRINTF("block_cnt: %d, data_cnt:%d, hr_result:%d,ir_quality:%d,motion:%d,poor_signal:%d,reliable_score_result:%d,screen_up:%d,spo2_result:%d\r\n",spo2_alg_results.block_cnt,spo2_alg_results.data_cnt,spo2_alg_results.hr_result,spo2_alg_results.ir_quality,spo2_alg_results.motion,spo2_alg_results.poor_signal,spo2_alg_results.reliable_score_result,spo2_alg_results.screen_up,spo2_alg_results.spo2_result); - - hrsresult.lastestspo2 = spo2_alg_results.spo2_result; - spo2_result = hrsresult.lastestspo2; -// if(hrsresult.lastestspo2) - { - // store_latest_spo2(hrsresult.lastestspo2); - // app_hr_cal_hr_values(hrsresult.lastesthrs); -// gui_send_message_by_data(MSG_SPO2_DATA, &hrsresult.lastestspo2, 1); -// hr_sensor_notify_factory_test(); - } - - // hx3695_msg_callback_t func = hx3695_get_send_msg_callback_func(); - // if(func != NULL) - // { - // hrsresult.wearstatus = spo2_wear_status; - // func(HX3695_MSG_TYPE_WEARSTAT_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t)); - // func(HX3695_MSG_TYPE_SPO2_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t)); - // } + hx3695_agc_process(ppg_sensor_dat); +} +void agc_timeout_handler(void *p_context) +{ + // printf("agc_timeout_handler \n"); + hx3695_agc_Int_handle(&ppg_sensor_data); +} +void heart_rate_meas_timeout_handler(void *p_context) +{ + // printf("heart_rate_meas_timeout_handler \n"); + hx3695_ppg_Int_handle(&ppg_sensor_data); + hx3695_agc_Int_handle(&ppg_sensor_data); +} +void nrf_gpioint_handle(void) +{ + hx3695_ppg_Int_handle(&ppg_sensor_data); + hx3695_agc_Int_handle(&ppg_sensor_data); +} -#ifdef HRS_BLE_APP - { - rawdata_vector_t rawdata; - SPO2_CAL_SET_T cal= get_spo2_agc_status(); - for(ii=0; ii<*count; ii++) - { -#ifdef SPO2_DATA_CALI - ir_data_cali = hx3695_ir_data_cali(ir_buf[ii]); - red_data_cali = hx3695_red_data_cali(red_buf[ii]); - rawdata.red_raw_data = red_data_cali>>2; - rawdata.ir_raw_data = ir_data_cali>>2; -#else - rawdata.red_raw_data = red_buf[ii]; - rawdata.ir_raw_data = ir_buf[ii]; -#endif - rawdata.vector_flag = SPO2_VECTOR_FLAG; - rawdata.data_cnt = cal.G_LED; - rawdata.hr_result = spo2_alg_results.spo2_result; - rawdata.gsensor_x = (int16_t)(green_buf[ii]>>5); - rawdata.gsensor_y = cal.R_LEDDAC; - rawdata.gsensor_z = cal.IR_LEDDAC1; - rawdata.red_cur = cal.R_LED; - rawdata.ir_cur = cal.IR_LED1; - ble_rawdata_vector_push(rawdata); - } - ble_rawdata_send_handler(); - } -#endif -if(hrs_ble_falg) + +#define HRS_WINDOW_SIZE 5 +static uint8_t hrs_num = 0; +static int32_t sum_hrs = 0; +static int32_t hrs_data[7] = {0}; +static uint8_t left = 0; +static uint8_t right = 0; +static uint8_t avg_hrs = 0; + +static void get_avg_hrs(uint8_t hrs) { - uint8_t encoded_hrm[PPG_DATA_LEN_MAX] = {0};//PPG_DATA_LEN_MAX>17会导致APP连接提示定义设备与所选类型不匹配 - uint8_t red_bit = 0; - uint8_t ir_bit = 0; - uint8_t green_bit = 0; - //rawdata_vector_t rawdata; - // SPO2_CAL_SET_T cal= get_spo2_agc_status(); - for(ii=0; ii<*count; ii++) - { - if(red_buf[ii]<0) - { - red_bit = 0x80; - red_buf[ii] = -red_buf[ii]; + if (hrs_num >= HRS_WINDOW_SIZE) { + sum_hrs -= hrs_data[left]; + left = (left + 1) % HRS_WINDOW_SIZE; + hrs_num--; + } + + hrs_data[right] = hrs; + sum_hrs += hrs; + right = (right + 1) % HRS_WINDOW_SIZE; + hrs_num++; + + + if (hrs_num > 2) + { + + uint8_t first_idx = left; + int32_t min_hrs = hrs_data[first_idx]; + int32_t max_hrs = hrs_data[first_idx]; + + + for (uint8_t i = 0; i < hrs_num; i++) { + uint8_t current_idx = (left + i) % HRS_WINDOW_SIZE; + uint8_t current_hrs = hrs_data[current_idx]; + + if (current_hrs < min_hrs) { + min_hrs = current_hrs; } - if(ir_buf[ii]<0) - { - ir_bit = 0x80; - ir_buf[ii] = -ir_buf[ii]; + if (current_hrs > max_hrs) { + max_hrs = current_hrs; } - - encoded_hrm[0] = 0x66;//血氧标志位，一定要对 - encoded_hrm[1] = (uint8_t)(spo2_alg_results.data_cnt - *count + ii) % 256; - encoded_hrm[2] = (uint8_t)(spo2_alg_results.spo2_result& 0xFF); - - encoded_hrm[3] = (uint8_t)((red_buf[ii] & 0xFF0000) >> 16) | red_bit; //红灯原始数据 - encoded_hrm[4] = (uint8_t)((red_buf[ii] & 0xFF00) >> 8); - encoded_hrm[5] = (uint8_t)(red_buf[ii] & 0xFF); - - encoded_hrm[6] = (uint8_t)((ir_buf[ii] & 0xFF0000) >> 16) | ir_bit; //ir原始数据 - encoded_hrm[7] = (uint8_t)((ir_buf[ii] & 0xFF00) >> 8); - encoded_hrm[8] = (uint8_t)(ir_buf[ii] & 0xFF); - - #ifdef SAR_ALG_LIB - encoded_hrm[9] = (uint8_t)((gdiff[0]&0xFF00)>>8);//sar diff - encoded_hrm[10] = (uint8_t)(gdiff[0]&0xFF); - #else - encoded_hrm[9] = (uint8_t)((gsen_fifo_x_send[ii]&0xFF00)>>8);//模拟x - encoded_hrm[10] = (uint8_t)(gsen_fifo_x_send[ii]&0xFF); - #endif - - encoded_hrm[11] = (uint8_t)((gsen_fifo_y_send[ii]&0xFF00)>>8);//模拟y - encoded_hrm[12] = (uint8_t)(gsen_fifo_y_send[ii]&0xFF); - encoded_hrm[13] = (uint8_t)((gsen_fifo_z_send[ii]&0xFF00)>>8);//模拟z - encoded_hrm[14] = (uint8_t)(gsen_fifo_z_send[ii]&0xFF); - - encoded_hrm[15] = cal.R_LED; - encoded_hrm[16] = cal.IR_LED1; -#ifdef SUPPORT_PPG_BLE_SERVICE - if(cm_custom_ble_service_on_flag()) - ble_ppgtest_server_send_input_report(encoded_hrm,PPG_DATA_LEN_MAX); -#endif } - } + uint8_t valid_count = hrs_num - 2; + avg_hrs = (sum_hrs - max_hrs - min_hrs) / valid_count; -///////////////////////////////////////////////////////////////////////////////////////////////// + // printf("max_hrs[%d],min_hrs[%d],avg_hrs[%d]\n",max_hrs,min_hrs,avg_hrs); + } } -#endif //SPO2_ALG_LIB +void hx3695_alg_send_data(ppg_sensor_data_t *ppg_sensor_dat, WORK_MODE_T mode, uint8_t data_count) +{ + uint16_t gcc_len = 16; + hrs_results_t hrs_result = {MSG_HRS_ALG_NOT_OPEN,MSG_LIVING_INITIAL,0,0,0,0,0,0,0,0,0,0,0,0}; + spo2_results_t spo2_result = {MSG_SPO2_ALG_NOT_OPEN,MSG_SPO2_LIVING_INITIAL,0,0,0,0,0,0,0,0,0,0,0}; + hrv_results_t hrv_alg_results= {MSG_HRV_ALG_NOT_OPEN,0,0,0,0,0,1,0,0,0,0}; + switch(mode) + { + case HRS_MODE: + { +// tyhx_acc_send_data(gsen_data_x_fifo, gsen_data_y_fifo, gsen_data_z_fifo, gcc_len, 50); +// tyhx_hrs_alg_send_data(ppg_sensor_dat->led_data[0].data_val, ppg_sensor_dat->led_data[1].data_val, data_count, 100); +#ifdef SUPPORT_CYWEE_SERVICE + memset(gsensordata,0.0f,sizeof(gsenson_t) * data_count); + cywee_get_gsensor_data(data_count,gsensordata); -#if defined(HRS_ALG_LIB) && defined (SPO2_ALG_LIB) -spo2_sensor_data_t hrspo2_s_data; + for(int ii=0; ii 20 && !acc_restart_flag) //避免重复开关gsensor + // { + // do_cywee_service_check_msg(CYWEE_SERVICE_CMD_RESTART_ACC,NULL); + // acc_restart_flag = 1; + // } + // } + // else + // { + // timeout = 0; + // acc_restart_flag = 0; + // } + + if(gsensordata[ii].x == 0 && gsensordata[ii].y == 0 && gsensordata[ii].z == 0) + { + gsen_data_x_fifo[ii] = gsen_data_x_fifo[ii - 1]; + gsen_data_y_fifo[ii] = gsen_data_y_fifo[ii - 1]; + gsen_data_z_fifo[ii] = gsen_data_z_fifo[ii - 1]; + } + else + { + gsen_data_x_fifo[ii] = gsensordata[ii].x * 4096 / 10; + gsen_data_y_fifo[ii] = gsensordata[ii].y * 4096 / 10; + gsen_data_z_fifo[ii] = gsensordata[ii].z * 4096 / 10; + } + // cywee_get_gsensor_data(8,gsensordata); + // for(ii=0; ii<*count; ii++) + // { + // if(gsensordata[ii].x == 0.0f && gsensordata[ii].y == 0.0f && gsensordata[ii].z == 0.0f) + // { + // timeout++; + // if(timeout > 20) + // { + // do_cywee_service_check_msg(CYWEE_SERVICE_CMD_RESTART_ACC,NULL); + // } + // } + // else + // { + // timeout = 0; + // } + // // if(ii == 8) + // // { + // // gsen_fifo_x_send[ii] = gsen_fifo_x_send[ii - 1]; + // // gsen_fifo_y_send[ii] = gsen_fifo_y_send[ii - 1]; + // // gsen_fifo_z_send[ii] = gsen_fifo_z_send[ii - 1]; + // // } + // // else + // // { + // if(ii < 9) + // { + // gsen_fifo_x_send[ii] = gsensordata[ii].x * 4096 / 10; + // gsen_fifo_y_send[ii] = gsensordata[ii].y * 4096 / 10; + // gsen_fifo_z_send[ii] = gsensordata[ii].z * 4096 / 10; + // } + + // } + // printf("gsensor: %d %.3f %.3f %.3f\r\n" ,data_count,gsensordata[ii].x,gsensordata[ii].y,gsensordata[ii].z); + //PRINT("hxdata:%d/%d %d %d %.3f %.3f %.3f %d\r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x_send[ii],gsen_fifo_y_send[ii],gsen_fifo_z_send[ii],ppg_s_data.green_cur); + //PRINT("hxdata:%d/%d %d %d %d %d %d %d\r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x_send[ii],gsen_fifo_y_send[ii],gsen_fifo_z_send[ii],ppg_s_data.green_cur); + //PRINT("hxdata:%d/%d %d %d %.3f %.3f %.3f %d\r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsensordata[ii].x,gsensordata[ii].y,gsensordata[ii].z,ppg_s_data.green_cur); -void hx3695_hrspo2_ppg_Int_handle(void) -{ - uint8_t ii=0; - spo2_results_t spo2_alg_results = {MSG_SPO2_ALG_NOT_OPEN,0,0,0,0,0,0,0,0,0,0,0,0}; - hrs_results_t alg_results = {MSG_HRS_ALG_NOT_OPEN,0,0,0,0,0,0}; - spo2_wear_msg_code_t spo2_wear_status = MSG_SPO2_NO_WEAR; - SPO2_CAL_SET_T cal = get_spo2_agc_status(); - int32_t *red_buf = &(hrspo2_s_data.red_data[0]); - int32_t *ir_buf = &(hrspo2_s_data.ir_data1[0]); - int32_t *green_buf = &(hrspo2_s_data.red_data[0]); // &(hrspo2_s_data.green_data[0]); - uint8_t *count = &(ppg_s_data.count); - int16_t gsen_fifo_x_send[32]= {0}; - int16_t gsen_fifo_y_send[32]= {0}; - int16_t gsen_fifo_z_send[32]= {0}; -#ifdef SPO2_DATA_CALI - int32_t red_data_cali, ir_data_cali; + } #endif + factory_data = ppg_sensor_dat->led_data[0].data_val; + // printf("factory_data:%d\n", factory_data); + tyhx_hrs_alg_send_data(ppg_sensor_dat->led_data[0].data_val,data_count, gsen_data_x_fifo, gsen_data_y_fifo, gsen_data_z_fifo, ppg_sensor_dat->led_data[0].offset_idac); + //tyhx_hrs_alg_send_data(ppg_sensor_dat->led_data[0].data_val,data_count, gsen_data_x_fifo, gsen_data_y_fifo, gsen_data_z_fifo); + hrs_result = tyhx_hrs_alg_get_results(); + DEBUG_PRINTF("HRS: %d %d\r\n",hrs_result.data_cnt, hrs_result.hr_result); + // printf("hr:%d\n", hrs_result.hr_result); + get_avg_hrs(hrs_result.hr_result); + break; + } + case SPO2_MODE: + { + tyhx_spo2_alg_send_data(ppg_sensor_dat->led_data[1].data_val, ppg_sensor_dat->led_data[2].data_val, ppg_sensor_dat->led_data[0].data_val, \ + ppg_sensor_dat->led_data[1].offset_idac, ppg_sensor_dat->led_data[2].offset_idac,ppg_sensor_dat->led_data[0].offset_idac, \ + gsen_data_x_fifo, gsen_data_y_fifo, gsen_data_z_fifo, data_count); + spo2_result = tyhx_spo2_alg_get_results(); + DEBUG_PRINTF("SPO2: %d %d\r\n",spo2_result.data_cnt, spo2_result.spo2_result); + // printf("spo2:%d\n", spo2_result.spo2_result); + spo2_ret = spo2_result.spo2_result; + break; + } + case HRV_MODE: + { + hrv_alg_results = tyhx_hrv_alg_send_bufdata(ppg_sensor_dat->led_data[0].data_val,data_count, gsen_data_x_fifo, gsen_data_y_fifo, gsen_data_z_fifo); + DEBUG_PRINTF("data_cnt:%d hrv_result:%d motion:%d p_m:%d screen_up:%d signal_quality:%d \r\n", hrv_alg_results.data_cnt,hrv_alg_results.hrv_result,hrv_alg_results.motion,hrv_alg_results.p_m,hrv_alg_results.screen_up,hrv_alg_results.signal_quality); + // printf("hrv:%d\n",hrv_alg_results.hrv_result); + break; + } + default: + { + break; + } + } +} - if(hx3695_spo2_read(&hrspo2_s_data) == 0) - { - return; - } - -#ifndef GSEN_40MS_TIMMER -//readFifoByHrsModule(); -#endif - //DEBUG_PRINTF("\r\nsend jlink cnt=%d\r\n",*count); - - - // for(ii=0; ii<*count; ii++) - // { - // gsen_fifo_x_send[ii] = gsen_fifo_x[32-*count+ii]; - // gsen_fifo_y_send[ii] = gsen_fifo_y[32-*count+ii]; - // gsen_fifo_z_send[ii] = gsen_fifo_z[32-*count+ii]; - // } - spo2_wear_status = hx3695_spo2_get_wear_status(); - if(spo2_wear_status == MSG_SPO2_WEAR) +void hx3695_ppg_Int_handle(ppg_sensor_data_t *ppg_sensor_dat) +{ + uint16_t count = 0; + uint16_t ii = 0; + if(s_ppg_state == 0) + { + return; + } + count = hx3695_read_fifo_data(ppg_sensor_dat); + if(count > 0) { - tyhx_spo2_alg_send_data(red_buf, ir_buf, green_buf, cal.R_LEDDAC, cal.IR_LEDDAC1, cal.R_LEDDAC, gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send, *count); - //tyhx_hrs_alg_send_data(green_buf,*count, gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send); - //DEBUG_PRINTF("%d/%d %d %d %d %d %d %d\r\n" ,1+ii,*count,red_buf[ii],ir_buf[ii],green_buf[ii],gsen_fifo_x[ii],gsen_fifo_y[ii],gsen_fifo_z[ii]); + hx3695_check_wear(ppg_sensor_dat); + if(wear_status == MSG_WEAR) + { + hx3695_alg_send_data(ppg_sensor_dat,work_mode_flag,count); + } } - //DEBUG_PRINTF("%d %d %d %d %d %d\r\n", cal.R_LED, cal.IR_LED, cal.G_LED, cal.R_LEDDAC, cal.IR_LEDDAC, cal.G_LEDDAC); - spo2_alg_results = tyhx_spo2_alg_get_results(); - alg_results = tyhx_hrs_alg_get_results(); - //DEBUG_PRINTF("spo2_wear_status: %d, hr_result:%d, spo2_result:%d\r\n" ,spo2_wear_status, spo2_alg_results.hr_result,spo2_alg_results.spo2_result); + for(ii=0;iiled_data[0].data_val[ii], ppg_sensor_dat->led_data[1].data_val[ii],ppg_sensor_dat->led_data[2].data_val[ii], ppg_sensor_dat->led_data[3].data_val[ii], \ + ppg_sensor_dat->led_data[0].led_current, ppg_sensor_dat->led_data[0].offset_idac, ppg_sensor_dat->led_data[1].led_current, ppg_sensor_dat->led_data[1].offset_idac,ppg_sensor_dat->led_data[2].led_current, ppg_sensor_dat->led_data[2].offset_idac); + } +} -/////////////////////////////////////////BLE+DISPLAY////////////////////////////////////////// +uint8_t hx3695_get_hrs(void) +{ + return avg_hrs; +} + +uint8_t hx3695_get_spo2(void) +{ + return spo2_ret; +} -#ifdef HRS_BLE_APP - { - rawdata_vector_t rawdata; - SPO2_CAL_SET_T cal= get_spo2_agc_status(); - for(ii=0; ii<*count; ii++) - { -#ifdef SPO2_DATA_CALI - ir_data_cali = hx3695_ir_data_cali(ir_buf[ii]); - red_data_cali = hx3695_red_data_cali(red_buf[ii]); - rawdata.red_raw_data = red_data_cali>>2; - rawdata.ir_raw_data = ir_data_cali>>2; -#else - rawdata.red_raw_data = red_buf[ii]; - rawdata.ir_raw_data = ir_buf[ii]; -#endif - rawdata.vector_flag = SPO2_VECTOR_FLAG; - rawdata.data_cnt = cal.G_LEDDAC; - rawdata.hr_result = spo2_alg_results.spo2_result; - rawdata.gsensor_x = (int16_t)(green_buf[ii]>>5); - rawdata.gsensor_y = cal.R_LEDDAC; - rawdata.gsensor_z = cal.IR_LEDDAC1; - rawdata.red_cur = cal.R_LED; - rawdata.ir_cur = cal.IR_LED1; - ble_rawdata_vector_push(rawdata); - } - ble_rawdata_send_handler(); - } -#endif -///////////////////////////////////////////////////////////////////////////////////////////////// +uint8_t hx3695_get_wear_status(void) +{ + return wear_status; } -#endif //defined(HRS_ALG_LIB) && defined (SPO2_ALG_LIB) -#ifdef HRV_ALG_LIB -hrv_sensor_data_t hrv_s_dat; -void hx3695_hrv_ppg_Int_handle(void) +void hx3695_set_hrs_ble_swtich(uint8_t cmd) { - uint8_t ii=0; - hrv_results_t hrv_alg_results= {MSG_HRV_ALG_NOT_OPEN,0,0,0,0,0,1,0,0}; - int32_t *PPG_buf = &(hrv_s_dat.green_data[0]); - int32_t *ir_buf = &(hrv_s_dat.ir_data[0]); - uint8_t *count = &(hrv_s_dat.count); - hrv_wear_msg_code_t hrv_wear_status = MSG_HRV_NO_WEAR; - int16_t gsen_fifo_x_send[64]= {0}; - int16_t gsen_fifo_y_send[64]= {0}; - int16_t gsen_fifo_z_send[64]= {0}; - - // DEBUG_PRINTF("1111 \r\n" ); -#ifdef HRV_TESTVEC - int32_t hrm_raw_data; - hrm_raw_data = vec_data[vec_data_cnt]; - vec_data_cnt++; - alg_hrv_results = hx3695_hrv_alg_send_data(hrm_raw_data, 0, 0); -#else - if(hx3695_hrv_read(&hrv_s_dat) == 0) - { - TYHX_LOG("read ppg_s data invalid\r\n"); - return; - } - -#ifndef GSEN_40MS_TIMMER -// readFifoByHrsModule(); -#endif - DEBUG_PRINTF("\r\nsend jlink cnt=%d\r\n",*count); - - for(ii=0; ii<*count; ii++) - { - gsen_fifo_x_send[ii] = gsen_fifo_x[32-8+ii%8]; - gsen_fifo_y_send[ii] = gsen_fifo_y[32-8+ii%8]; - gsen_fifo_z_send[ii] = gsen_fifo_z[32-8+ii%8]; - // DEBUG_PRINTF("%d/%d %d %d %d %d %d \r\n" ,1+ii,*count,PPG_buf[ii],ir_buf[0],gsen_fifo_x_send[ii] ,gsen_fifo_y_send[ii] ,gsen_fifo_z_send[ii] ); + hrs_ble_falg = cmd; + // PRINT("hrs_ble_falg : %d \n",hrs_ble_falg); +} - } - hrv_wear_status = hx3695_hrv_get_wear_status(); -// DEBUG_PRINTF("wear:%d \r\n" ,hrv_wear_status); - if(hrv_wear_status==MSG_HRS_WEAR) - { - hrv_alg_results = tyhx_hrv_alg_send_bufdata(PPG_buf, *count, gsen_fifo_x_send, gsen_fifo_y_send, gsen_fifo_z_send); - hrsresult.lastesthrv = hrv_alg_results.hrv_result; - TYHX_LOG("get the hrv = %d\r\n",hrv_alg_results.hrv_result); - } - //--------------adjust---------------- -// hrv_alg_results.motion,hrv_alg_results.screen_up; - //DEBUG_PRINTF("data_cnt:%d hrv_result:%d motion:%d p_m:%d screen_up:%d signal_quality:%d \r\n", hrv_alg_results.data_cnt,hrv_alg_results.hrv_result,hrv_alg_results.motion,hrv_alg_results.p_m,hrv_alg_results.screen_up,hrv_alg_results.signal_quality); +uint8_t hx3695_get_hrs_ble_swtich(void) +{ + uint8_t cmd = hrs_ble_falg; + return cmd; +} + +void hx3695_wearstatus_update(void) +{ + // if(history_wear_status != wear_result) + // { + // history_wear_status = wear_result; +#ifdef SUPPORT_CYWEE_SERVICE + // do_cywee_service_check_msg(CYWEE_SERVICE_CMD_WEAR_STATUS_CHANGE,&wear_status); + cywee_wear_status_update(&wear_status); #endif + // } +} + //脱腕上报未佩戴信息 +void hx3695_unwearstatus_update(void) +{ + // hx3695_msg_callback_t func = hx3695_get_send_msg_callback_func(); + // if(func != NULL && !uapi_dev_runtime_get_train_status()) + // { + // hrsresult.lastesthrs = 0; + // hrsresult.wearstatus = 0; + // //为了主界面脱腕灵敏；需要增加未佩戴 + // func(HX3695_MSG_TYPE_HRS_UPDATE, &hrsresult, sizeof(FT_CUSTOM_RESULTS_t)); + // func(HX3695_MSG_TYPE_WEARSTAT_UPDATE, &hrsresult,sizeof(FT_CUSTOM_RESULTS_t)); + // func(HX3695_MSG_TYPE_WEARSTAT_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t)); + // func(HX3695_MSG_TYPE_WEARSTAT_UPDATE,&hrsresult,sizeof(FT_CUSTOM_RESULTS_t)); + // } -/////////////////////////////////////////BLE+DISPLAY////////////////////////////////////////// + if(uapi_dev_runtime_get_train_status()) + { + wear_result = 0; + hx3695_wearstatus_update(); + avg_hrs = 0; + } +} -#ifdef HRS_BLE_APP +void wear_mode_timeout_handler(void * p_context) +{ + // printf("wear_mode_timeout_handler \n"); + if(work_mode_flag == WEAR_MODE) { - rawdata_vector_t rawdata; - HRS_CAL_SET_T cal= get_hrs_agc_status(); - for(ii=0; ii<*count; ii++) - { - rawdata.vector_flag = HRS_VECTOR_FLAG; - rawdata.data_cnt = 0; - rawdata.hr_result = hrv_alg_results.hrv_result; - rawdata.red_raw_data = PPG_buf[ii]; - rawdata.ir_raw_data = 0; - rawdata.gsensor_x = gsen_fifo_x_send[ii]; - rawdata.gsensor_y = gsen_fifo_y_send[ii]; - rawdata.gsensor_z = gsen_fifo_z_send[ii]; - rawdata.red_cur = cal.Group1_Cur; - rawdata.ir_cur = 0; - ble_rawdata_vector_push(rawdata); - } + #ifdef CHECK_TOUCH_LIB + hx3695_ppg_Int_handle(&ppg_sensor_data); + #endif } +} - ble_rawdata_send_handler(); -#endif +void hx3695_spo2_disable(void) +{ + hx3695_ppg_set_mode(PPG_OFF); + tyhx_spo2_alg_close(); -////////////////////////////////////////////////////////////////////////////////////////////// + AGC_LOG("hx3695 disable!\r\n"); } -#endif -#ifdef CHECK_TOUCH_LIB -void hx3695_wear_ppg_Int_handle(void) +void hx3695_hrs_disable(void) { -// PRINT("hx3695_wear_ppg_Int_handle wearstatus = %d\r\n", hrsresult.wearstatus); - uint8_t *count = &(ppg_s_data.count); - int32_t *ir_buf = &(ppg_s_data.ir_data[0]); - hx3695_wear_msg_code_t hx3695_wear_status; - - hx3695_check_touch_read(&ppg_s_data); - wear_status = hx3695_check_touch_send_data(ir_buf,*count); - hx3695_wearstatus_update(); - extern uint8_t notouch_cnt; - extern uint8_t touch_cnt; - -// PRINT("===> touch_cnt: %d, notouch_cnt: %d, wear status: %d, \r\n", touch_cnt, notouch_cnt, hx3695_wear_status); - - // PRINT("hx3695_wear_ppg_Int_handle wearstatus = %d\r\n", hrsresult.wearstatus); - // PRINT("count : %d \r\n",*count); - // for(int i=0;i<*count;i++) - // { - // PRINT("%d,%d,%d,%d,%d,%d\r\n",1+i,*count,ir_buf[i],ppg_s_data.s_buf[i*2],ppg_s_data.s_buf[i*2+1],hx3695_wear_status); - // } + hx3695_ppg_set_mode(PPG_OFF); + tyhx_hrs_alg_close(); + AGC_LOG("hx3695 disable!\r\n"); } -#endif -#ifdef LAB_TEST -void hx3695_lab_test_Int_handle(void) +void hx3695_hrv_disable(void) { - NOISE_PS_T ps_noise; - ps_noise = hx3695_lab_test_read_packet(); - DEBUG_PRINTF("%d %d %d %d\r\n", ps_noise.p1_noise, ps_noise.p2_noise, ps_noise.p3_noise, ps_noise.p4_noise); + hx3695_ppg_set_mode(PPG_OFF); + tyhx_hrv_alg_close(); + + AGC_LOG("hx3695 hrv disable!\r\n"); } -#endif void hx3695_control(char *mode,uint8_t enable) { @@ -3885,15 +1542,13 @@ void hx3695_control(char *mode,uint8_t enable) md = FT_LED_OFF_MODE; } else if (strcmp(mode, "wear") == 0) { md = WEAR_MODE; - } else if (strcmp(mode, "single") == 0) { - md = FT_SINGLE_CHECK_MODE; - } + } if (enable == 1 || md == FT_LED_OFF_MODE) { hx3695_init(md); } else { - if(md == HRS_MODE|| md == FT_LEAK_LIGHT_MODE || md == FT_GRAY_CARD_MODE || md == WEAR_MODE || md == FT_SINGLE_CHECK_MODE) + if(md == HRS_MODE|| md == FT_LEAK_LIGHT_MODE || md == FT_GRAY_CARD_MODE || md == WEAR_MODE) { #ifdef HRS_ALG_LIB hx3695_hrs_disable(); @@ -3912,7 +1567,7 @@ void hx3695_control(char *mode,uint8_t enable) left = 0; right = 0; avg_hrs = 0; - wear_cnt = 0; + // wear_cnt = 0; #endif }else if(md == HRV_MODE) { @@ -3933,6 +1588,7 @@ void hx3695_control(char *mode,uint8_t enable) } } + int32_t hx3695_get_factory_data(void) { int32_t data = factory_data; @@ -3940,5 +1596,3 @@ int32_t hx3695_get_factory_data(void) return data; } -#endif //CHIP_HX3695 - diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695.h b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695.h index f976cb8b9..4402b853c 100644 --- a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695.h +++ b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695.h @@ -24,279 +24,216 @@ NEW_GSEN_SCHME DEMO调试使用， 客户关闭 */ #define HRS_ALG_LIB #define SPO2_ALG_LIB -//#define HRV_ALG_LIB + #define HRV_ALG_LIB #define CHECK_TOUCH_LIB -//#define CHECK_LIVING_LIB -//#define BP_CUSTDOWN_ALG_LIB +// #define CHECK_LIVING_LIB +#define BP_CUSTDOWN_ALG_LIB //**************** read_data_mode ******************// -#define TIMMER_MODE //timmer read fifo -//#define INT_MODE //fifo_all_most_full + #define TIMMER_MODE //timmer read fifo +//#define INT_MODE // this is fifo_all_most_full mode //****************** gsen_cgf *********************// -//#define GSEN_40MS_TIMMER -//#define NEW_GSEN_SCHME +// #define GSEN_40MS_TIMMER +// #define NEW_GSEN_SCHME +//#define TYHX_DEMO // for ty demo +//#define DOUBLE_GREEN //****************** other_cgf ********************// +// #define EVB #define DEMO_COMMON -//#define HRS_BLE_APP -//#define SPO2_DATA_CALI +// #define HRS_BLE_APP +// #define SPO2_DATA_CALI //***************** vecter_swi ********************// -//#define SPO2_VECTOR -//#define HR_VECTOR -//#define HRV_TESTVEC +// #define SPO2_VECTOR +// #define HR_VECTOR +// #define HRV_TESTVEC //**************** lab_test_mode ******************// -//#define LAB_TEST -//#define LAB_TEST_AGC +// #define LAB_TEST +// #define LAB_TEST_AGC //****************** print_swi ********************// -#define HRS_DEBUG +//#define HRS_DEBUG //#define AGC_DEBUG +//#define TYHX_DEBUG //**************************************************// -#define PREFIX_PRINTF(_message,...) //printf(_message,##__VA_ARGS__) - -#define SEGGER_RTT_printf(_message, ...) //printf(_message,##__VA_ARGS__) +// #ifdef TYHX_DEBUG +// #define TYHX_LOG(...) SEGGER_RTT_printf(0,__VA_ARGS__) +// #else +// #define TYHX_LOG(...) +// #endif #ifdef AGC_DEBUG #define AGC_LOG(...) SEGGER_RTT_printf(0,__VA_ARGS__) #else -#define AGC_LOG(...) PREFIX_PRINTF("hx3695 agc=>"__VA_ARGS__) +#define AGC_LOG(...) #endif #ifdef HRS_DEBUG #define DEBUG_PRINTF(...) SEGGER_RTT_printf(0,__VA_ARGS__) #else -#define DEBUG_PRINTF(...) PREFIX_PRINTF("hx3695 debug=>"__VA_ARGS__) +#define DEBUG_PRINTF(...) #endif - #if defined(DEMO_COMMON) - #define HRS4100_IIC_CLK 30 - #define HRS4100_IIC_SDA 0 - #define LIS3DH_IIC_CLK 18 - #define LIS3DH_IIC_SDA 16 - #define EXT_INT_PIN 1 - #define GREEN_LED_SLE 0x50 //demo 0x10 evb 2 - #define RED_LED_SLE 0x80 //demo 0x20 evb 4 - #define IR_LED_SLE 0x20 //demo 0x40 evb 1 - #define RED_AGC_OFFSET 64 //32 - #define IR_AGC_OFFSET 64 //32 - #define GREEN_AGC_OFFSET 20 //10 - #define HR_GREEN_AGC_OFFSET 48 - #define HR_GREEN1_AGC_OFFSET 48 - #define HR_GREEN2_AGC_OFFSET 48 - #define HR_GREEN3_AGC_OFFSET 48 - #define HRS_PD 0x0F // PD1:1 PD2:2 PD3:4 PD4:8 - #define SPO2_PD 0x02 // PD1:1 PD2:2 PD3:4 PD4:8 - - #define BIG_SCREEN - -#elif defined(DEMO_MI) - #define HRS4100_IIC_CLK 30 - #define HRS4100_IIC_SDA 0 - #define LIS3DH_IIC_CLK 18 - #define LIS3DH_IIC_SDA 16 - #define EXT_INT_PIN 1 - #define GREEN_LED_SLE 1 - #define RED_LED_SLE 2 - #define IR_LED_SLE 4 - #define RED_AGC_OFFSET 50 - #define IR_AGC_OFFSET 50 - #define GREEN_AGC_OFFSET 4 - #define HR_GREEN_AGC_OFFSET 4 - #define BIG_SCREEN - -#elif defined(DEMO_NEW) - #define HRS4100_IIC_CLK 30 - #define HRS4100_IIC_SDA 0 - #define LIS3DH_IIC_CLK 18 - #define LIS3DH_IIC_SDA 16 - #define EXT_INT_PIN 1 - #define GREEN_LED_SLE 1 - #define RED_LED_SLE 2 - #define IR_LED_SLE 4 - #define RED_AGC_OFFSET 75 - #define IR_AGC_OFFSET 75 - #define GREEN_AGC_OFFSET 4 - #define HR_GREEN_AGC_OFFSET 8 - #define BIG_SCREEN - -#elif defined(EVB) #define HRS4100_IIC_CLK 9 - #define HRS4100_IIC_SDA 10 + #define HRS4100_IIC_SDA 10 #define LIS3DH_IIC_CLK 13 #define LIS3DH_IIC_SDA 14 #define EXT_INT_PIN 11 - #define GREEN_LED_SLE 1 - #define RED_LED_SLE 2 - #define IR_LED_SLE 4 - #define RED_AGC_OFFSET 64 - #define IR_AGC_OFFSET 64 - #define GREEN_AGC_OFFSET 8 - #define HR_GREEN_AGC_OFFSET 10 - -#else - #define GREEN_LED_SLE 1 - #define RED_LED_SLE 4 - #define IR_LED_SLE 2 - #define RED_AGC_OFFSET 64 - #define IR_AGC_OFFSET 64 - #define GREEN_AGC_OFFSET 8 - + + #define FIFO_DATA_LENGTH 200 //fifo_max = 256 + #define PHASE_DATA_LENGTH 64 + + #define LED0_LDR_SEL 0x50 //�̵� + #define LED1_LDR_SEL 0x80 // ��� + #define LED2_LDR_SEL 0x20 // ���� + #define LED3_LDR_SEL 0x20 // ���� + + #define LED0_PD_SEL 0x0F //Ñ¡pd1 + #define LED1_PD_SEL 0x02 + #define LED2_PD_SEL 0x02 + #define LED3_PD_SEL 0x02 + + #ifdef DOUBLE_GREEN + #define LED1N_LDR_SEL 0x01 + #define LED1N_PD_SEL 0x01 + #endif + + #define CHECK_TOUCH_NUM 5 //��������ʱ,N��data + #define CHECK_WEAR_THRE 30000 + #define CHECK_UNWEAR_THRE 20000 +#elif defined(EVB) + #define HRS4100_IIC_CLK 9 + #define HRS4100_IIC_SDA 10 + #define LIS3DH_IIC_CLK 13 + #define LIS3DH_IIC_SDA 14 + #define EXT_INT_PIN 11 + + #define FIFO_DATA_LENGTH 200 //fifo_max = 256 + #define PHASE_DATA_LENGTH 64 + + #define LED0_LDR_SEL 0x10 //�̵� + #define LED1_LDR_SEL 0x08 // ��� + #define LED2_LDR_SEL 0x80 // ���� + #define LED3_LDR_SEL 0x80 // ���� + + #define LED0_PD_SEL 0x06 //Ñ¡pd2��pd3 + #define LED1_PD_SEL 0x06 + #define LED2_PD_SEL 0x06 + #define LED3_PD_SEL 0x02 + #ifdef DOUBLE_GREEN + #define LED1N_LDR_SEL 0x03 + #define LED1N_PD_SEL 0x02 + #endif + #define CHECK_TOUCH_NUM 5 //��������ʱ,N��data + #define CHECK_WEAR_THRE 30000 + #define CHECK_UNWEAR_THRE 20000 #endif -typedef enum { - PPG_INIT, - PPG_OFF, +typedef enum { + PPG_INIT, + PPG_OFF, PPG_LED_OFF, CAL_INIT, CAL_OFF, - RECAL_INIT + RECAL_INIT } hx3695_mode_t; -typedef enum { - SENSOR_OK, - SENSOR_OP_FAILED, -} SENSOR_ERROR_T; - - -typedef enum { - DATA_TYPE_PPG, - DATA_TYPE_GSEN, -} SENSOR_TYPE_T; +typedef enum { + MSG_NO_WEAR, + MSG_WEAR, + MSG_NO_INIT +} wear_msg_code_t; -typedef enum { - HRS_MODE, // 0 - SPO2_MODE, // 1 - HRSPO2_MODE, // 2 - WEAR_MODE, //3 - HRV_MODE, // 4 - LIVING_MODE, // 5 - LAB_TEST_MODE, // 6 - FT_LEAK_LIGHT_MODE, // 7 - FT_GRAY_CARD_MODE, // 8 - FT_INT_TEST_MODE, // 9 - FT_SINGLE_CHECK_MODE, +typedef enum { + HRS_MODE, + SPO2_MODE, + WEAR_MODE, + HRV_MODE, + HRSDAILY_MODE, + LIVING_MODE, + LAB_TEST_MODE, + FT_LEAK_LIGHT_MODE, + FT_GRAY_CARD_MODE, + FT_INT_TEST_MODE, + AGING_CHECK_MODE, FT_LED_OFF_MODE, FT_WEAR_MODE, - NEW_PPG_TEST_MODE, NULL_MODE, } WORK_MODE_T; - -//typedef struct { -// uint8_t count; -// int32_t green_data[64]; -// int32_t ir_data[64]; -// int32_t s_buf[64]; -// uint32_t als; -// uint32_t agc_green; -//} hrs_sensor_data_t; - - -typedef struct { - uint8_t count; - int32_t red_data[64]; - int32_t green_data[64]; - int32_t ir_data[64]; - int32_t s_buf[64]; - uint8_t green_cur; - uint8_t red_cur; - uint8_t ir_cur; - uint8_t green_offset; - uint8_t red_offset; - uint8_t ir_offset; -}ppg_sensor_data_t; - -typedef enum { - MSG_LIVING_INIT, - MSG_LIVING_NO_WEAR, - MSG_LIVING_WEAR -} hx3695_living_wear_msg_code_t; - typedef enum { - MSG_NO_WEAR, - MSG_WEAR -} hx3695_wear_msg_code_t; + InActivating, + InActivated, + Activating, + Activated, +} led_state_t; typedef struct { - hx3695_living_wear_msg_code_t wear_status; - uint32_t data_cnt; - uint8_t signal_quality; - uint8_t motion_status; -} hx3695_living_results_t; + int32_t data_val[PHASE_DATA_LENGTH]; + uint8_t data_count; + uint16_t led_current; + uint8_t offset_idac; + uint8_t tia_rf; + led_state_t led_state; + bool isneed_cal_start; +}led_data_t; typedef struct { - int32_t p1_noise; - int32_t p2_noise; - int32_t p3_noise; - int32_t p4_noise; -}NOISE_PS_T; - + WORK_MODE_T mode; + led_data_t led_data[4]; + uint8_t s_buf[FIFO_DATA_LENGTH*3]; + uint8_t led_activated; + uint8_t watermark; + uint8_t fs; +}ppg_sensor_data_t; -extern uint8_t alg_ram[11*1024]; -//extern uint8_t alg_ram[10]; +extern uint8_t alg_ram[11 * 1024]; void hx3695_delay_us(uint32_t us); void hx3695_delay_ms(uint32_t ms); -bool hx3695_write_reg(uint8_t addr, uint8_t data); -uint8_t hx3695_read_reg(uint8_t addr); -bool hx3695_brust_read_reg(uint8_t addr , uint8_t *buf, uint16_t length); +bool hx3695_write_reg(uint8_t addr, uint8_t data); +uint8_t hx3695_read_reg(uint8_t addr); +void hx3695_brust_read_reg(uint8_t addr, uint8_t *buf, uint16_t length); uint8_t hx3695_chip_check(void); -void hx3695_get_id(uint8_t *ppg_id); uint8_t hx3695_read_fifo_size(void); -uint16_t hx3695_read_fifo_data(int32_t *s_buf, uint8_t size, uint8_t phase_num); +uint16_t hx3695_read_fifo_data(ppg_sensor_data_t *ppg_sensor_data); +uint16_t hx3695_led_data_analysis(ppg_sensor_data_t *ppg_sensor_dat, uint16_t fifo_read_length, uint8_t sig); +void hx3695_get_led_para(ppg_sensor_data_t *ppg_sensor_dat); +void hx3695_read_phase_data(int32_t *s_buf); +void hx3695_read_led_data(int32_t *s_buf); void hx3695_ppg_off(void); -void hx3695_ppg_on(void); +void hx3695_ppg_on(void); +void hx3695_ppg_para_init(ppg_sensor_data_t *ppg_sensor_dat); +void hx3695_wear_low_power(ppg_sensor_data_t *ppg_sensor_dat); +void hx3695_set_fs(ppg_sensor_data_t *ppg_sensor_dat); +void hx3695_set_watermark(ppg_sensor_data_t *ppg_sensor_dat); +void hx3695_led_control(ppg_sensor_data_t *ppg_sensor_dat, uint8_t index); +void hx3695_updata_sensor(ppg_sensor_data_t *ppg_sensor_dat); +void hx3695_hrs_enable(ppg_sensor_data_t *ppg_sensor_dat); +void hx3695_spo2_enable(ppg_sensor_data_t *ppg_sensor_dat); +void hx3695_hrv_enable(ppg_sensor_data_t *ppg_sensor_dat); +void hx3695_ppg_set_mode(uint8_t mode_cmd); void hx3695_320ms_timer_cfg(bool en); void hx3695_40ms_timer_cfg(bool en); void hx3695_5000ms_timer_cfg(bool en); void hx3695_gpioint_cfg(bool en); bool hx3695_init(WORK_MODE_T mode); -void hx3695_agc_Int_handle(void); -void hx3695_gesensor_Int_handle(void); -void hx3695_spo2_ppg_init(void); -void hx3695_spo2_data_cali_init(void); -void hx3695_spo2_ppg_Int_handle(void); -void hx3695_check_touch_init(void); -void hx3695_wear_ppg_Int_handle(void); -void hx3695_hrs_ppg_init(void); -void hx3695_hrs_ppg_Int_handle(void); -void hx3695_hrv_ppg_init(void); -void hx3695_hrv_ppg_Int_handle(void); -void hx3695_living_Int_handle(void); -void hx3695_hrspo2_ppg_Int_handle(void); - - -void hx3695_ppg_Int_handle(void); -uint32_t hx3695_timers_start(void); -uint32_t hx3695_timers_stop(void); -uint32_t hx3695_gpioint_init(void); - -uint32_t hx3695_gpioint_enable(void); -uint32_t hx3695_gpioint_disable(void); -uint32_t gsen_read_timers_start(void); +void hx3695_agc_Int_handle(ppg_sensor_data_t *ppg_sensor_dat); +void hx3695_ppg_Int_handle(ppg_sensor_data_t *ppg_sensor_dat); +void heart_rate_meas_timeout_handler(void *p_context); +void agc_timeout_handler(void *p_context); +void hx3695_alg_send_data(ppg_sensor_data_t *ppg_sensor_dat, WORK_MODE_T mode, uint8_t data_count); +uint32_t hx3695_320ms_timers_stop(void); +uint32_t hx3695_320ms_timers_start(void); uint32_t gsen_read_timers_stop(void); -bool Efuse_judge(void); -void hx3695_vin_check(uint16_t led_vin); -void nrf_gpioint_handle(void); -#ifdef LAB_TEST -void hx3695_lab_test_init(void); -void hx3695_test_alg_cfg(void); -SENSOR_ERROR_T hx3695_lab_test_enable(void); -void hx3695_lab_test_Int_handle(void); -NOISE_PS_T hx3695_lab_test_read_packet(void); -#endif +uint32_t gsen_read_timers_start(void); -bool hx3695_living_send_data(int32_t *new_raw_data, uint8_t dat_len, int16_t *gsen_data_x, int16_t *gsen_data_y, int16_t *gsen_data_z); -hx3695_living_results_t hx3695_living_get_results(void); -void agc_timeout_handler(void * p_context); -void heart_rate_meas_timeout_handler(void * p_context); void wear_mode_timeout_handler(void * p_context); -void Efuse_Mode_Check(void); void hx3695_wearstatus_update(void); void hx3695_unwearstatus_update(void); void hx3695_set_hrs_ble_swtich(uint8_t cmd); @@ -305,5 +242,5 @@ uint8_t hx3695_get_hrs(void); uint8_t hx3695_get_spo2(void); uint8_t hx3695_get_wear_status(void); int32_t hx3695_get_factory_data(void); - +void hx3695_control(char *mode,uint8_t enable); #endif diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_agc.c b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_agc.c new file mode 100644 index 000000000..c71c99801 --- /dev/null +++ b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_agc.c @@ -0,0 +1,635 @@ +#include +#include +#include +#include + +#include "hx3695.h" +#include "hx3695_agc.h" +#include "tyhx_spo2_alg.h" +#include "tyhx_hrs_alg.h" + +extern uint8_t read_fifo_first_flg; +extern uint8_t s_ppg_state; +extern uint8_t s_cal_state; +static int32_t agc_buf[8] = {0}; +static agc_set_t calReg; + +void hx3695_agc_reset(void) +{ + calReg.STATE = sCalStart; + calReg.FLAG = CAL_FLG_LED_DR|CAL_FLG_LED_DAC|CAL_FLG_AMB_DAC|CAL_FLG_RF; + + calReg.LED0_IDAC = 0; + calReg.LED1_IDAC = 0; + calReg.LED2_IDAC = 0; + calReg.LED3_IDAC = 0; + calReg.AMB0_IDAC = 0; + calReg.AMB1_IDAC = 0; + calReg.AMB2_IDAC = 0; + calReg.AMB3_IDAC = 0; + + calReg.LED0_RF = 0; + calReg.LED1_RF = 0; + calReg.LED2_RF = 0; + calReg.LED3_RF = 0; + + calReg.LED0_CUR = 0; + calReg.LED1_CUR = 0; + calReg.LED2_CUR = 0; + calReg.LED3_CUR = 0; + + calReg.CAL_DELAY_CNT = 0; +} + +void Init_PPG_Calibration_Routine(agc_set_t *calR) +{ + calR->STATE = sCalStart; + calR->FLAG = CAL_FLG_LED_DR|CAL_FLG_LED_DAC|CAL_FLG_AMB_DAC|CAL_FLG_RF; + + if(AGC_SWI_LED0) + { + calR->LED0_IDAC = 0; + calR->AMB0_IDAC = 0; + calR->LED0_RF = 0; + calR->LED0_CUR = AGC_CUR_INIT_LED0; + } + if(AGC_SWI_LED1) + { + calR->LED1_IDAC = 0; + calR->AMB1_IDAC = 0; + calR->LED1_RF = 0; + calR->LED1_CUR = AGC_CUR_INIT_LED1; + } + if(AGC_SWI_LED2) + { + calR->LED2_IDAC = 0; + calR->AMB2_IDAC = 0; + calR->LED2_RF = 0; + calR->LED2_CUR = AGC_CUR_INIT_LED2; + } + if(AGC_SWI_LED3) + { + calR->LED3_IDAC = 0; + calR->AMB3_IDAC = 0; + calR->LED3_RF = 0; + calR->LED3_CUR = AGC_CUR_INIT_LED3; + } +} + +void Restart_PPG_Calibration_Routine(agc_set_t *calR) +{ + calR->FLAG = CAL_FLG_LED_DAC; + calR->STATE = sCalOffset1; +} + +void PPG_Calibration_Routine(ppg_sensor_data_t *ppg_sensor_dat, agc_set_t *calR, int32_t amb0_val, int32_t led0_val, \ + int32_t amb1_val, int32_t led1_val, int32_t amb2_val, int32_t led2_val, int32_t amb3_val, int32_t led3_val) +{ + int32_t led0_cur_temp = 0; + int32_t led1_cur_temp = 0; + int32_t led2_cur_temp = 0; + int32_t led3_cur_temp = 0; + + switch(calR->STATE) + { + case sCalStart: + { + calR->STATE = sCalCur; + break; + } + case sCalCur: + { + if(AGC_SWI_LED0 && ppg_sensor_dat->led_data[0].isneed_cal_start==1) + { + ppg_sensor_dat->led_data[0].isneed_cal_start = 0; + if(amb0_val > 535000) + { + calR->AMB0_IDAC = (amb0_val - 535000)/1250; + } + else + { + calR->AMB0_IDAC = 0; + } + if(led0_val > (amb0_val+256)) + { + calR->LED0_STEP = (led0_val - amb0_val) / AGC_CUR_INIT_LED0; + led0_cur_temp = 1250 * (AGC_IDAC_TARGET_LED0 + calR->AMB0_IDAC) / calR->LED0_STEP; + + if(led0_cur_temp > AGC_CUR_MAX_LED0) + { + calR->LED0_CUR = AGC_CUR_MAX_LED0; + } + else + { + calR->LED0_CUR = led0_cur_temp; + } + + if(calR->LED0_CUR != AGC_CUR_MAX_LED0) + { + calR->LED0_IDAC = (AGC_IDAC_TARGET_LED0*3)>>2; + } + else + { + calR->LED0_IDAC = AGC_IDAC_TARGET_LED0>>1; + } + } + calR->LED0_RF = AGC_RF_LED0; + } + #ifdef DOUBLE_GREEN + if(ppg_sensor_dat->mode == HRS_MODE) + { + if(AGC_SWI_LED1 && ppg_sensor_dat->led_data[1].isneed_cal_start==1) + { + ppg_sensor_dat->led_data[1].isneed_cal_start = 0; + if(amb1_val > 535000) + { + calR->AMB1_IDAC = (amb1_val - 535000)/1250; + } + else + { + calR->AMB1_IDAC = 0; + } + if(led1_val > (amb1_val+256)) + { + calR->LED1_STEP = (led1_val - amb1_val) / AGC_CUR_INIT_LED1; + led1_cur_temp = 1250 * (AGC_IDAC_TARGET_LED1N + calR->AMB1_IDAC) / calR->LED1_STEP; + + if(led1_cur_temp > AGC_CUR_MAX_LED1N) + { + calR->LED1_CUR = AGC_CUR_MAX_LED1N; + } + else + { + calR->LED1_CUR = led1_cur_temp; + } + + if(calR->LED1_CUR != AGC_CUR_MAX_LED1N) + { + calR->LED1_IDAC = (AGC_IDAC_TARGET_LED1N*3)>>2; + } + else + { + calR->LED1_IDAC = AGC_IDAC_TARGET_LED1N>>1; + } + } + calR->LED1_RF = AGC_RF_LED1N; + } + } + else + #endif + { + if(AGC_SWI_LED1 && ppg_sensor_dat->led_data[1].isneed_cal_start==1) + { + ppg_sensor_dat->led_data[1].isneed_cal_start = 0; + if(amb1_val > 535000) + { + calR->AMB1_IDAC = (amb1_val - 535000)/1250; + } + else + { + calR->AMB1_IDAC = 0; + } + if(led1_val > (amb1_val+256)) + { + calR->LED1_STEP = (led1_val - amb1_val) / AGC_CUR_INIT_LED1; + led1_cur_temp = 1250 * (AGC_IDAC_TARGET_LED1 + calR->AMB1_IDAC) / calR->LED1_STEP; + + if(led1_cur_temp > AGC_CUR_MAX_LED1) + { + calR->LED1_CUR = AGC_CUR_MAX_LED1; + } + else + { + calR->LED1_CUR = led1_cur_temp; + } + + if(calR->LED1_CUR != AGC_CUR_MAX_LED1) + { + calR->LED1_IDAC = (AGC_IDAC_TARGET_LED1*3)>>2; + } + else + { + calR->LED1_IDAC = AGC_IDAC_TARGET_LED1>>1; + } + } + calR->LED1_RF = AGC_RF_LED1; + } + } + + if(AGC_SWI_LED2 && ppg_sensor_dat->led_data[2].isneed_cal_start==1) + { + ppg_sensor_dat->led_data[2].isneed_cal_start = 0; + if(amb2_val > 535000) + { + calR->AMB2_IDAC = (amb2_val - 535000)/1250; + } + else + { + calR->AMB2_IDAC = 0; + } + if(led2_val > (amb2_val+256)) + { + calR->LED2_STEP = (led2_val - amb2_val) / AGC_CUR_INIT_LED2; + led2_cur_temp = 1250 * (AGC_IDAC_TARGET_LED2 + calR->AMB2_IDAC) / calR->LED2_STEP; + + if(led2_cur_temp > AGC_CUR_MAX_LED2) + { + calR->LED2_CUR = AGC_CUR_MAX_LED2; + } + else + { + calR->LED2_CUR = led2_cur_temp; + } + + if(calR->LED2_CUR != AGC_CUR_MAX_LED2) + { + calR->LED2_IDAC = (AGC_IDAC_TARGET_LED2*3)>>2; + } + else + { + calR->LED2_IDAC = AGC_IDAC_TARGET_LED2>>1; + } + } + calR->LED2_RF = AGC_RF_LED2; + } + + if(AGC_SWI_LED3 && ppg_sensor_dat->led_data[3].isneed_cal_start==1) + { + ppg_sensor_dat->led_data[3].isneed_cal_start = 0; + if(amb3_val > 535000) + { + calR->AMB3_IDAC = (amb3_val - 535000)/1250; + } + else + { + calR->AMB3_IDAC = 0; + } + if(led3_val > (amb3_val+256)) + { + calR->LED3_STEP = (led3_val - amb3_val) / AGC_CUR_INIT_LED3; + led3_cur_temp = 1250 * (AGC_IDAC_TARGET_LED3 + calR->AMB3_IDAC) / calR->LED3_STEP; + + if(led3_cur_temp > AGC_CUR_MAX_LED3) + { + calR->LED3_CUR = AGC_CUR_MAX_LED3; + } + else + { + calR->LED3_CUR = led3_cur_temp; + } + + if(calR->LED3_CUR != AGC_CUR_MAX_LED3) + { + calR->LED3_IDAC = (AGC_IDAC_TARGET_LED3*3)>>2; + } + else + { + calR->LED3_IDAC =AGC_IDAC_TARGET_LED3>>1; + } + } + calR->LED3_RF = AGC_RF_LED3; + } + + calR->FLAG = CAL_FLG_LED_DR|CAL_FLG_LED_DAC|CAL_FLG_AMB_DAC|CAL_FLG_RF; + calR->STATE = sCalOffset1; + break; + } + case sCalOffset1: + { + if(AGC_SWI_LED0 && ppg_sensor_dat->led_data[0].led_state == Activated) + { + if(led0_val>850000 && calR->LED0_IDAC < 240) + { + calR->LED0_IDAC = calR->LED0_IDAC+10; + } + } + if(AGC_SWI_LED1 && ppg_sensor_dat->led_data[1].led_state == Activated) + { + if(led1_val>850000 && calR->LED1_IDAC < 240) + { + calR->LED1_IDAC = calR->LED1_IDAC+10; + } + } + if(AGC_SWI_LED2 && ppg_sensor_dat->led_data[2].led_state == Activated) + { + if(led2_val>850000 && calR->LED2_IDAC < 240) + { + calR->LED2_IDAC = calR->LED2_IDAC+10; + } + } + if(AGC_SWI_LED3 && ppg_sensor_dat->led_data[3].led_state == Activated) + { + if(led3_val>850000 && calR->LED3_IDAC < 240) + { + calR->LED3_IDAC = calR->LED3_IDAC+10; + } + } + + if ((!AGC_SWI_LED0 || ppg_sensor_dat->led_data[0].led_state == InActivated || led0_val<=850000) \ + &&(!AGC_SWI_LED1 || ppg_sensor_dat->led_data[1].led_state == InActivated || led1_val<=850000) \ + &&(!AGC_SWI_LED2 || ppg_sensor_dat->led_data[2].led_state == InActivated || led2_val<=850000) \ + &&(!AGC_SWI_LED3 || ppg_sensor_dat->led_data[3].led_state == InActivated || led3_val<=850000) ) + { + calR->STATE = sCalOffset2; + } + else if(calR->LED0_IDAC >= 240 || calR->LED1_IDAC >= 240 || calR->LED2_IDAC >= 240 || calR->LED3_IDAC >= 240) + { + calR->STATE = sCalErr; + } + else + { + calR->STATE = sCalOffset1; + } + calR->FLAG = CAL_FLG_LED_DAC; + break; + } + case sCalOffset2: + { + if(AGC_SWI_LED0 && ppg_sensor_dat->led_data[0].led_state == Activated) + { + if(led0_val > 650000 && calR->LED0_IDAC < 240) + { + calR->LED0_IDAC = calR->LED0_IDAC+5; + } + else if(led0_val <450000 && calR->LED0_IDAC >= 5) + { + calR->LED0_IDAC = calR->LED0_IDAC-5; + } + else if(led0_val<450000 && calR->LED0_IDAC > 0) + { + calR->LED0_IDAC = calR->LED0_IDAC-1; + } + } + if(AGC_SWI_LED1 && ppg_sensor_dat->led_data[1].led_state == Activated) + { + if(led1_val > 650000 && calR->LED1_IDAC < 240) + { + calR->LED1_IDAC = calR->LED1_IDAC+5; + } + else if(led1_val <450000 && calR->LED1_IDAC >= 5) + { + calR->LED1_IDAC = calR->LED1_IDAC-5; + } + else if(led1_val<450000 && calR->LED1_IDAC > 0) + { + calR->LED1_IDAC = calR->LED1_IDAC-1; + } + } + if(AGC_SWI_LED2 && ppg_sensor_dat->led_data[2].led_state == Activated) + { + if(led2_val > 650000 && calR->LED2_IDAC < 240) + { + calR->LED2_IDAC = calR->LED2_IDAC+5; + } + else if(led2_val <450000 && calR->LED2_IDAC >= 5) + { + calR->LED2_IDAC = calR->LED2_IDAC-5; + } + else if(led2_val<450000 && calR->LED2_IDAC > 0) + { + calR->LED2_IDAC = calR->LED2_IDAC-1; + } + } + if(AGC_SWI_LED3 && ppg_sensor_dat->led_data[3].led_state == Activated) + { + if(led3_val > 650000 && calR->LED3_IDAC < 240) + { + calR->LED3_IDAC = calR->LED3_IDAC+5; + } + else if(led3_val <450000 && calR->LED3_IDAC >= 5) + { + calR->LED3_IDAC = calR->LED3_IDAC-5; + } + else if(led3_val<450000 && calR->LED3_IDAC > 0) + { + calR->LED3_IDAC = calR->LED3_IDAC-1; + } + } + + if ((!AGC_SWI_LED0 || ppg_sensor_dat->led_data[0].led_state == InActivated || (led0_val>=450000 && led0_val<=650000))\ + &&(!AGC_SWI_LED1 || ppg_sensor_dat->led_data[1].led_state == InActivated || (led1_val>=450000 && led1_val<=650000))\ + &&(!AGC_SWI_LED2 || ppg_sensor_dat->led_data[2].led_state == InActivated || (led2_val>=450000 && led2_val<=650000))\ + &&(!AGC_SWI_LED3 || ppg_sensor_dat->led_data[3].led_state == InActivated || (led3_val>=450000 && led3_val<=650000))) + { + calR->STATE = sCalFinish; + } + else if(calR->LED0_IDAC >= 240 || calR->LED1_IDAC >= 240 || calR->LED2_IDAC >= 240 || calR->LED3_IDAC >= 240) + { + calR->STATE = sCalErr; + } + else + { + calR->STATE = sCalOffset2; + } + calR->FLAG = CAL_FLG_LED_DAC; + break; + } + case sCalErr: + { + calR->STATE = sCalFinish; + break; + } + default: + { + break; + } + + } + hx3695_agc_updata_reg(calR); + //DEBUG_PRINTF("AGC:cur=%d,%d,%d,%d, idac=%d,%d,%d,%d, step=%d,%d,%d,%d, state=%d \r\n",calR->LED0_CUR,calR->LED1_CUR,calR->LED2_CUR,calR->LED3_CUR,calR->LED0_IDAC,calR->LED1_IDAC,calR->LED2_IDAC,calR->LED3_IDAC,calR->LED0_STEP,calR->LED1_STEP,calR->LED2_STEP,calR->LED3_STEP,calR->STATE); +} + +void hx3695_agc_process(ppg_sensor_data_t *ppg_sensor_dat) +{ + if (!s_cal_state && s_ppg_state) + { + hx3695_read_led_data(agc_buf); + + if ((AGC_SWI_LED0 && ppg_sensor_dat->led_data[0].led_state==Activated && (agc_buf[0]<250000 || agc_buf[0]>850000))\ + ||(AGC_SWI_LED1 && ppg_sensor_dat->led_data[1].led_state==Activated && (agc_buf[1]<250000 || agc_buf[1]>850000))\ + ||(AGC_SWI_LED2 && ppg_sensor_dat->led_data[2].led_state==Activated && (agc_buf[2]<250000 || agc_buf[2]>850000))\ + ||(AGC_SWI_LED3 && ppg_sensor_dat->led_data[3].led_state==Activated && (agc_buf[3]<250000 || agc_buf[3]>850000))) + { + calReg.CAL_DELAY_CNT++; + if(calReg.CAL_DELAY_CNT >= AGC_DELAY_COUNT_SET) + { + hx3695_ppg_set_mode(RECAL_INIT); + } + } + else + { + calReg.CAL_DELAY_CNT = 0; + } + return; + } + + hx3695_read_phase_data(agc_buf); + + PPG_Calibration_Routine(ppg_sensor_dat,&calReg,agc_buf[0],agc_buf[1],agc_buf[2],agc_buf[3],agc_buf[4],agc_buf[5],agc_buf[6],agc_buf[7]); + + if (calReg.STATE == sCalFinish) + { + hx3695_ppg_set_mode(CAL_OFF); + } +} + +void hx3695_cal_init(void) +{ + hx3695_write_reg(0x1b,0x10); + hx3695_write_reg(0x38,0x01); + hx3695_write_reg(0x60,0x34); + + hx3695_write_reg(0x5c,0x02); + hx3695_delay_ms(1); + hx3695_write_reg(0x5c,0x00); + hx3695_delay_ms(1); + + Init_PPG_Calibration_Routine(&calReg); + hx3695_agc_updata_reg(&calReg); +} + +void hx3695_recal_init(void) +{ + hx3695_write_reg(0x1b,0x10); + hx3695_write_reg(0x38,0x01); + hx3695_write_reg(0x60,0x34); + + hx3695_write_reg(0x5c,0x02); + hx3695_delay_ms(1); + hx3695_write_reg(0x5c,0x00); + hx3695_delay_ms(1); + + Restart_PPG_Calibration_Routine(&calReg); + hx3695_agc_updata_reg(&calReg); +} + +void hx3695_cal_off(void) +{ + hx3695_write_reg(0x38,0x04); + hx3695_write_reg(0x60,0x14); + + hx3695_write_reg(0x5c,0x02); + hx3695_delay_ms(1); + hx3695_write_reg(0x1b,0x91); + hx3695_write_reg(0x5c,0x00); + hx3695_delay_ms(1); + read_fifo_first_flg = 1; +} + +void hx3695_agc_updata_reg(agc_set_t *calR) +{ + uint8_t phase1_mux_sel = 0; + uint8_t phase2_mux_sel = 1; + uint8_t phase3_mux_sel = 2; + uint8_t phase4_mux_sel = 3; + uint8_t phase5_mux_sel = 4; + uint8_t phase6_mux_sel = 5; + uint8_t phase7_mux_sel = 6; + uint8_t phase8_mux_sel = 7; + + if (calR->FLAG & CAL_FLG_LED_DR) + { + if(AGC_SWI_LED0) + { + hx3695_write_reg(0X43, phase2_mux_sel); + hx3695_write_reg(0X45, calR->LED0_CUR/2); + hx3695_write_reg(0X70, calR->LED0_CUR/2); + } + if(AGC_SWI_LED1) + { + hx3695_write_reg(0X43, phase4_mux_sel); + hx3695_write_reg(0X45, calR->LED1_CUR/2); + hx3695_write_reg(0X70, calR->LED1_CUR/2); + } + if(AGC_SWI_LED2) + { + hx3695_write_reg(0X43, phase6_mux_sel); + hx3695_write_reg(0X45, calR->LED2_CUR); + } + if(AGC_SWI_LED3) + { + hx3695_write_reg(0X43, phase8_mux_sel); + hx3695_write_reg(0X45, calR->LED3_CUR); + } + } + + if (calR->FLAG & CAL_FLG_LED_DAC) + { + if(AGC_SWI_LED0) + { + hx3695_write_reg(0X43, phase2_mux_sel); + hx3695_write_reg(0X48, calR->LED0_IDAC); + } + if(AGC_SWI_LED1) + { + hx3695_write_reg(0X43, phase4_mux_sel); + hx3695_write_reg(0X48, calR->LED1_IDAC); + } + if(AGC_SWI_LED2) + { + hx3695_write_reg(0X43, phase6_mux_sel); + hx3695_write_reg(0X48, calR->LED2_IDAC); + } + if(AGC_SWI_LED3) + { + hx3695_write_reg(0X43, phase8_mux_sel); + hx3695_write_reg(0X48, calR->LED3_IDAC); + } + } + + if (calR->FLAG & CAL_FLG_AMB_DAC) + { + if(AGC_SWI_LED0) + { + hx3695_write_reg(0X43, phase1_mux_sel); + hx3695_write_reg(0X48, calR->AMB0_IDAC); + } + if(AGC_SWI_LED1) + { + hx3695_write_reg(0X43, phase3_mux_sel); + hx3695_write_reg(0X48, calR->AMB1_IDAC); + } + if(AGC_SWI_LED2) + { + hx3695_write_reg(0X43, phase5_mux_sel); + hx3695_write_reg(0X48, calR->AMB2_IDAC); + } + if(AGC_SWI_LED3) + { + hx3695_write_reg(0X43, phase7_mux_sel); + hx3695_write_reg(0X48, calR->AMB3_IDAC); + } + } + + if (calR->FLAG & CAL_FLG_RF) + { + if(AGC_SWI_LED0) + { + hx3695_write_reg(0X43, phase1_mux_sel); + hx3695_write_reg(0X44, (0x40 | calR->LED0_RF)); + hx3695_write_reg(0X43, phase2_mux_sel); + hx3695_write_reg(0X44, (0x40 | calR->LED0_RF)); + } + if(AGC_SWI_LED1) + { + hx3695_write_reg(0X43, phase3_mux_sel); + hx3695_write_reg(0X44, (0x40 | calR->LED1_RF)); + hx3695_write_reg(0X43, phase4_mux_sel); + hx3695_write_reg(0X44, (0x40 | calR->LED1_RF)); + } + if(AGC_SWI_LED2) + { + hx3695_write_reg(0X43, phase5_mux_sel); + hx3695_write_reg(0X44, (0x40 | calR->LED2_RF)); + hx3695_write_reg(0X43, phase6_mux_sel); + hx3695_write_reg(0X44, (0x40 | calR->LED2_RF)); + } + if(AGC_SWI_LED3) + { + hx3695_write_reg(0X43, phase7_mux_sel); + hx3695_write_reg(0X44, (0x40 | calR->LED3_RF)); + hx3695_write_reg(0X43, phase8_mux_sel); + hx3695_write_reg(0X44, (0x40 | calR->LED3_RF)); + } + } +} diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_agc.h b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_agc.h new file mode 100644 index 000000000..d02a19449 --- /dev/null +++ b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_agc.h @@ -0,0 +1,87 @@ +#ifndef _HX3695_SPO2_AGC_H_ +#define _HX3695_SPO2_AGC_H_ +#include +#include + +#define CAL_FLG_LED_DR 0x01 +#define CAL_FLG_LED_DAC 0x02 +#define CAL_FLG_AMB_DAC 0x04 +#define CAL_FLG_RF 0x08 + +#define AGC_SWI_LED0 1 //LEDÊÇ·ñÐèÒªµ÷¹â +#define AGC_SWI_LED1 1 +#define AGC_SWI_LED2 1 +#define AGC_SWI_LED3 0 + +#define AGC_CUR_INIT_LED0 64 //LEDµ÷¹â³õʼµçÁ÷ +#define AGC_CUR_INIT_LED1 64 +#define AGC_CUR_INIT_LED2 64 +#define AGC_CUR_INIT_LED3 64 + +#define AGC_CUR_MAX_LED0 450 //LEDµ÷¹â×î´óµçÁ÷ +#define AGC_CUR_MAX_LED1 255 +#define AGC_CUR_MAX_LED2 255 +#define AGC_CUR_MAX_LED3 255 +#define AGC_CUR_MAX_LED1N 450 + +#define AGC_RF_LED0 3 //LEDµ÷¹âÔöÒæ,0=10k,1=20k,2=50k,3=100k,4=150k,5=200k,6=500k,7=1M +#define AGC_RF_LED1 3 +#define AGC_RF_LED2 3 +#define AGC_RF_LED3 0 +#define AGC_RF_LED1N 5 + +#define AGC_IDAC_TARGET_LED0 20 //µ÷¹âÄ¿±êoffset +#define AGC_IDAC_TARGET_LED1 160 +#define AGC_IDAC_TARGET_LED2 160 +#define AGC_IDAC_TARGET_LED3 0 +#define AGC_IDAC_TARGET_LED1N 20 + +#define AGC_DELAY_COUNT_SET 4 //µ÷¹âÑÓʱ,N¸ö¶¨Ê±Æ÷»òÖÐ¶Ï + +typedef enum { + sCalStart, + sCalCur, + sCalOffset1, + sCalOffset2, + sCalFinish, + sCalErr, +} agc_state_t; + +typedef struct { + uint8_t FLAG; + uint16_t LED0_IDAC; + uint16_t LED1_IDAC; + uint16_t LED2_IDAC; + uint16_t LED3_IDAC; + uint16_t AMB0_IDAC; + uint16_t AMB1_IDAC; + uint16_t AMB2_IDAC; + uint16_t AMB3_IDAC; + uint16_t LED0_CUR; + uint16_t LED1_CUR; + uint16_t LED2_CUR; + uint16_t LED3_CUR; + uint8_t LED0_RF; + uint8_t LED1_RF; + uint8_t LED2_RF; + uint8_t LED3_RF; + uint32_t LED0_STEP; + uint32_t LED1_STEP; + uint32_t LED2_STEP; + uint32_t LED3_STEP; + uint8_t CAL_DELAY_CNT; + agc_state_t STATE; +} agc_set_t; + +void hx3695_agc_reset(void); +void Init_PPG_Calibration_Routine(agc_set_t *calR); +void Restart_PPG_Calibration_Routine(agc_set_t *calR); +void PPG_Calibration_Routine(ppg_sensor_data_t *ppg_sensor_data, agc_set_t *calR, int32_t amb0_val, int32_t led0_val, \ + int32_t amb1_val, int32_t led1_val, int32_t amb2_val, int32_t led2_val, int32_t amb3_val, int32_t led3_val); +void hx3695_agc_process(ppg_sensor_data_t *ppg_sensor); +void hx3695_cal_init(void); +void hx3695_recal_init(void); +void hx3695_cal_off(void); +void hx3695_agc_updata_reg(agc_set_t *calR); + +#endif diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_factory_test.c b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_factory_test.c index 9a94ffa7e..1ea493b4b 100644 --- a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_factory_test.c +++ b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_factory_test.c @@ -8,247 +8,224 @@ #include "hx3695.h" #include "hx3695_factory_test.h" +int32_t phase_result[10][8]; + static uint32_t factory_green = 0; static uint32_t factory_red = 0; static uint32_t factory_ir = 0; -void hx3695_factory_wear_mode_config(void) +void hx3695_factory_ft_card_test_config(void)//�ҿ�15mm�߶Ȳ������� { - uint16_t sample_rate = 10; /*config the data rate of chip alps2_fm ,uint is Hz*/ + uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/ uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */ - uint8_t adc_rst_post_num=0; /* 00=16,01=32,10=64,11=128*/ - uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ + uint16_t fifo_watermark= 250 ; + uint8_t adc_rst_post_num= 0; /* 00=16,01=32,10=64,11=128*/ + uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/ uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/ - uint8_t phase7_8_internal = 0; /* phase7 and phase8 prf internal cfg */ - + uint8_t phase7_8_internal = 0; //0x18; /* phase7 and phase8 prf internal cfg */ + +// uint16_t thred_value = 32500; + uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase3_enable = 0; /*phase3_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase4_enable = 0; /*phase4_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase5_enable = 0; /*phase5_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase6_enable = 0; /*phase6_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase7_enable = 0; /*phase7_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase8_enable = 0; /*phase8_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase5_enable = 1; /*phase5_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase6_enable = 1; /*phase6_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase7_enable = 1; /*phase7_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase1_mux_sel = 0; /* sel phase1*/ - uint8_t phase2_mux_sel = 1; /* sel phase2*/ - uint8_t phase3_mux_sel = 2; /* sel phase3*/ - uint8_t phase4_mux_sel = 3; /* sel phase4*/ - uint8_t phase5_mux_sel = 4; /* sel phase5*/ - uint8_t phase6_mux_sel = 5; /* sel phase6*/ - uint8_t phase7_mux_sel = 6; /* sel phase7*/ - uint8_t phase8_mux_sel = 7; /* sel phase8*/ + uint8_t phase1_mux_sel = 0; /* sel phase1*/ + uint8_t phase2_mux_sel = 1; /* sel phase2*/ + uint8_t phase3_mux_sel = 2; /* sel phase3*/ + uint8_t phase4_mux_sel = 3; /* sel phase4*/ + uint8_t phase5_mux_sel = 4; /* sel phase5*/ + uint8_t phase6_mux_sel = 5; /* sel phase6*/ + uint8_t phase7_mux_sel = 6; /* sel phase7*/ + uint8_t phase8_mux_sel = 7; /* sel phase8*/ - - uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase1_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase1_led_drv1_cha_sel = 0x10; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */ + uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ + uint8_t phase1_tia_res = PS_GRAD_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */ uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */ - uint8_t phase1_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase1_pd_sel = ALS_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase1_ldr1_cur = 64; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase1_ldr2_cur = 0; -// uint8_t phase1_of_idac1_cur = 0; -// uint8_t phase1_of_idac2_cur = 0; + uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase1_ldr2_cur = 0; uint8_t phase1_ad_inr_ctrl = 3; uint8_t phase1_ad_of_idac_ctrl = 0; -// uint8_t afe_offset = 0; uint8_t phase1_led_en = 1; /* phase1 led enable*/ - uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - - uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase2_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase2_led_drv1_cha_sel = 0; //GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase2_led_drv2_cha_sel = 0; - uint8_t phase2_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ + uint8_t phase2_tia_res = PS_GRAD_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase2_led_drv1_cha_sel = LDR0_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase2_led_drv2_cha_sel = 0x00; + uint8_t phase2_pd_sel = LDR0_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase2_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase2_ldr2_cur = 0; -// uint8_t phase2_of_idac1_cur = 0; -// uint8_t phase2_of_idac2_cur = 0; + uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase2_ldr1_cur = DRV1_GRAD_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase2_ldr2_cur = DRV2_GRAD_CUR; uint8_t phase2_ad_inr_ctrl = 3; uint8_t phase2_ad_of_idac_ctrl = 0; -// uint8_t phase2_afe_offset = 0; - uint8_t phase2_led_en = 1; /* phase1 led enable*/ - - uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase2_led_en = 1; /* phase1 led enable*/ + uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase3_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase3_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase3_tia_res = PS_GRAD_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase3_led_drv1_cha_sel = LDR1_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase3_led_drv2_cha_sel = 0; - uint8_t phase3_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase3_pd_sel = LDR1_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase3_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase3_ldr2_cur = 0; -// uint8_t phase3_of_idac1_cur = 0; -// uint8_t phase3_of_idac2_cur = 0; + uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase3_ldr1_cur = DRV1_GRAD_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase3_ldr2_cur = DRV2_GRAD_CUR; uint8_t phase3_ad_inr_ctrl = 3; uint8_t phase3_ad_of_idac_ctrl = 0; // uint8_t phase3_afe_offset = 0; uint8_t phase3_led_en = 1; /* phase1 led enable*/ - - uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase4_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase4_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase4_tia_res = PS_GRAD_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase4_led_drv1_cha_sel = LDR2_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase4_led_drv2_cha_sel = 0; - uint8_t phase4_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase4_pd_sel = LDR2_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase4_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase4_ldr2_cur = 0; -// uint8_t phase4_of_idac1_cur = 0; -// uint8_t phase4_of_idac2_cur = 0; + uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase4_ldr1_cur = DRV1_GRAD_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase4_ldr2_cur = DRV2_GRAD_CUR; uint8_t phase4_ad_inr_ctrl = 3; uint8_t phase4_ad_of_idac_ctrl = 0; // uint8_t phase4_afe_offset = 0; - uint8_t phase4_led_en = 1; /* phase1 led enable*/ - - uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase4_led_en = 1; /* phase1 led enable*/ + uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase5_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase5_tia_res = PS_GRAD_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase5_led_drv1_cha_sel = LDR3_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase5_led_drv2_cha_sel = 0; - uint8_t phase5_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ + uint8_t phase5_pd_sel = LDR3_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */ uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase5_ldr2_cur = 0; -// uint8_t phase5_of_idac1_cur = 0; -// uint8_t phase5_of_idac2_cur = 0; + uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase5_ldr1_cur = DRV1_GRAD_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase5_ldr2_cur = DRV2_GRAD_CUR; uint8_t phase5_ad_inr_ctrl = 3; uint8_t phase5_ad_of_idac_ctrl = 0; // uint8_t phase5_afe_offset = 0; - uint8_t phase5_led_en = 1; /* phase1 led enable*/ - - uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase5_led_en = 1; /* phase1 led enable*/ + uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase6_tia_res = PS_GRAD_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase6_led_drv1_cha_sel = LDR4_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase6_led_drv2_cha_sel = 0; - uint8_t phase6_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ + uint8_t phase6_pd_sel = LDR4_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */ uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase6_ldr2_cur = 0; -// uint8_t phase6_of_idac1_cur = 0; -// uint8_t phase6_of_idac2_cur = 0; + uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase6_ldr1_cur = DRV1_GRAD_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase6_ldr2_cur = DRV2_GRAD_CUR; uint8_t phase6_ad_inr_ctrl = 3; uint8_t phase6_ad_of_idac_ctrl = 0; // uint8_t phase6_afe_offset = 0; - uint8_t phase6_led_en = 1; /* phase1 led enable*/ - - uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase6_led_en = 1; /* phase1 led enable*/ + uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase7_tia_res = PS_GRAD_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase7_led_drv1_cha_sel = LDR5_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase7_led_drv2_cha_sel = 0; - uint8_t phase7_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ + uint8_t phase7_pd_sel = LDR5_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */ uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase7_ldr2_cur = 0; -// uint8_t phase7_of_idac1_cur = 0; -// uint8_t phase7_of_idac2_cur = 0; + uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase7_ldr1_cur = DRV1_GRAD_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase7_ldr2_cur = DRV2_GRAD_CUR; uint8_t phase7_ad_inr_ctrl = 3; uint8_t phase7_ad_of_idac_ctrl = 0; // uint8_t phase7_afe_offset = 0; - uint8_t phase7_led_en = 1; /* phase1 led enable*/ - - uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase7_led_en = 1; /* phase1 led enable*/ + uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase8_led_drv1_cha_sel = 0; //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase8_tia_res = 1; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase8_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase8_led_drv2_cha_sel = 0; - uint8_t phase8_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ + uint8_t phase8_pd_sel = 0; /* 1 = pd1; 2 = pd2; */ uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ uint8_t phase8_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase8_ldr2_cur = 0; -// uint8_t phase8_of_idac1_cur = 0; -// uint8_t phase8_of_idac2_cur = 0; + uint8_t phase8_ldr2_cur = 0; uint8_t phase8_ad_inr_ctrl = 3; uint8_t phase8_ad_of_idac_ctrl = 0; // uint8_t phase8_afe_offset = 0; - uint8_t phase8_led_en = 1; /* phase1 led enable*/ - - uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase8_led_en = 0; /* phase1 led enable*/ + uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - uint8_t init_wait_delay = 5 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ; + uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ; 4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ; 4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */ - uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/ - + uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/ + uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ - - uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ - + + uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ + uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ; 4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */ hx3695_delay_ms(10); - + hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6 hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8> hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); - hx3695_write_reg(0X2d, phase7_8_internal); - hx3695_write_reg(0X2e, 0x33);// gpio ctrl + hx3695_write_reg(0X2d, phase7_8_internal); + hx3695_write_reg(0X2e, 0x33);// gpio ctrl hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay)); - hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); + hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); hx3695_write_reg(0X31, (led_on_time<<4| 0x00)); - hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置； - hx3695_write_reg(0X34, 0x00);// 中断特殊配置； - hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置； - hx3695_write_reg(0X38, 0x00); + hx3695_write_reg(0X33, 0x83);// �жϼ��Լ��������ã� + hx3695_write_reg(0X34, 0x00);// �ж��������ã� + hx3695_write_reg(0X36, 0x00);// phase data ready ��־���ã� + hx3695_write_reg(0X38, 0x00); hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); @@ -257,172 +234,156 @@ void hx3695_factory_wear_mode_config(void) hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num ); hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num ); - - hx3695_write_reg(0X43, phase1_mux_sel); - hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); - hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase1_als_offset_idac); - hx3695_write_reg(0X48, phase1_led_offset_idac); - + hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num ); + hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num ); + + hx3695_write_reg(0X43, phase1_mux_sel); + hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); + hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase1_als_offset_idac); + hx3695_write_reg(0X48, phase1_led_offset_idac); hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4); -// hx3695_write_reg(0X4e, thred_value); -// hx3695_write_reg(0X4f, thred_value>>5); - + hx3695_write_reg(0X43, phase2_mux_sel); - hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); - hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase2_als_offset_idac); - hx3695_write_reg(0X48, phase2_led_offset_idac); + hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); + hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase2_als_offset_idac); + hx3695_write_reg(0X48, phase2_led_offset_idac); // hx3695_write_reg(0X48, phase1_led_offset_idac); hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4); //phase3 sel hx3695_write_reg(0X43, phase3_mux_sel); - hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); - hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase3_als_offset_idac); - hx3695_write_reg(0X48, phase3_led_offset_idac); + hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); + hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase3_als_offset_idac); + hx3695_write_reg(0X48, phase3_led_offset_idac); // hx3695_write_reg(0X48, phase1_led_offset_idac); hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4); //phase4 sel hx3695_write_reg(0X43, phase4_mux_sel); - hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); - hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase4_als_offset_idac); - hx3695_write_reg(0X48, phase4_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); + hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); + hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase4_als_offset_idac); + hx3695_write_reg(0X48, phase4_led_offset_idac); hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4); - - hx3695_write_reg(0X43, phase5_mux_sel); - hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); - hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase5_pd_sel)); //<<4 | 0x00)); - hx3695_write_reg(0X47, phase5_als_offset_idac); - hx3695_write_reg(0X48, phase5_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); + hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4); + + hx3695_write_reg(0X43, phase5_mux_sel); + hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); + hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase5_als_offset_idac); + hx3695_write_reg(0X48, phase5_led_offset_idac); hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase6_mux_sel); - hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); - hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase6_als_offset_idac); - hx3695_write_reg(0X48, phase6_led_offset_idac); -// hx3695_write_reg(0X48, phase6_led_offset_idac); + hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4); + + + hx3695_write_reg(0X43, phase6_mux_sel); + hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); + hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase6_als_offset_idac); + hx3695_write_reg(0X48, phase6_led_offset_idac); hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4); - hx3695_write_reg(0X43, phase7_mux_sel); - hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); - hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase7_als_offset_idac); - hx3695_write_reg(0X48, phase7_led_offset_idac); -// hx3695_write_reg(0X48, phase7_led_offset_idac); + hx3695_write_reg(0X43, phase7_mux_sel); + hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); + hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase7_als_offset_idac); + hx3695_write_reg(0X48, phase7_led_offset_idac); hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4); - hx3695_write_reg(0X43, phase8_mux_sel); - hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); - hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase8_als_offset_idac); - hx3695_write_reg(0X48, phase8_led_offset_idac); -// hx3695_write_reg(0X48, phas8_led_offset_idac); + hx3695_write_reg(0X43, phase8_mux_sel); + hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); + hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase8_als_offset_idac); + hx3695_write_reg(0X48, phase8_led_offset_idac); hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4); // analog circuit cfg - hx3695_write_reg(0X60, 0x14); // - hx3695_write_reg(0X61, 0xf0); - hx3695_write_reg(0X62, 0x22); - hx3695_write_reg(0X63, 0x15); - - hx3695_write_reg(0X64, 0x08); - hx3695_write_reg(0X65, 0x88); //bug - - hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30 - hx3695_write_reg(0X67, 0x23); - hx3695_write_reg(0X68, 0x46); - hx3695_write_reg(0X69, 0x42); - - hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg - hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable + hx3695_write_reg(0X60, 0x34); // + hx3695_write_reg(0X61, 0xf0); + hx3695_write_reg(0X62, 0x22); + hx3695_write_reg(0X63, 0x15); + + hx3695_write_reg(0X64, 0x08); + hx3695_write_reg(0X65, 0x88); //bug + + hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30 + hx3695_write_reg(0X67, 0x23); + hx3695_write_reg(0X68, 0x46); + hx3695_write_reg(0X69, 0x42); + + hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg + hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable hx3695_write_reg(0X6a, 0X0f); - hx3695_write_reg(0X6b, 0X22); - hx3695_write_reg(0X6c, 0X00); - hx3695_write_reg(0X6d, 0X37); - hx3695_write_reg(0X6e, 0X82); - hx3695_write_reg(0X6f, 0X08); + hx3695_write_reg(0X6b, 0X22); + hx3695_write_reg(0X6c, 0X00); + hx3695_write_reg(0X6d, 0X37); + hx3695_write_reg(0X6e, 0X82); + hx3695_write_reg(0X6f, 0X00); /////////FIFO and adc conversion ready config//////// /////////FIFO and adc conversion ready config//////// -#if defined(PPG_INT_MODE) - hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ - bits<7> fifo enble - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear - hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int -#elif defined(INT_MODE) //FIFO_ALL_MOST_FULL) - hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ - bits<7> fifo enble - hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark - hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear - hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int +#if defined(INT_MODE) //(FIFO_ALL_MOST_FULL) + hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ + 0011=p4;0100=p5;0101=p6;0110=p7;\ + bits<7> fifo enble + hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark + hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] + hx3695_write_reg(0X33, 0x83); // int width + hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int #else - hx3695_write_reg(0X1b, 0x92); // bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3; - // 0011=p4;0100=p5;0101=p6;0110=p7; - // bits<7> fifo enble - hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int - + hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;0011=p4;0100=p5;0101=p6;0110=p7;bits<7> fifo enble + hx3695_write_reg(0X36, 0x00); //intrupt + + hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int + #endif @@ -434,217 +395,183 @@ void hx3695_factory_wear_mode_config(void) // hx3695_write_reg(0X5c, 0x02);//soft reset hx3695_delay_ms(5); hx3695_write_reg(0X5c, 0x00);//release -// read_fifo_first_flg = 1; - return ; - - - + + return ; } -void hx3695_factory_ft_card_test_config(void)//灰卡15mm高度测试配置 + + +void hx3695_factory_ft_leak_light_test_config(void)//©��������� { - uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/ + uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/ uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */ - -// uint16_t fifo_watermark= 250 ; + + uint16_t fifo_watermark= 250 ; uint8_t adc_rst_post_num= 0; /* 00=16,01=32,10=64,11=128*/ - uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ + uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/ uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/ - uint8_t phase7_8_internal = 0; //0x18; /* phase7 and phase8 prf internal cfg */ - -// uint16_t thred_value = 32500; + uint8_t phase7_8_internal = 0; //0x18; /* phase7 and phase8 prf internal cfg */ + uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase5_enable = 0; /*phase5_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase6_enable = 0; /*phase6_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase7_enable = 0; /*phase7_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase8_enable = 0; /*phase8_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase5_enable = 1; /*phase5_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase6_enable = 1; /*phase6_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase7_enable = 1; /*phase7_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase1_mux_sel = 0; /* sel phase1*/ - uint8_t phase2_mux_sel = 1; /* sel phase2*/ - uint8_t phase3_mux_sel = 2; /* sel phase3*/ - uint8_t phase4_mux_sel = 3; /* sel phase4*/ - uint8_t phase5_mux_sel = 4; /* sel phase5*/ - uint8_t phase6_mux_sel = 5; /* sel phase6*/ - uint8_t phase7_mux_sel = 6; /* sel phase7*/ - uint8_t phase8_mux_sel = 7; /* sel phase8*/ + uint8_t phase1_mux_sel = 0; /* sel phase1*/ + uint8_t phase2_mux_sel = 1; /* sel phase2*/ + uint8_t phase3_mux_sel = 2; /* sel phase3*/ + uint8_t phase4_mux_sel = 3; /* sel phase4*/ + uint8_t phase5_mux_sel = 4; /* sel phase5*/ + uint8_t phase6_mux_sel = 5; /* sel phase6*/ + uint8_t phase7_mux_sel = 6; /* sel phase7*/ + uint8_t phase8_mux_sel = 7; /* sel phase8*/ - uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase1_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ + uint8_t phase1_tia_res = PS_LEAK_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */ uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */ - uint8_t phase1_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase1_pd_sel = ALS_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase1_ldr1_cur = 32; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase1_ldr2_cur = 0; -// uint8_t phase1_of_idac1_cur = 0; -// uint8_t phase1_of_idac2_cur = 0; + uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase1_ldr2_cur = 0; uint8_t phase1_ad_inr_ctrl = 3; uint8_t phase1_ad_of_idac_ctrl = 0; -// uint8_t afe_offset = 0; - uint8_t phase1_led_en = 1; /* phase1 led enable*/ - - uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase1_led_en = 1; /* phase1 led enable*/ + uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase2_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase2_led_drv1_cha_sel = GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ + uint8_t phase2_tia_res = PS_LEAK_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase2_led_drv1_cha_sel = LDR0_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase2_led_drv2_cha_sel = 0x00; - uint8_t phase2_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase2_pd_sel = LDR0_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase2_ldr1_cur = 32; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase2_ldr2_cur = 0; -// uint8_t phase2_of_idac1_cur = 0; -// uint8_t phase2_of_idac2_cur = 0; + uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase2_ldr1_cur = DRV1_LEAK_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase2_ldr2_cur = DRV2_LEAK_CUR; uint8_t phase2_ad_inr_ctrl = 3; uint8_t phase2_ad_of_idac_ctrl = 0; -// uint8_t phase2_afe_offset = 0; - uint8_t phase2_led_en = 1; /* phase1 led enable*/ - - uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase2_led_en = 1; /* phase1 led enable*/ + uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase3_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase3_led_drv1_cha_sel = RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase3_tia_res = PS_LEAK_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase3_led_drv1_cha_sel = LDR1_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase3_led_drv2_cha_sel = 0; - uint8_t phase3_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase3_pd_sel = LDR1_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase3_ldr1_cur = 32; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase3_ldr2_cur = 0; -// uint8_t phase3_of_idac1_cur = 0; -// uint8_t phase3_of_idac2_cur = 0; + uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase3_ldr1_cur = DRV1_LEAK_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase3_ldr2_cur = DRV2_LEAK_CUR; uint8_t phase3_ad_inr_ctrl = 3; uint8_t phase3_ad_of_idac_ctrl = 0; -// uint8_t phase3_afe_offset = 0; - uint8_t phase3_led_en = 1; /* phase1 led enable*/ - - uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase3_led_en = 1; /* phase1 led enable*/ + uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase4_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase4_led_drv1_cha_sel = IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase4_tia_res = PS_LEAK_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase4_led_drv1_cha_sel = LDR2_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase4_led_drv2_cha_sel = 0; - uint8_t phase4_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase4_pd_sel = LDR2_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase4_ldr1_cur = 32; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase4_ldr2_cur = 0; -// uint8_t phase4_of_idac1_cur = 0; -// uint8_t phase4_of_idac2_cur = 0; + uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase4_ldr1_cur = DRV1_LEAK_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase4_ldr2_cur = DRV2_LEAK_CUR; uint8_t phase4_ad_inr_ctrl = 3; uint8_t phase4_ad_of_idac_ctrl = 0; -// uint8_t phase4_afe_offset = 0; - uint8_t phase4_led_en = 1; /* phase1 led enable*/ - - uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase4_led_en = 1; /* phase1 led enable*/ + uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase5_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase5_tia_res = PS_LEAK_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase5_led_drv1_cha_sel = LDR3_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase5_led_drv2_cha_sel = 0; - uint8_t phase5_pd_sel = 0x0a; /* 1 = pd1; 2 = pd2; */ + uint8_t phase5_pd_sel =LDR3_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */ uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase5_ldr2_cur = 0; -// uint8_t phase5_of_idac1_cur = 0; -// uint8_t phase5_of_idac2_cur = 0; + uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase5_ldr1_cur = DRV1_LEAK_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase5_ldr2_cur = DRV2_LEAK_CUR; uint8_t phase5_ad_inr_ctrl = 3; uint8_t phase5_ad_of_idac_ctrl = 0; -// uint8_t phase5_afe_offset = 0; - uint8_t phase5_led_en = 1; /* phase1 led enable*/ - - uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase5_led_en = 1; /* phase1 led enable*/ + uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase6_tia_res = PS_LEAK_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase6_led_drv1_cha_sel = LDR4_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase6_led_drv2_cha_sel = 0; - uint8_t phase6_pd_sel = 4; /* 1 = pd1; 2 = pd2; */ + uint8_t phase6_pd_sel = LDR4_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */ uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase6_ldr2_cur = 0; -// uint8_t phase6_of_idac1_cur = 0; -// uint8_t phase6_of_idac2_cur = 0; + uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase6_ldr1_cur = DRV1_LEAK_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase6_ldr2_cur = DRV2_LEAK_CUR; uint8_t phase6_ad_inr_ctrl = 3; uint8_t phase6_ad_of_idac_ctrl = 0; -// uint8_t phase6_afe_offset = 0; - uint8_t phase6_led_en = 1; /* phase1 led enable*/ - - uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase6_led_en = 1; /* phase1 led enable*/ + uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase7_tia_res = PS_LEAK_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase7_led_drv1_cha_sel = LDR5_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase7_led_drv2_cha_sel = 0; - uint8_t phase7_pd_sel = 0x00; /* 1 = pd1; 2 = pd2; */ + uint8_t phase7_pd_sel = LDR5_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */ uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase7_ldr2_cur = 0; -// uint8_t phase7_of_idac1_cur = 0; -// uint8_t phase7_of_idac2_cur = 0; + uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase7_ldr1_cur = DRV1_LEAK_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase7_ldr2_cur = DRV2_LEAK_CUR; uint8_t phase7_ad_inr_ctrl = 3; uint8_t phase7_ad_of_idac_ctrl = 0; -// uint8_t phase7_afe_offset = 0; - uint8_t phase7_led_en = 1; /* phase1 led enable*/ - - uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase7_led_en = 1; /* phase1 led enable*/ + uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase8_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ uint8_t phase8_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase8_led_drv2_cha_sel = 0; - uint8_t phase8_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ + uint8_t phase8_pd_sel = 0; /* 1 = pd1; 2 = pd2; */ uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ uint8_t phase8_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase8_ldr2_cur = 0; -// uint8_t phase8_of_idac1_cur = 0; -// uint8_t phase8_of_idac2_cur = 0; + uint8_t phase8_ldr2_cur = 0; uint8_t phase8_ad_inr_ctrl = 3; uint8_t phase8_ad_of_idac_ctrl = 0; -// uint8_t phase8_afe_offset = 0; - uint8_t phase8_led_en = 1; /* phase1 led enable*/ - - uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase8_led_en = 1; /* phase1 led enable*/ + uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ; @@ -653,12 +580,12 @@ void hx3695_factory_ft_card_test_config(void)//灰卡15mm高度测试配置 uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ; 4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */ - uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/ - + uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/ + uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ - - uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ - + + uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ + uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ; 4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */ @@ -669,18 +596,18 @@ void hx3695_factory_ft_card_test_config(void)//灰卡15mm高度测试配置 hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); - hx3695_write_reg(0X2d, phase7_8_internal); - hx3695_write_reg(0X2e, 0x33);// gpio ctrl + hx3695_write_reg(0X2d, phase7_8_internal); + hx3695_write_reg(0X2e, 0x33);// gpio ctrl hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay)); - hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); + hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); hx3695_write_reg(0X31, (led_on_time<<4| 0x00)); - hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置； - hx3695_write_reg(0X34, 0x00);// 中断特殊配置； - hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置； - hx3695_write_reg(0X38, 0x00); + hx3695_write_reg(0X33, 0x83);// �жϼ��Լ��������ã� + hx3695_write_reg(0X34, 0x00);// �ж��������ã� + hx3695_write_reg(0X36, 0x00);// phase data ready ��־���ã� + hx3695_write_reg(0X38, 0x00); hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); @@ -689,423 +616,373 @@ void hx3695_factory_ft_card_test_config(void)//灰卡15mm高度测试配置 hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num ); hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num ); - - hx3695_write_reg(0X43, phase1_mux_sel); - hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); - hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase1_als_offset_idac); - hx3695_write_reg(0X48, phase1_led_offset_idac); + hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num ); + hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num ); + + hx3695_write_reg(0X43, phase1_mux_sel); + hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); + hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase1_als_offset_idac); + hx3695_write_reg(0X48, phase1_led_offset_idac); hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4); hx3695_write_reg(0X43, phase2_mux_sel); - hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); - hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase2_als_offset_idac); - hx3695_write_reg(0X48, phase2_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); + hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); + hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase2_als_offset_idac); + hx3695_write_reg(0X48, phase2_led_offset_idac); hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4); //phase3 sel hx3695_write_reg(0X43, phase3_mux_sel); - hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); - hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase3_als_offset_idac); - hx3695_write_reg(0X48, phase3_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); + hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); + hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase3_als_offset_idac); + hx3695_write_reg(0X48, phase3_led_offset_idac); hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4); //phase4 sel hx3695_write_reg(0X43, phase4_mux_sel); - hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); - hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase4_als_offset_idac); - hx3695_write_reg(0X48, phase4_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); + hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); + hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase4_als_offset_idac); + hx3695_write_reg(0X48, phase4_led_offset_idac); hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4); - - hx3695_write_reg(0X43, phase5_mux_sel); - hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); - hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase5_als_offset_idac); - hx3695_write_reg(0X48, phase5_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); + hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4); + + hx3695_write_reg(0X43, phase5_mux_sel); + hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); + hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase5_als_offset_idac); + hx3695_write_reg(0X48, phase5_led_offset_idac); hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase6_mux_sel); - hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); - hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase6_als_offset_idac); - hx3695_write_reg(0X48, phase6_led_offset_idac); -// hx3695_write_reg(0X48, phase6_led_offset_idac); + hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4); + + + hx3695_write_reg(0X43, phase6_mux_sel); + hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); + hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase6_als_offset_idac); + hx3695_write_reg(0X48, phase6_led_offset_idac); hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4); - hx3695_write_reg(0X43, phase7_mux_sel); - hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); - hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase7_als_offset_idac); - hx3695_write_reg(0X48, phase7_led_offset_idac); -// hx3695_write_reg(0X48, phase7_led_offset_idac); + hx3695_write_reg(0X43, phase7_mux_sel); + hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); + hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase7_als_offset_idac); + hx3695_write_reg(0X48, phase7_led_offset_idac); hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4); - hx3695_write_reg(0X43, phase8_mux_sel); - hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); - hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase8_als_offset_idac); - hx3695_write_reg(0X48, phase8_led_offset_idac); -// hx3695_write_reg(0X48, phas8_led_offset_idac); + hx3695_write_reg(0X43, phase8_mux_sel); + hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); + hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase8_als_offset_idac); + hx3695_write_reg(0X48, phase8_led_offset_idac); hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4); // analog circuit cfg - hx3695_write_reg(0X60, 0x14); // - hx3695_write_reg(0X61, 0xf0); - hx3695_write_reg(0X62, 0x22); - hx3695_write_reg(0X63, 0x15); - - hx3695_write_reg(0X64, 0x08); - hx3695_write_reg(0X65, 0x88); //bug - - hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30 - hx3695_write_reg(0X67, 0x23); - hx3695_write_reg(0X68, 0x46); - hx3695_write_reg(0X69, 0x42); - - hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg - hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable + hx3695_write_reg(0X60, 0x34); // + hx3695_write_reg(0X61, 0xf0); + hx3695_write_reg(0X62, 0x22); + hx3695_write_reg(0X63, 0x15); + + hx3695_write_reg(0X64, 0x08); + hx3695_write_reg(0X65, 0x88); //bug + + hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30 + hx3695_write_reg(0X67, 0x23); + hx3695_write_reg(0X68, 0x46); + hx3695_write_reg(0X69, 0x42); + + hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg + hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable hx3695_write_reg(0X6a, 0X0f); - hx3695_write_reg(0X6b, 0X22); - hx3695_write_reg(0X6c, 0X00); - hx3695_write_reg(0X6d, 0X37); - hx3695_write_reg(0X6e, 0X82); - hx3695_write_reg(0X6f, 0X08); + hx3695_write_reg(0X6b, 0X22); + hx3695_write_reg(0X6c, 0X00); + hx3695_write_reg(0X6d, 0X37); + hx3695_write_reg(0X6e, 0X82); + hx3695_write_reg(0X6f, 0X00); /////////FIFO and adc conversion ready config//////// /////////FIFO and adc conversion ready config//////// -#if defined(PPG_INT_MODE) - hx3695_write_reg(0X1b, 0x00);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ - bits<7> fifo enble - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear - hx3695_write_reg(0X38, 0x08); // int sel,00=close almost full int,04=enable almost full int -#elif defined(INT_MODE) //(FIFO_ALL_MOST_FULL) - hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ - bits<7> fifo enble - hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark - hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int +#if defined(INT_MODE) //(FIFO_ALL_MOST_FULL) + hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ + 0011=p4;0100=p5;0101=p6;0110=p7;\ + bits<7> fifo enble + hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark + hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] + hx3695_write_reg(0X33, 0x83); // int width + hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int #else - hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3; - // 0011=p4;0100=p5;0101=p6;0110=p7; - // bits<7> fifo enble - hx3695_write_reg(0X36, 0x00); //intrupt - - hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int + hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;0011=p4;0100=p5;0101=p6;0110=p7;bits<7> fifo enble + hx3695_write_reg(0X36, 0x00); //intrupt + + hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int #endif - hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); - hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); - hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) ); - hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); + hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); + hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); + hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) ); + hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); // hx3695_write_reg(0X5c, 0x02);//soft reset - hx3695_delay_ms(5); - hx3695_write_reg(0X5c, 0x00);//release + hx3695_delay_ms(5); + hx3695_write_reg(0X5c, 0x00);//release - return ; + return ; } - -void hx3695_factory_ft_single_check_config(void)//灰卡10mm高度测试配置 +void hx3695_factory_Gnoise_config(void) // ������� { - - uint16_t sample_rate = 200; /*config the data rate of chip alps2_fm ,uint is Hz*/ + uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/ uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */ - - uint8_t adc_rst_post_num=0; /* 00=16,01=32,10=64,11=128*/ - uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ + + uint16_t fifo_watermark= 250 ; + uint8_t adc_rst_post_num= 0; /* 00=16,01=32,10=64,11=128*/ + uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/ uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/ - uint8_t phase7_8_internal = 0; /* phase7 and phase8 prf internal cfg */ - + uint8_t phase7_8_internal = 0; //0x18; /* phase7 and phase8 prf internal cfg */ + uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase5_enable = 0; /*phase5_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase6_enable = 0; /*phase6_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase7_enable = 0; /*phase7_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase8_enable = 0; /*phase8_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase5_enable = 1; /*phase5_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase6_enable = 1; /*phase6_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase7_enable = 1; /*phase7_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase1_mux_sel = 0; /* sel phase1*/ - uint8_t phase2_mux_sel = 1; /* sel phase2*/ - uint8_t phase3_mux_sel = 2; /* sel phase3*/ - uint8_t phase4_mux_sel = 3; /* sel phase4*/ - uint8_t phase5_mux_sel = 4; /* sel phase5*/ - uint8_t phase6_mux_sel = 5; /* sel phase6*/ - uint8_t phase7_mux_sel = 6; /* sel phase7*/ - uint8_t phase8_mux_sel = 7; /* sel phase8*/ + uint8_t phase1_mux_sel = 0; /* sel phase1*/ + uint8_t phase2_mux_sel = 1; /* sel phase2*/ + uint8_t phase3_mux_sel = 2; /* sel phase3*/ + uint8_t phase4_mux_sel = 3; /* sel phase4*/ + uint8_t phase5_mux_sel = 4; /* sel phase5*/ + uint8_t phase6_mux_sel = 5; /* sel phase6*/ + uint8_t phase7_mux_sel = 6; /* sel phase7*/ + uint8_t phase8_mux_sel = 7; /* sel phase8*/ - uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase1_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ + uint8_t phase1_tia_res = PS_Gnoise_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */ uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */ - uint8_t phase1_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase1_pd_sel = ALS_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase1_ldr2_cur = 0; -// uint8_t phase1_of_idac1_cur = 0; -// uint8_t phase1_of_idac2_cur = 0; + uint8_t phase1_ldr2_cur = 0; uint8_t phase1_ad_inr_ctrl = 3; uint8_t phase1_ad_of_idac_ctrl = 0; -// uint8_t afe_offset = 0; - uint8_t phase1_led_en = 1; /* phase1 led enable*/ - - uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase1_led_en = 0; /* phase1 led enable*/ + uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase2_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase2_led_drv1_cha_sel = GREEN_LED_SLE; //GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ + uint8_t phase2_tia_res = 3; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase2_led_drv1_cha_sel = LDR0_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase2_led_drv2_cha_sel = 0x00; - uint8_t phase2_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase2_pd_sel = LDR0_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase2_ldr1_cur = 16; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase2_ldr2_cur = 0; -// uint8_t phase2_of_idac1_cur = 0; -// uint8_t phase2_of_idac2_cur = 0; + uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase2_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase2_ldr2_cur = 0; uint8_t phase2_ad_inr_ctrl = 3; uint8_t phase2_ad_of_idac_ctrl = 0; -// uint8_t phase2_afe_offset = 0; - uint8_t phase2_led_en = 1; /* phase1 led enable*/ - - uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase2_led_en = 0; /* phase1 led enable*/ + uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase3_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase3_led_drv1_cha_sel = RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase3_tia_res = PS_Gnoise_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase3_led_drv1_cha_sel = LDR1_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase3_led_drv2_cha_sel = 0; - uint8_t phase3_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase3_pd_sel = LDR1_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase3_ldr1_cur = 16; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase3_ldr2_cur = 0; -// uint8_t phase3_of_idac1_cur = 0; -// uint8_t phase3_of_idac2_cur = 0; + uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase3_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase3_ldr2_cur = 0; uint8_t phase3_ad_inr_ctrl = 3; uint8_t phase3_ad_of_idac_ctrl = 0; -// uint8_t phase3_afe_offset = 0; - uint8_t phase3_led_en = 1; /* phase1 led enable*/ - - uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase3_led_en = 0; /* phase1 led enable*/ + uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase4_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase4_led_drv1_cha_sel = IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase4_tia_res = PS_Gnoise_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase4_led_drv1_cha_sel = LDR2_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase4_led_drv2_cha_sel = 0; - uint8_t phase4_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase4_pd_sel = LDR2_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase4_ldr1_cur = 16; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase4_ldr2_cur = 0; -// uint8_t phase4_of_idac1_cur = 0; -// uint8_t phase4_of_idac2_cur = 0; + uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase4_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase4_ldr2_cur = 0; uint8_t phase4_ad_inr_ctrl = 3; uint8_t phase4_ad_of_idac_ctrl = 0; -// uint8_t phase4_afe_offset = 0; - uint8_t phase4_led_en = 1; /* phase1 led enable*/ - - uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase4_led_en = 0; /* phase1 led enable*/ + uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase5_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase5_tia_res = PS_Gnoise_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase5_led_drv1_cha_sel = LDR3_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase5_led_drv2_cha_sel = 0; - uint8_t phase5_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ + uint8_t phase5_pd_sel = LDR3_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */ uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase5_ldr2_cur = 0; -// uint8_t phase5_of_idac1_cur = 0; -// uint8_t phase5_of_idac2_cur = 0; + uint8_t phase5_ldr2_cur = 0; uint8_t phase5_ad_inr_ctrl = 3; uint8_t phase5_ad_of_idac_ctrl = 0; -// uint8_t phase5_afe_offset = 0; - uint8_t phase5_led_en = 1; /* phase1 led enable*/ - - uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase5_led_en = 0; /* phase1 led enable*/ + uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase6_tia_res = PS_Gnoise_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase6_led_drv1_cha_sel = LDR4_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase6_led_drv2_cha_sel = 0; - uint8_t phase6_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ + uint8_t phase6_pd_sel = LDR4_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */ uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase6_ldr2_cur = 0; -// uint8_t phase6_of_idac1_cur = 0; -// uint8_t phase6_of_idac2_cur = 0; + uint8_t phase6_ldr2_cur = 0; uint8_t phase6_ad_inr_ctrl = 3; uint8_t phase6_ad_of_idac_ctrl = 0; -// uint8_t phase6_afe_offset = 0; - uint8_t phase6_led_en = 1; /* phase1 led enable*/ - - uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase6_led_en = 0; /* phase1 led enable*/ + uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase7_tia_res = PS_Gnoise_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase7_led_drv1_cha_sel = LDR5_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase7_led_drv2_cha_sel = 0; - uint8_t phase7_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ + uint8_t phase7_pd_sel = LDR5_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */ uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase7_ldr2_cur = 0; -// uint8_t phase7_of_idac1_cur = 0; -// uint8_t phase7_of_idac2_cur = 0; + uint8_t phase7_ldr2_cur = 0; uint8_t phase7_ad_inr_ctrl = 3; uint8_t phase7_ad_of_idac_ctrl = 0; -// uint8_t phase7_afe_offset = 0; - uint8_t phase7_led_en = 1; /* phase1 led enable*/ - - uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase7_led_en = 0; /* phase1 led enable*/ + uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase8_led_drv1_cha_sel = 0; //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase8_tia_res = 3; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase8_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase8_led_drv2_cha_sel = 0; - uint8_t phase8_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ + uint8_t phase8_pd_sel = 0; /* 1 = pd1; 2 = pd2; */ uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ uint8_t phase8_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase8_ldr2_cur = 0; -// uint8_t phase8_of_idac1_cur = 0; -// uint8_t phase8_of_idac2_cur = 0; + uint8_t phase8_ldr2_cur = 0; uint8_t phase8_ad_inr_ctrl = 3; uint8_t phase8_ad_of_idac_ctrl = 0; -// uint8_t phase8_afe_offset = 0; - uint8_t phase8_led_en = 1; /* phase1 led enable*/ - - uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase8_led_en = 0; /* phase1 led enable*/ + uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - uint8_t init_wait_delay = 5 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ; + uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ; 4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ; 4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */ - uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/ - + uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/ + uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ - - uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ - - uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ; + + uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ + + uint8_t led_on_time = 3; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ; 4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */ hx3695_delay_ms(10); - + hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6 hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8> hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); - hx3695_write_reg(0X2d, phase7_8_internal); - hx3695_write_reg(0X2e, 0x33);// gpio ctrl + hx3695_write_reg(0X2d, phase7_8_internal); + hx3695_write_reg(0X2e, 0x33);// gpio ctrl hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay)); - hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); + hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); hx3695_write_reg(0X31, (led_on_time<<4| 0x00)); - hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置； - hx3695_write_reg(0X34, 0x00);// 中断特殊配置； - hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置； - hx3695_write_reg(0X38, 0x00); + hx3695_write_reg(0X33, 0x83);// �жϼ��Լ��������ã� + hx3695_write_reg(0X34, 0x00);// �ж��������ã� + hx3695_write_reg(0X36, 0x00);// phase data ready ��־���ã� + hx3695_write_reg(0X38, 0x00); hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); @@ -1114,851 +991,474 @@ void hx3695_factory_ft_single_check_config(void)//灰卡10mm高度测试配置 hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num ); hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num ); - - hx3695_write_reg(0X43, phase1_mux_sel); - hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); - hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase1_als_offset_idac); - hx3695_write_reg(0X48, phase1_led_offset_idac); - + hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num ); + hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num ); + + hx3695_write_reg(0X43, phase1_mux_sel); + hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); + hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase1_als_offset_idac); + hx3695_write_reg(0X48, phase1_led_offset_idac); hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4); -// hx3695_write_reg(0X4e, thred_value); -// hx3695_write_reg(0X4f, thred_value>>5); - + hx3695_write_reg(0X43, phase2_mux_sel); - hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); - hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase2_als_offset_idac); - hx3695_write_reg(0X48, phase2_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); + hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); + hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase2_als_offset_idac); + hx3695_write_reg(0X48, phase2_led_offset_idac); hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4); //phase3 sel hx3695_write_reg(0X43, phase3_mux_sel); - hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); - hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase3_als_offset_idac); - hx3695_write_reg(0X48, phase3_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); + hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); + hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase3_als_offset_idac); + hx3695_write_reg(0X48, phase3_led_offset_idac); hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4); //phase4 sel hx3695_write_reg(0X43, phase4_mux_sel); - hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); - hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase4_als_offset_idac); - hx3695_write_reg(0X48, phase4_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); + hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); + hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase4_als_offset_idac); + hx3695_write_reg(0X48, phase4_led_offset_idac); hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4); - - hx3695_write_reg(0X43, phase5_mux_sel); - hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); - hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase5_pd_sel)); //<<4 | 0x00)); - hx3695_write_reg(0X47, phase5_als_offset_idac); - hx3695_write_reg(0X48, phase5_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); + hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4); + + hx3695_write_reg(0X43, phase5_mux_sel); + hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); + hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase5_als_offset_idac); + hx3695_write_reg(0X48, phase5_led_offset_idac); hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase6_mux_sel); - hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); - hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase6_als_offset_idac); - hx3695_write_reg(0X48, phase6_led_offset_idac); -// hx3695_write_reg(0X48, phase6_led_offset_idac); + hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4); + + + hx3695_write_reg(0X43, phase6_mux_sel); + hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); + hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase6_als_offset_idac); + hx3695_write_reg(0X48, phase6_led_offset_idac); hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4); - hx3695_write_reg(0X43, phase7_mux_sel); - hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); - hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase7_als_offset_idac); - hx3695_write_reg(0X48, phase7_led_offset_idac); -// hx3695_write_reg(0X48, phase7_led_offset_idac); + hx3695_write_reg(0X43, phase7_mux_sel); + hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); + hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase7_als_offset_idac); + hx3695_write_reg(0X48, phase7_led_offset_idac); hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4); - hx3695_write_reg(0X43, phase8_mux_sel); - hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); - hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase8_als_offset_idac); - hx3695_write_reg(0X48, phase8_led_offset_idac); -// hx3695_write_reg(0X48, phas8_led_offset_idac); + hx3695_write_reg(0X43, phase8_mux_sel); + hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); + hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase8_als_offset_idac); + hx3695_write_reg(0X48, phase8_led_offset_idac); hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4); // analog circuit cfg - hx3695_write_reg(0X60, 0x14); // - hx3695_write_reg(0X61, 0xf0); - hx3695_write_reg(0X62, 0x22); - hx3695_write_reg(0X63, 0x15); - - hx3695_write_reg(0X64, 0x08); - hx3695_write_reg(0X65, 0x88); //bug - - hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30 - hx3695_write_reg(0X67, 0x23); - hx3695_write_reg(0X68, 0x46); - hx3695_write_reg(0X69, 0x42); - - hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg - hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable + hx3695_write_reg(0X60, 0x34); // + hx3695_write_reg(0X61, 0xf0); + hx3695_write_reg(0X62, 0x22); + hx3695_write_reg(0X63, 0x15); + + hx3695_write_reg(0X64, 0x08); + hx3695_write_reg(0X65, 0x88); //bug + + hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30 + hx3695_write_reg(0X67, 0x23); + hx3695_write_reg(0X68, 0x46); + hx3695_write_reg(0X69, 0x42); + + hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg + hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable hx3695_write_reg(0X6a, 0X0f); - hx3695_write_reg(0X6b, 0X22); - hx3695_write_reg(0X6c, 0X00); - hx3695_write_reg(0X6d, 0X37); - hx3695_write_reg(0X6e, 0X82); - hx3695_write_reg(0X6f, 0X08); + hx3695_write_reg(0X6b, 0X22); + hx3695_write_reg(0X6c, 0X00); + hx3695_write_reg(0X6d, 0X37); + hx3695_write_reg(0X6e, 0X82); + hx3695_write_reg(0X6f, 0X00); /////////FIFO and adc conversion ready config//////// /////////FIFO and adc conversion ready config//////// -#if defined(PPG_INT_MODE) - hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ - bits<7> fifo enble - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear - hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int -#elif defined(INT_MODE) //FIFO_ALL_MOST_FULL) - hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ - bits<7> fifo enble - hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark - hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear - hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int +#if defined(INT_MODE) //(FIFO_ALL_MOST_FULL) + hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;0011=p4;0100=p5;0101=p6;0110=p7;bits<7> fifo enble + hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark + hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] + hx3695_write_reg(0X33, 0x83); // int width + hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int #else - hx3695_write_reg(0X1b, 0x92); // bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3; - // 0011=p4;0100=p5;0101=p6;0110=p7; - // bits<7> fifo enble - hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int - + hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;0011=p4;0100=p5;0101=p6;0110=p7;bits<7> fifo enble + hx3695_write_reg(0X36, 0x00); //intrupt + + hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int + #endif - hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); - hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); - hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) ); - hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); + hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); + hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); + hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) ); + hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); // hx3695_write_reg(0X5c, 0x02);//soft reset - hx3695_delay_ms(5); - hx3695_write_reg(0X5c, 0x00);//release + hx3695_delay_ms(5); + hx3695_write_reg(0X5c, 0x00);//release return ; } - -void hx3695_factory_ft_leak_light_test_config(void)//漏光测试配置 +void hx3695_LDR0_led_control(uint8_t phase2_led_en,uint8_t phase2_ldr1_cur) { - uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/ - uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */ - - - uint8_t adc_rst_post_num= 0; /* 00=16,01=32,10=64,11=128*/ - uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ - uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/ - uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/ - uint8_t phase7_8_internal = 0; //0x18; /* phase7 and phase8 prf internal cfg */ - -// uint16_t thred_value = 32500; - - uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase5_enable = 0; /*phase5_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase6_enable = 0; /*phase6_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase7_enable = 0; /*phase7_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase8_enable = 0; /*phase8_enable , 1 mean enable ; 0 mean disable */ - - uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - - uint8_t phase1_mux_sel = 0; /* sel phase1*/ - uint8_t phase2_mux_sel = 1; /* sel phase2*/ - uint8_t phase3_mux_sel = 2; /* sel phase3*/ - uint8_t phase4_mux_sel = 3; /* sel phase4*/ - uint8_t phase5_mux_sel = 4; /* sel phase5*/ - uint8_t phase6_mux_sel = 5; /* sel phase6*/ - uint8_t phase7_mux_sel = 6; /* sel phase7*/ - uint8_t phase8_mux_sel = 7; /* sel phase8*/ - - - uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase1_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */ - uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */ - uint8_t phase1_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase1_ldr2_cur = 0; -// uint8_t phase1_of_idac1_cur = 0; -// uint8_t phase1_of_idac2_cur = 0; - uint8_t phase1_ad_inr_ctrl = 3; - uint8_t phase1_ad_of_idac_ctrl = 0; -// uint8_t afe_offset = 0; - uint8_t phase1_led_en = 1; /* phase1 led enable*/ - - uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - - - uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase2_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase2_led_drv1_cha_sel = GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase2_mux_sel = 1; /* sel phase2*/ + uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ + uint8_t phase2_tia_res = PS_SINGLE_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase2_led_drv1_cha_sel = LDR0_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase2_led_drv2_cha_sel = 0x00; - uint8_t phase2_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase2_pd_sel = LDR0_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase2_ldr1_cur = 64; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase2_ldr2_cur = 0; -// uint8_t phase2_of_idac1_cur = 0; -// uint8_t phase2_of_idac2_cur = 0; + uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ +// uint8_t phase2_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase2_ldr2_cur = 0; uint8_t phase2_ad_inr_ctrl = 3; uint8_t phase2_ad_of_idac_ctrl = 0; -// uint8_t phase2_afe_offset = 0; - uint8_t phase2_led_en = 1; /* phase1 led enable*/ - - uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ +// uint8_t phase2_led_en = 0; /* phase1 led enable*/ + uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ + + + hx3695_write_reg(0X43, phase2_mux_sel); + hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); + hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase2_als_offset_idac); + hx3695_write_reg(0X48, phase2_led_offset_idac); + hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); + hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X30, phase2_led_en<<1); + hx3695_write_reg(0X72, phase2_led_en<<1); +} - +void hx3695_LDR1_led_control(uint8_t phase3_led_en,uint8_t phase3_ldr1_cur) +{ + uint8_t phase3_mux_sel = 2; /* sel phase3*/ uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase3_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase3_led_drv1_cha_sel = RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase3_tia_res = PS_SINGLE_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase3_led_drv1_cha_sel = LDR1_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase3_led_drv2_cha_sel = 0; - uint8_t phase3_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase3_pd_sel = LDR1_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase3_ldr1_cur = 64; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase3_ldr2_cur = 0; -// uint8_t phase3_of_idac1_cur = 0; -// uint8_t phase3_of_idac2_cur = 0; + uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ +// uint8_t phase3_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase3_ldr2_cur = 0; uint8_t phase3_ad_inr_ctrl = 3; - uint8_t phase3_ad_of_idac_ctrl = 0; -// uint8_t phase3_afe_offset = 0; - uint8_t phase3_led_en = 1; /* phase1 led enable*/ - - uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase3_ad_of_idac_ctrl = 0; + uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ + hx3695_write_reg(0X43, phase3_mux_sel); + hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); + hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase3_als_offset_idac); + hx3695_write_reg(0X48, phase3_led_offset_idac); + hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); + hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X30, phase3_led_en<<2); + hx3695_write_reg(0X72, phase3_led_en<<2); +} - +void hx3695_LDR2_led_control(uint8_t phase4_led_en ,uint8_t phase4_ldr1_cur) +{ + uint8_t phase4_mux_sel = 3; /* sel phase4*/ uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase4_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase4_led_drv1_cha_sel = IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase4_tia_res = PS_SINGLE_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase4_led_drv1_cha_sel = LDR2_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase4_led_drv2_cha_sel = 0; - uint8_t phase4_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase4_pd_sel = LDR2_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase4_ldr1_cur = 64; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase4_ldr2_cur = 0; -// uint8_t phase4_of_idac1_cur = 0; -// uint8_t phase4_of_idac2_cur = 0; + uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ +// uint8_t phase4_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase4_ldr2_cur = 0; uint8_t phase4_ad_inr_ctrl = 3; uint8_t phase4_ad_of_idac_ctrl = 0; -// uint8_t phase4_afe_offset = 0; - uint8_t phase4_led_en = 1; /* phase1 led enable*/ - - uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ +// uint8_t phase4_led_en = 0; /* phase1 led enable*/ + uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ + hx3695_write_reg(0X43, phase4_mux_sel); + hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); + hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase4_als_offset_idac); + hx3695_write_reg(0X48, phase4_led_offset_idac); + hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); + hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X30, phase4_led_en<<3); + hx3695_write_reg(0X72, phase4_led_en<<3); +} +void hx3695_LDR3_led_control(uint8_t phase5_led_en,uint8_t phase5_ldr1_cur) +{ + uint8_t phase5_mux_sel = 4; /* sel phase5*/ uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase5_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase5_tia_res = PS_SINGLE_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase5_led_drv1_cha_sel = LDR3_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase5_led_drv2_cha_sel = 0; - uint8_t phase5_pd_sel = 4; /* 1 = pd1; 2 = pd2; */ + uint8_t phase5_pd_sel = LDR3_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */ uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase5_ldr2_cur = 0; -// uint8_t phase5_of_idac1_cur = 0; -// uint8_t phase5_of_idac2_cur = 0; + uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ +// uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase5_ldr2_cur = 0; uint8_t phase5_ad_inr_ctrl = 3; uint8_t phase5_ad_of_idac_ctrl = 0; -// uint8_t phase5_afe_offset = 0; - uint8_t phase5_led_en = 0; /* phase1 led enable*/ - - uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + + uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - + + hx3695_write_reg(0X43, phase5_mux_sel); + hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); + hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase5_als_offset_idac); + hx3695_write_reg(0X48, phase5_led_offset_idac); + hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); + hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X30, phase5_led_en<<4); + hx3695_write_reg(0X72, phase5_led_en<<4); +} +void hx3695_LDR4_led_control(uint8_t phase6_led_en,uint8_t phase6_ldr1_cur) +{ + uint8_t phase6_mux_sel = 5; /* sel phase6*/ uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase6_tia_res = PS_SINGLE_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase6_led_drv1_cha_sel = LDR4_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase6_led_drv2_cha_sel = 0; - uint8_t phase6_pd_sel = 4; /* 1 = pd1; 2 = pd2; */ + uint8_t phase6_pd_sel = LDR4_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */ uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase6_ldr2_cur = 0; -// uint8_t phase6_of_idac1_cur = 0; -// uint8_t phase6_of_idac2_cur = 0; + uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ +// uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase6_ldr2_cur = 0; uint8_t phase6_ad_inr_ctrl = 3; - uint8_t phase6_ad_of_idac_ctrl = 0; -// uint8_t phase6_afe_offset = 0; - uint8_t phase6_led_en = 0; /* phase1 led enable*/ - - uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase6_ad_of_idac_ctrl = 0; + uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ + + hx3695_write_reg(0X43, phase6_mux_sel); + hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); + hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase6_als_offset_idac); + hx3695_write_reg(0X48, phase6_led_offset_idac); + hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); + hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X30, phase6_led_en<<5); + hx3695_write_reg(0X72, phase6_led_en<<5); +} - uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ +void hx3695_LDR5_led_control(uint8_t phase7_led_en,uint8_t phase7_ldr1_cur) +{ + uint8_t phase7_mux_sel = 6; /* sel phase7*/ + uint8_t phase7_tia_res = PS_SINGLE_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase7_led_drv1_cha_sel = LDR5_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase7_led_drv2_cha_sel = 0; - uint8_t phase7_pd_sel = 0x00; /* 1 = pd1; 2 = pd2; */ + uint8_t phase7_pd_sel = LDR5_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */ uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase7_ldr2_cur = 0; -// uint8_t phase7_of_idac1_cur = 0; -// uint8_t phase7_of_idac2_cur = 0; + uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ +// uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase7_ldr2_cur = 0; uint8_t phase7_ad_inr_ctrl = 3; uint8_t phase7_ad_of_idac_ctrl = 0; -// uint8_t phase7_afe_offset = 0; - uint8_t phase7_led_en = 0; /* phase1 led enable*/ - - uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ +// uint8_t phase7_led_en = 0; /* phase7 led enable*/ + uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ + + hx3695_write_reg(0X43, phase7_mux_sel); + hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); + hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase7_als_offset_idac); + hx3695_write_reg(0X48, phase7_led_offset_idac); + hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); + hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X30, phase7_led_en<<6); + hx3695_write_reg(0X72, phase7_led_en<<6); +} + +void hx3695_factory_ft_single_check_config(void) +{ + uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/ + uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */ - uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase8_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase8_led_drv2_cha_sel = 0; - uint8_t phase8_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ - uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase8_ldr1_cur = 50; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase8_ldr2_cur = 0; -// uint8_t phase8_of_idac1_cur = 0; -// uint8_t phase8_of_idac2_cur = 0; - uint8_t phase8_ad_inr_ctrl = 3; - uint8_t phase8_ad_of_idac_ctrl = 0; -// uint8_t phase8_afe_offset = 0; - uint8_t phase8_led_en = 0; /* phase1 led enable*/ - - uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ; - 4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ - - uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ; - 4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */ - - uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/ - - uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ - - uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ - - uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ; - 4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */ - - hx3695_delay_ms(10); - - hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6 - hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8> - hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> - - hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); - hx3695_write_reg(0X2d, phase7_8_internal); - hx3695_write_reg(0X2e, 0x33);// gpio ctrl - hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay)); - hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); - hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); - - - hx3695_write_reg(0X31, (led_on_time<<4| 0x00)); - hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置； - hx3695_write_reg(0X34, 0x00);// 中断特殊配置； - hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置； - hx3695_write_reg(0X38, 0x00); - - hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); - hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); - hx3695_write_reg(0X3c, (phase5_inner_avg | (phase6_inner_avg<<4))); - hx3695_write_reg(0X3d, (phase7_inner_avg | (phase8_inner_avg<<4))); - hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); - hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num ); - - hx3695_write_reg(0X43, phase1_mux_sel); - hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); - hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase1_als_offset_idac); - hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase2_mux_sel); - hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); - hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase2_als_offset_idac); - hx3695_write_reg(0X48, phase2_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4); - -//phase3 sel - - hx3695_write_reg(0X43, phase3_mux_sel); - hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); - hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase3_als_offset_idac); - hx3695_write_reg(0X48, phase3_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4); - -//phase4 sel - - hx3695_write_reg(0X43, phase4_mux_sel); - hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); - hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase4_als_offset_idac); - hx3695_write_reg(0X48, phase4_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4); - - hx3695_write_reg(0X43, phase5_mux_sel); - hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); - hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase5_als_offset_idac); - hx3695_write_reg(0X48, phase5_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase6_mux_sel); - hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); - hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase6_als_offset_idac); - hx3695_write_reg(0X48, phase6_led_offset_idac); -// hx3695_write_reg(0X48, phase6_led_offset_idac); - hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase7_mux_sel); - hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); - hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase7_als_offset_idac); - hx3695_write_reg(0X48, phase7_led_offset_idac); -// hx3695_write_reg(0X48, phase7_led_offset_idac); - hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase8_mux_sel); - hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); - hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase8_als_offset_idac); - hx3695_write_reg(0X48, phase8_led_offset_idac); -// hx3695_write_reg(0X48, phas8_led_offset_idac); - hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4); - - -// analog circuit cfg - hx3695_write_reg(0X60, 0x14); // - hx3695_write_reg(0X61, 0xf0); - hx3695_write_reg(0X62, 0x22); - hx3695_write_reg(0X63, 0x15); - - hx3695_write_reg(0X64, 0x08); - hx3695_write_reg(0X65, 0x88); //bug - - hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30 - hx3695_write_reg(0X67, 0x23); - hx3695_write_reg(0X68, 0x46); - hx3695_write_reg(0X69, 0x42); - - hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg - hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable - - hx3695_write_reg(0X6a, 0X0f); - hx3695_write_reg(0X6b, 0X22); - hx3695_write_reg(0X6c, 0X00); - hx3695_write_reg(0X6d, 0X37); - hx3695_write_reg(0X6e, 0X82); - hx3695_write_reg(0X6f, 0X08); -/////////FIFO and adc conversion ready config//////// -/////////FIFO and adc conversion ready config//////// -#if defined(PPG_INT_MODE) - hx3695_write_reg(0X1b, 0x00);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ - bits<7> fifo enble - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear - hx3695_write_reg(0X38, 0x08); // int sel,00=close almost full int,04=enable almost full int -#elif defined(INT_MODE) //(FIFO_ALL_MOST_FULL) - hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ - bits<7> fifo enble - hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark - hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int - -#else - hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3; - // 0011=p4;0100=p5;0101=p6;0110=p7; - // bits<7> fifo enble - hx3695_write_reg(0X36, 0x00); //intrupt - - hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int - -#endif - - - hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); - hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); - hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) ); - hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); - -// hx3695_write_reg(0X5c, 0x02);//soft reset - hx3695_delay_ms(5); - hx3695_write_reg(0X5c, 0x00);//release - - return ; -} - -void hx3695_factory_led_off_config(void) -{ - uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/ - uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */ - - uint8_t adc_rst_post_num=0; /* 00=16,01=32,10=64,11=128*/ - uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ + uint16_t fifo_watermark= 250 ; + uint8_t adc_rst_post_num= 0; /* 00=16,01=32,10=64,11=128*/ + uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/ uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/ - uint8_t phase7_8_internal = 0; /* phase7 and phase8 prf internal cfg */ - + uint8_t phase7_8_internal = 0; //0x18; /* phase7 and phase8 prf internal cfg */ + uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase5_enable = 0; /*phase5_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase6_enable = 0; /*phase6_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase7_enable = 0; /*phase7_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase8_enable = 0; /*phase8_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase5_enable = 1; /*phase5_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase6_enable = 1; /*phase6_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase7_enable = 1; /*phase7_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase1_mux_sel = 0; /* sel phase1*/ - uint8_t phase2_mux_sel = 1; /* sel phase2*/ - uint8_t phase3_mux_sel = 2; /* sel phase3*/ - uint8_t phase4_mux_sel = 3; /* sel phase4*/ - uint8_t phase5_mux_sel = 4; /* sel phase5*/ - uint8_t phase6_mux_sel = 5; /* sel phase6*/ - uint8_t phase7_mux_sel = 6; /* sel phase7*/ - uint8_t phase8_mux_sel = 7; /* sel phase8*/ + uint8_t phase1_mux_sel = 0; /* sel phase1*/ + uint8_t phase8_mux_sel = 7; /* sel phase8*/ - uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase1_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ + uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ + uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ + uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ + uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ + uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ + uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ + uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ + + uint8_t phase1_tia_res = PS_SINGLE_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */ uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */ - uint8_t phase1_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase1_pd_sel = ALS_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase1_ldr2_cur = 0; -// uint8_t phase1_of_idac1_cur = 0; -// uint8_t phase1_of_idac2_cur = 0; + uint8_t phase1_ldr2_cur = 0; uint8_t phase1_ad_inr_ctrl = 3; uint8_t phase1_ad_of_idac_ctrl = 0; -// uint8_t afe_offset = 0; - uint8_t phase1_led_en = 1; /* phase1 led enable*/ - - uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase1_led_en = 0; /* phase1 led enable*/ + uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - - - uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase2_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase2_led_drv1_cha_sel = GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase2_led_drv2_cha_sel = 0; - uint8_t phase2_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase2_ldr1_cur = 15; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase2_ldr2_cur = 0; -// uint8_t phase2_of_idac1_cur = 0; -// uint8_t phase2_of_idac2_cur = 0; - uint8_t phase2_ad_inr_ctrl = 3; - uint8_t phase2_ad_of_idac_ctrl = 0; -// uint8_t phase2_afe_offset = 0; - uint8_t phase2_led_en = 1; /* phase1 led enable*/ - - uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - - uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase3_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase3_led_drv1_cha_sel = RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase3_led_drv2_cha_sel = 0; - uint8_t phase3_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase3_ldr1_cur = 15; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase3_ldr2_cur = 0; -// uint8_t phase3_of_idac1_cur = 0; -// uint8_t phase3_of_idac2_cur = 0; - uint8_t phase3_ad_inr_ctrl = 3; - uint8_t phase3_ad_of_idac_ctrl = 0; -// uint8_t phase3_afe_offset = 0; - uint8_t phase3_led_en = 1; /* phase1 led enable*/ - - uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - - uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase4_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase4_led_drv1_cha_sel = IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase4_led_drv2_cha_sel = 0; - uint8_t phase4_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase4_ldr1_cur = 15; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase4_ldr2_cur = 0; -// uint8_t phase4_of_idac1_cur = 0; -// uint8_t phase4_of_idac2_cur = 0; - uint8_t phase4_ad_inr_ctrl = 3; - uint8_t phase4_ad_of_idac_ctrl = 0; -// uint8_t phase4_afe_offset = 0; - uint8_t phase4_led_en = 1; /* phase1 led enable*/ - - uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase5_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase5_led_drv2_cha_sel = 0; - uint8_t phase5_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ - uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase5_ldr2_cur = 0; -// uint8_t phase5_of_idac1_cur = 0; -// uint8_t phase5_of_idac2_cur = 0; - uint8_t phase5_ad_inr_ctrl = 3; - uint8_t phase5_ad_of_idac_ctrl = 0; -// uint8_t phase5_afe_offset = 0; - uint8_t phase5_led_en = 1; /* phase1 led enable*/ - - uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase6_led_drv2_cha_sel = 0; - uint8_t phase6_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ - uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase6_ldr2_cur = 0; -// uint8_t phase6_of_idac1_cur = 0; -// uint8_t phase6_of_idac2_cur = 0; - uint8_t phase6_ad_inr_ctrl = 3; - uint8_t phase6_ad_of_idac_ctrl = 0; -// uint8_t phase6_afe_offset = 0; - uint8_t phase6_led_en = 1; /* phase1 led enable*/ - - uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase7_led_drv2_cha_sel = 0; - uint8_t phase7_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ - uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase7_ldr2_cur = 0; -// uint8_t phase7_of_idac1_cur = 0; -// uint8_t phase7_of_idac2_cur = 0; - uint8_t phase7_ad_inr_ctrl = 3; - uint8_t phase7_ad_of_idac_ctrl = 0; -// uint8_t phase7_afe_offset = 0; - uint8_t phase7_led_en = 1; /* phase1 led enable*/ - - uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ - uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - - uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase8_led_drv1_cha_sel = 0; //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + + + uint8_t phase8_tia_res = 3; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase8_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase8_led_drv2_cha_sel = 0; - uint8_t phase8_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ + uint8_t phase8_pd_sel = 0; /* 1 = pd1; 2 = pd2; */ uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase8_ldr1_cur = 20; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase8_ldr2_cur = 0; -// uint8_t phase8_of_idac1_cur = 0; -// uint8_t phase8_of_idac2_cur = 0; + uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase8_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase8_ldr2_cur = 0; uint8_t phase8_ad_inr_ctrl = 3; uint8_t phase8_ad_of_idac_ctrl = 0; -// uint8_t phase8_afe_offset = 0; - uint8_t phase8_led_en = 1; /* phase1 led enable*/ - - uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase8_led_en = 0; /* phase1 led enable*/ + uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - uint8_t init_wait_delay = 5 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ; + uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ; 4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ; 4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */ - uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/ - + uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/ + uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ - - uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ - - uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ; + + uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ + + uint8_t led_on_time = 3; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ; 4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */ hx3695_delay_ms(10); - + hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6 hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8> hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); - hx3695_write_reg(0X2d, phase7_8_internal); - hx3695_write_reg(0X2e, 0x33);// gpio ctrl + hx3695_write_reg(0X2d, phase7_8_internal); + hx3695_write_reg(0X2e, 0x33);// gpio ctrl hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay)); - hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); - hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); - + + hx3695_write_reg(0X30, (phase8_led_en<<7 | phase1_led_en)); + hx3695_write_reg(0X72, (phase8_led_en<<7 | phase1_led_en)); + hx3695_write_reg(0X2e, 0x33);// gpio ctrl hx3695_write_reg(0X31, (led_on_time<<4| 0x00)); - hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置； - hx3695_write_reg(0X34, 0x00);// 中断特殊配置； - hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置； - hx3695_write_reg(0X38, 0x00); + hx3695_write_reg(0X33, 0x83);// �жϼ��Լ��������ã� + hx3695_write_reg(0X34, 0x00);// �ж��������ã� + hx3695_write_reg(0X36, 0x00);// phase data ready ��־���ã� + hx3695_write_reg(0X38, 0x00); hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); @@ -1967,424 +1467,292 @@ void hx3695_factory_led_off_config(void) hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num ); hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num ); - - hx3695_write_reg(0X43, phase1_mux_sel); - hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); - hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase1_als_offset_idac); - hx3695_write_reg(0X48, phase1_led_offset_idac); - + hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num ); + hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num ); + + hx3695_write_reg(0X43, phase1_mux_sel); + hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); + hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase1_als_offset_idac); + hx3695_write_reg(0X48, phase1_led_offset_idac); hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4); - -// hx3695_write_reg(0X4e, thred_value); -// hx3695_write_reg(0X4f, thred_value>>5); - - hx3695_write_reg(0X43, phase2_mux_sel); - hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); - hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase2_als_offset_idac); - hx3695_write_reg(0X48, phase2_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4); - -//phase3 sel - - hx3695_write_reg(0X43, phase3_mux_sel); - hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); - hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase3_als_offset_idac); - hx3695_write_reg(0X48, phase3_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4); - -//phase4 sel - - hx3695_write_reg(0X43, phase4_mux_sel); - hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); - hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase4_als_offset_idac); - hx3695_write_reg(0X48, phase4_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4); - - hx3695_write_reg(0X43, phase5_mux_sel); - hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); - hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase5_pd_sel)); //<<4 | 0x00)); - hx3695_write_reg(0X47, phase5_als_offset_idac); - hx3695_write_reg(0X48, phase5_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); - hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase6_mux_sel); - hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); - hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase6_als_offset_idac); - hx3695_write_reg(0X48, phase6_led_offset_idac); -// hx3695_write_reg(0X48, phase6_led_offset_idac); - hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase7_mux_sel); - hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); - hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase7_als_offset_idac); - hx3695_write_reg(0X48, phase7_led_offset_idac); -// hx3695_write_reg(0X48, phase7_led_offset_idac); - hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase8_mux_sel); - hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); - hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase8_als_offset_idac); - hx3695_write_reg(0X48, phase8_led_offset_idac); -// hx3695_write_reg(0X48, phas8_led_offset_idac); + hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4); + + hx3695_write_reg(0X43, phase8_mux_sel); + hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); + hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase8_als_offset_idac); + hx3695_write_reg(0X48, phase8_led_offset_idac); hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4); - // analog circuit cfg - hx3695_write_reg(0X60, 0x14); // - hx3695_write_reg(0X61, 0xf0); - hx3695_write_reg(0X62, 0x22); - hx3695_write_reg(0X63, 0x15); - - hx3695_write_reg(0X64, 0x08); - hx3695_write_reg(0X65, 0x88); //bug - - hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30 - hx3695_write_reg(0X67, 0x23); - hx3695_write_reg(0X68, 0x46); - hx3695_write_reg(0X69, 0x42); - - hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg - hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable + hx3695_write_reg(0X60, 0x34); // + hx3695_write_reg(0X61, 0xf0); + hx3695_write_reg(0X62, 0x22); + hx3695_write_reg(0X63, 0x15); + + hx3695_write_reg(0X64, 0x08); + hx3695_write_reg(0X65, 0x88); //bug + + hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30 + hx3695_write_reg(0X67, 0x23); + hx3695_write_reg(0X68, 0x46); + hx3695_write_reg(0X69, 0x42); + + hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg + hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable hx3695_write_reg(0X6a, 0X0f); - hx3695_write_reg(0X6b, 0X22); - hx3695_write_reg(0X6c, 0X00); - hx3695_write_reg(0X6d, 0X37); - hx3695_write_reg(0X6e, 0X82); - hx3695_write_reg(0X6f, 0X08); + hx3695_write_reg(0X6b, 0X22); + hx3695_write_reg(0X6c, 0X00); + hx3695_write_reg(0X6d, 0X37); + hx3695_write_reg(0X6e, 0X82); + hx3695_write_reg(0X6f, 0X00); /////////FIFO and adc conversion ready config//////// /////////FIFO and adc conversion ready config//////// -#if defined(PPG_INT_MODE) - hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ - bits<7> fifo enble - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear - hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int -#elif defined(INT_MODE) //FIFO_ALL_MOST_FULL) - hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ - 0011=p4;0100=p5;0101=p6;0110=p7;\ - bits<7> fifo enble - hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark - hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear - hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int +#if defined(INT_MODE) //(FIFO_ALL_MOST_FULL) + hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;0011=p4;0100=p5;0101=p6;0110=p7;bits<7> fifo enble + hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark + hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] + hx3695_write_reg(0X33, 0x83); // int width + hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int #else - hx3695_write_reg(0X1b, 0x92); // bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3; - // 0011=p4;0100=p5;0101=p6;0110=p7; - // bits<7> fifo enble - hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int - + hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;0011=p4;0100=p5;0101=p6;0110=p7;\bits<7> fifo enble + hx3695_write_reg(0X36, 0x00); //intrupt + hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int + #endif - hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); - hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); - hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) ); - hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); + hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); + hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); + hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) ); + hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); // hx3695_write_reg(0X5c, 0x02);//soft reset - hx3695_delay_ms(5); - hx3695_write_reg(0X5c, 0x00);//release -// read_fifo_first_flg = 1; + hx3695_delay_ms(5); + hx3695_write_reg(0X5c, 0x00);//release + return ; } -void hx3695_factory_ft_int_test_config(void)//中断测试配置 +void hx3695_factory_ft_aging_check_config(void) { - uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/ + uint16_t sample_rate = 25; /*config the data rate of chip alps2_fm ,uint is Hz*/ uint32_t prf_clk_num = 32000/sample_rate; /*period in clk num, num = Fclk/fs */ - uint8_t adc_rst_post_num=0; /* 00=16,01=32,10=64,11=128*/ - uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ + uint16_t fifo_watermark= 250 ; + uint8_t adc_rst_post_num= 0; /* 00=16,01=32,10=64,11=128*/ + uint8_t samp_delay_leden_num = 0; /* 00=8,01=16,10=32,11=64*/ uint8_t samp_copy_avg = 0; /* 0=1, 1=2, 2=4 ,3=8, 4=16*/ uint8_t data_avg_num = 0; /* 0 = 1 ; 1 = 2; 2 =4 ; 3 =8 ; 4 =16 ;*/ - uint8_t phase7_8_internal = 0; /* phase7 and phase8 prf internal cfg */ - + uint8_t phase7_8_internal = 0; //0x18; /* phase7 and phase8 prf internal cfg */ + + uint8_t phase1_enable = 1; /*phase1_enable , 1 mean enable ; 0 mean disable */ uint8_t phase2_enable = 1; /*phase2_enable , 1 mean enable ; 0 mean disable */ uint8_t phase3_enable = 1; /*phase3_enable , 1 mean enable ; 0 mean disable */ uint8_t phase4_enable = 1; /*phase4_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase5_enable = 0; /*phase5_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase6_enable = 0; /*phase6_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase7_enable = 0; /*phase7_enable , 1 mean enable ; 0 mean disable */ - uint8_t phase8_enable = 0; /*phase8_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase5_enable = 1; /*phase5_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase6_enable = 1; /*phase6_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase7_enable = 1; /*phase7_enable , 1 mean enable ; 0 mean disable */ + uint8_t phase8_enable = 1; /*phase8_enable , 1 mean enable ; 0 mean disable */ uint8_t phase1_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ uint8_t phase2_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ uint8_t phase3_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ uint8_t phase4_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase5_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase6_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase7_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ + uint8_t phase8_adc_osr = 3; /* 0 = 128 ; 1 = 256 ; 2 = 512 ; 3 = 1024 ; 4 = 2048*/ - uint8_t phase1_mux_sel = 0; /* sel phase1*/ - uint8_t phase2_mux_sel = 1; /* sel phase2*/ - uint8_t phase3_mux_sel = 2; /* sel phase3*/ - uint8_t phase4_mux_sel = 3; /* sel phase4*/ - uint8_t phase5_mux_sel = 4; /* sel phase5*/ - uint8_t phase6_mux_sel = 5; /* sel phase6*/ - uint8_t phase7_mux_sel = 6; /* sel phase7*/ - uint8_t phase8_mux_sel = 7; /* sel phase8*/ + uint8_t phase1_mux_sel = 0; /* sel phase1*/ + uint8_t phase2_mux_sel = 1; /* sel phase2*/ + uint8_t phase3_mux_sel = 2; /* sel phase3*/ + uint8_t phase4_mux_sel = 3; /* sel phase4*/ + uint8_t phase5_mux_sel = 4; /* sel phase5*/ + uint8_t phase6_mux_sel = 5; /* sel phase6*/ + uint8_t phase7_mux_sel = 6; /* sel phase7*/ + uint8_t phase8_mux_sel = 7; /* sel phase8*/ - uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase1_tia_res = 3; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase1_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ + uint8_t phase1_tia_res = PS_AGING_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase1_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ uint8_t phase1_led_drv1_cha_sel = 0; /* 1 = ldr1 NG; 2 = ldr2 GR; 4 = ldr3 IR; 8 = ldr4 RED; */ uint8_t phase1_led_drv2_cha_sel = 0; /*ldr5:0x20 ldr6: 0x40 red ldr8 0x80 ir */ - uint8_t phase1_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ - uint8_t phase1_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase1_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase1_pd_sel = ALS_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase1_als_offset_idac = 1; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ + uint8_t phase1_led_offset_idac = 1; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ uint8_t phase1_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase1_ldr2_cur = 0; -// uint8_t phase1_of_idac1_cur = 0; -// uint8_t phase1_of_idac2_cur = 0; + uint8_t phase1_ldr2_cur = 0; uint8_t phase1_ad_inr_ctrl = 3; uint8_t phase1_ad_of_idac_ctrl = 0; -// uint8_t afe_offset = 0; - uint8_t phase1_led_en = 1; /* phase1 led enable*/ - - uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase1_led_en = 1; /* phase1 led enable*/ + uint8_t phase1_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase1_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase2_tia_res = 3; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase2_led_drv1_cha_sel = GREEN_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase2_led_drv2_cha_sel = 0; - uint8_t phase2_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase2_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ + uint8_t phase2_tia_res = PS_AGING_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase2_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase2_led_drv1_cha_sel = LDR0_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase2_led_drv2_cha_sel = LDR0_FT_SEL; + uint8_t phase2_pd_sel = LDR0_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase2_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase2_ldr1_cur = 15; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase2_ldr2_cur = 0; -// uint8_t phase2_of_idac1_cur = 0; -// uint8_t phase2_of_idac2_cur = 0; + uint8_t phase2_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase2_ldr1_cur = DRV1_AGING_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase2_ldr2_cur = DRV2_AGING_CUR; uint8_t phase2_ad_inr_ctrl = 3; uint8_t phase2_ad_of_idac_ctrl = 0; -// uint8_t phase2_afe_offset = 0; - uint8_t phase2_led_en = 1; /* phase1 led enable*/ - - uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase2_led_en = 1; /* phase1 led enable*/ + uint8_t phase2_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase2_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase3_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase3_tia_res = 3; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase3_led_drv1_cha_sel = RED_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase3_led_drv2_cha_sel = 0; - uint8_t phase3_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase3_tia_res = PS_AGING_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase3_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase3_led_drv1_cha_sel = LDR1_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase3_led_drv2_cha_sel = LDR1_FT_SEL; + uint8_t phase3_pd_sel = LDR1_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase3_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase3_ldr1_cur = 15; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase3_ldr2_cur = 0; -// uint8_t phase3_of_idac1_cur = 0; -// uint8_t phase3_of_idac2_cur = 0; + uint8_t phase3_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase3_ldr1_cur = DRV1_AGING_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase3_ldr2_cur = DRV2_AGING_CUR; uint8_t phase3_ad_inr_ctrl = 3; uint8_t phase3_ad_of_idac_ctrl = 0; -// uint8_t phase3_afe_offset = 0; - uint8_t phase3_led_en = 1; /* phase1 led enable*/ - - uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase3_led_en = 1; /* phase1 led enable*/ + uint8_t phase3_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase3_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase4_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase4_tia_res = 3; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase4_led_drv1_cha_sel = IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase4_led_drv2_cha_sel = 0; - uint8_t phase4_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; 4 = pd3*/ + uint8_t phase4_tia_res = PS_AGING_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase4_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase4_led_drv1_cha_sel = LDR2_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase4_led_drv2_cha_sel = LDR2_FT_SEL; + uint8_t phase4_pd_sel = LDR2_PD_FT_SEL; /* 1 = pd1; 2 = pd2; 4 = pd3*/ uint8_t phase4_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase4_ldr1_cur = 15; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase4_ldr2_cur = 0; -// uint8_t phase4_of_idac1_cur = 0; -// uint8_t phase4_of_idac2_cur = 0; + uint8_t phase4_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase4_ldr1_cur = DRV1_AGING_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase4_ldr2_cur = DRV2_AGING_CUR; uint8_t phase4_ad_inr_ctrl = 3; uint8_t phase4_ad_of_idac_ctrl = 0; -// uint8_t phase4_afe_offset = 0; - uint8_t phase4_led_en = 1; /* phase1 led enable*/ - - uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase4_led_en = 1; /* phase1 led enable*/ + uint8_t phase4_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase4_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase5_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase5_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase5_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase5_led_drv2_cha_sel = 0; - uint8_t phase5_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ + uint8_t phase5_tia_res = PS_AGING_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase5_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase5_led_drv1_cha_sel = LDR3_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase5_led_drv2_cha_sel = LDR3_FT_SEL; + uint8_t phase5_pd_sel = LDR3_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */ uint8_t phase5_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase5_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase5_ldr2_cur = 0; -// uint8_t phase5_of_idac1_cur = 0; -// uint8_t phase5_of_idac2_cur = 0; + uint8_t phase5_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase5_ldr1_cur = DRV1_AGING_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase5_ldr2_cur = DRV2_AGING_CUR; uint8_t phase5_ad_inr_ctrl = 3; uint8_t phase5_ad_of_idac_ctrl = 0; -// uint8_t phase5_afe_offset = 0; - uint8_t phase5_led_en = 1; /* phase1 led enable*/ - - uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase5_led_en = 1; /* phase1 led enable*/ + uint8_t phase5_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase5_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase6_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase6_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase6_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase6_led_drv2_cha_sel = 0; - uint8_t phase6_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ + uint8_t phase6_tia_res = PS_AGING_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase6_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase6_led_drv1_cha_sel = LDR4_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase6_led_drv2_cha_sel = LDR4_FT_SEL; + uint8_t phase6_pd_sel = LDR4_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */ uint8_t phase6_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase6_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase6_ldr2_cur = 0; -// uint8_t phase6_of_idac1_cur = 0; -// uint8_t phase6_of_idac2_cur = 0; + uint8_t phase6_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase6_ldr1_cur = DRV1_AGING_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase6_ldr2_cur = DRV2_AGING_CUR; uint8_t phase6_ad_inr_ctrl = 3; uint8_t phase6_ad_of_idac_ctrl = 0; -// uint8_t phase6_afe_offset = 0; - uint8_t phase6_led_en = 1; /* phase1 led enable*/ - - uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase6_led_en = 1; /* phase1 led enable*/ + uint8_t phase6_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase6_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase7_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase7_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase7_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ - uint8_t phase7_led_drv2_cha_sel = 0; - uint8_t phase7_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ + uint8_t phase7_tia_res = PS_AGING_TIA; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase7_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase7_led_drv1_cha_sel = LDR5_FT_SEL; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase7_led_drv2_cha_sel = LDR5_FT_SEL; + uint8_t phase7_pd_sel = LDR5_PD_FT_SEL; /* 1 = pd1; 2 = pd2; */ uint8_t phase7_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ - uint8_t phase7_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase7_ldr2_cur = 0; -// uint8_t phase7_of_idac1_cur = 0; -// uint8_t phase7_of_idac2_cur = 0; + uint8_t phase7_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase7_ldr1_cur = DRV1_AGING_CUR; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ + uint8_t phase7_ldr2_cur = DRV2_AGING_CUR; uint8_t phase7_ad_inr_ctrl = 3; uint8_t phase7_ad_of_idac_ctrl = 0; -// uint8_t phase7_afe_offset = 0; - uint8_t phase7_led_en = 1; /* phase1 led enable*/ - - uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase7_led_en = 1; /* phase1 led enable*/ + uint8_t phase7_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase7_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ uint8_t phase8_inner_avg = 0; /* phase1 adc avg num 0=1, 1=2, 2=4, 3=8 , 4=16*/ - uint8_t phase8_tia_res = 0; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ - uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ - uint8_t phase8_led_drv1_cha_sel = 0; //IR_LED_SLE; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ + uint8_t phase8_tia_res = 5; /* 0= 10K; 1= 20k; 2= 50k; 3= 100k; 4= 150k; 5= 200k; 6= 500k; 7= 1M*/ + uint8_t phase8_tia_cap = 4; /* 0= ; 1= ; 2= ; 3= ; 4= ; 5= ; 6= ; 7= */ + uint8_t phase8_led_drv1_cha_sel = 0; /* 1 = ldr1; 2 = ldr2; 4 = ldr3; 8 = ldr4 ; */ uint8_t phase8_led_drv2_cha_sel = 0; - uint8_t phase8_pd_sel = 0x0c; /* 1 = pd1; 2 = pd2; */ + uint8_t phase8_pd_sel = 0; /* 1 = pd1; 2 = pd2; */ uint8_t phase8_als_offset_idac = 0; /* 0~255 = 0 ~ 128ua , step = 0.5ua */ - uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ + uint8_t phase8_led_offset_idac = 0; /* 0~255 = 0 ~ 64ua , step = 0.25ua */ uint8_t phase8_ldr1_cur = 0; /* 0~255 = 0 ~ 200ma, step = 0.8ma */ - uint8_t phase8_ldr2_cur = 0; -// uint8_t phase8_of_idac1_cur = 0; -// uint8_t phase8_of_idac2_cur = 0; + uint8_t phase8_ldr2_cur = 0; uint8_t phase8_ad_inr_ctrl = 3; uint8_t phase8_ad_of_idac_ctrl = 0; -// uint8_t phase8_afe_offset = 0; - uint8_t phase8_led_en = 1; /* phase1 led enable*/ - - uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ + uint8_t phase8_led_en = 1; /* phase1 led enable*/ + uint8_t phase8_dsp_mov_avg_num = 0; /* 0=bypass ; 1=2 ; 2=4 ; 3=8 */ uint8_t phase8_dsp_iir_lp_coeff = 0; /* 0=bypass ; 1=1/2 ; 2=1/4 ; 3=1/8 ,...,7=1/128 */ - uint8_t init_wait_delay = 5 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ; + uint8_t init_wait_delay = 4 ; /* 0 = 31clk ; 1 = 64clk ; 2 = 127clk ; 3 = 255clk(d) ; 4 = 511clk; 5 = 1023clk; 6 = 2047; 7 = 4095clk */ uint8_t afe_reset = 3; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d) ; 4 = 255clk; 5 = 511clk; 6 = 1024; 7 = 2047clk */ - uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/ - + uint8_t afe_rst_cnvt = 1; /* 0 = 15clk ; 1 = 31clk ; 2 = 63clk ; 3 = 127clk(d)*/ + uint8_t led_en_idac_pre = 2; /* 0 = 8clk ; 1 = 16clk ; 2 = 32clk ; 3 = 64clk(d)*/ - - uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ - + + uint8_t led_en_idac = 1; /* 0 = 4clk ; 1 = 8clk ; 2 = 16clk ; 3 = 32clk(d)*/ + uint8_t led_on_time = 2; /* 0 = 32clk=8us ; 1 = 64clk=16us; 2=128clk=32us ; 3 = 256clk=64us ; 4 = 512clk=128us ; 5 = 1024clk=256us; 6= 2048clk=512us; 7 = 4096clk=1024us */ hx3695_delay_ms(10); - + hx3695_write_reg(0X2a, (uint8_t)prf_clk_num); // prf bit<7:0>6 hx3695_write_reg(0X2b, (uint8_t)(prf_clk_num>>8)); // prf bit<15:8> hx3695_write_reg(0X2c, (uint8_t)(prf_clk_num>>16)); // prf bit<23:16> hx3695_write_reg(0X25, (afe_rst_cnvt<<4| led_en_idac_pre<<2|led_en_idac)); - hx3695_write_reg(0X2d, phase7_8_internal); - hx3695_write_reg(0X2e, 0x33);// gpio ctrl + hx3695_write_reg(0X2d, phase7_8_internal); + hx3695_write_reg(0X2e, 0x33);// gpio ctrl hx3695_write_reg(0X2f, ((afe_reset<<4)| init_wait_delay)); - hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); + hx3695_write_reg(0X30, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); hx3695_write_reg(0X72, (phase8_led_en<<7 | phase7_led_en<<6 |phase6_led_en<<5 |phase5_led_en<<4 |phase4_led_en<<3 | phase3_led_en<<2 | phase2_led_en<<1 | phase1_led_en) ); hx3695_write_reg(0X31, (led_on_time<<4| 0x00)); - hx3695_write_reg(0X33, 0x83);// 中断极性及宽度配置； - hx3695_write_reg(0X34, 0x00);// 中断特殊配置； - hx3695_write_reg(0X36, 0x00);// phase data ready 标志设置； - hx3695_write_reg(0X38, 0x00); + hx3695_write_reg(0X33, 0x83);// �жϼ��Լ��������ã� + hx3695_write_reg(0X34, 0x00);// �ж��������ã� + hx3695_write_reg(0X36, 0x00);// phase data ready ��־���ã� + hx3695_write_reg(0X38, 0x00); hx3695_write_reg(0X3a, (phase1_inner_avg | (phase2_inner_avg<<4))); hx3695_write_reg(0X3b, (phase3_inner_avg | (phase4_inner_avg<<4))); @@ -2393,206 +1761,201 @@ void hx3695_factory_ft_int_test_config(void)//中断测试配置 hx3695_write_reg(0X3e, adc_rst_post_num<<6 | samp_delay_leden_num<<4 | samp_copy_avg); hx3695_write_reg(0X3f, data_avg_num<<4 | data_avg_num ); hx3695_write_reg(0X40, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num ); - hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num ); - - hx3695_write_reg(0X43, phase1_mux_sel); - hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); - hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase1_als_offset_idac); - hx3695_write_reg(0X48, phase1_led_offset_idac); - + hx3695_write_reg(0X41, data_avg_num<<4 | data_avg_num ); + hx3695_write_reg(0X42, data_avg_num<<4 | data_avg_num ); + + hx3695_write_reg(0X43, phase1_mux_sel); + hx3695_write_reg(0X44, phase1_tia_cap<<4|phase1_tia_res); + hx3695_write_reg(0X45, phase1_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase1_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase1_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase1_als_offset_idac); + hx3695_write_reg(0X48, phase1_led_offset_idac); hx3695_write_reg(0X49, phase1_ad_inr_ctrl<<4|phase1_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase1_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase1_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase1_dsp_mov_avg_num | phase1_dsp_iir_lp_coeff<<4); -// hx3695_write_reg(0X4e, thred_value); -// hx3695_write_reg(0X4f, thred_value>>5); - + hx3695_write_reg(0X43, phase2_mux_sel); - hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); - hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase2_als_offset_idac); - hx3695_write_reg(0X48, phase2_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); + hx3695_write_reg(0X44, phase2_tia_cap<<4|phase2_tia_res); + hx3695_write_reg(0X45, phase2_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase2_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase2_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase2_als_offset_idac); + hx3695_write_reg(0X48, phase2_led_offset_idac); hx3695_write_reg(0X49, phase2_ad_inr_ctrl<<4|phase2_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase2_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase2_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase2_dsp_mov_avg_num | phase2_dsp_iir_lp_coeff<<4); //phase3 sel hx3695_write_reg(0X43, phase3_mux_sel); - hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); - hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase3_als_offset_idac); - hx3695_write_reg(0X48, phase3_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); + hx3695_write_reg(0X44, phase3_tia_cap<<4|phase3_tia_res); + hx3695_write_reg(0X45, phase3_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase3_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase3_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase3_als_offset_idac); + hx3695_write_reg(0X48, phase3_led_offset_idac); hx3695_write_reg(0X49, phase3_ad_inr_ctrl<<4|phase3_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase3_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase3_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase3_dsp_mov_avg_num | phase3_dsp_iir_lp_coeff<<4); //phase4 sel hx3695_write_reg(0X43, phase4_mux_sel); - hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); - hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase4_als_offset_idac); - hx3695_write_reg(0X48, phase4_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); + hx3695_write_reg(0X44, phase4_tia_cap<<4|phase4_tia_res); + hx3695_write_reg(0X45, phase4_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase4_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase4_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase4_als_offset_idac); + hx3695_write_reg(0X48, phase4_led_offset_idac); hx3695_write_reg(0X49, phase4_ad_inr_ctrl<<4|phase4_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4); - - hx3695_write_reg(0X43, phase5_mux_sel); - hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); - hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase5_pd_sel)); //<<4 | 0x00)); - hx3695_write_reg(0X47, phase5_als_offset_idac); - hx3695_write_reg(0X48, phase5_led_offset_idac); -// hx3695_write_reg(0X48, phase1_led_offset_idac); + hx3695_write_reg(0X4a, phase4_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase4_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase4_dsp_mov_avg_num | phase4_dsp_iir_lp_coeff<<4); + + hx3695_write_reg(0X43, phase5_mux_sel); + hx3695_write_reg(0X44, phase5_tia_cap<<4|phase5_tia_res); + hx3695_write_reg(0X45, phase5_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase5_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase5_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase5_als_offset_idac); + hx3695_write_reg(0X48, phase5_led_offset_idac); hx3695_write_reg(0X49, phase5_ad_inr_ctrl<<4|phase5_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4); - - - hx3695_write_reg(0X43, phase6_mux_sel); - hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); - hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase6_als_offset_idac); - hx3695_write_reg(0X48, phase6_led_offset_idac); -// hx3695_write_reg(0X48, phase6_led_offset_idac); + hx3695_write_reg(0X4a, phase5_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase5_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase5_dsp_mov_avg_num | phase5_dsp_iir_lp_coeff<<4); + + + hx3695_write_reg(0X43, phase6_mux_sel); + hx3695_write_reg(0X44, phase6_tia_cap<<4|phase6_tia_res); + hx3695_write_reg(0X45, phase6_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase6_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase6_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase6_als_offset_idac); + hx3695_write_reg(0X48, phase6_led_offset_idac); hx3695_write_reg(0X49, phase6_ad_inr_ctrl<<4|phase6_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase6_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase6_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase6_dsp_mov_avg_num | phase6_dsp_iir_lp_coeff<<4); - hx3695_write_reg(0X43, phase7_mux_sel); - hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); - hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase7_als_offset_idac); - hx3695_write_reg(0X48, phase7_led_offset_idac); -// hx3695_write_reg(0X48, phase7_led_offset_idac); + hx3695_write_reg(0X43, phase7_mux_sel); + hx3695_write_reg(0X44, phase7_tia_cap<<4|phase7_tia_res); + hx3695_write_reg(0X45, phase7_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase7_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase7_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase7_als_offset_idac); + hx3695_write_reg(0X48, phase7_led_offset_idac); hx3695_write_reg(0X49, phase7_ad_inr_ctrl<<4|phase7_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase7_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase7_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase7_dsp_mov_avg_num | phase7_dsp_iir_lp_coeff<<4); - hx3695_write_reg(0X43, phase8_mux_sel); - hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); - hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR - hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur - hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00)); - hx3695_write_reg(0X47, phase8_als_offset_idac); - hx3695_write_reg(0X48, phase8_led_offset_idac); -// hx3695_write_reg(0X48, phas8_led_offset_idac); + hx3695_write_reg(0X43, phase8_mux_sel); + hx3695_write_reg(0X44, phase8_tia_cap<<4|phase8_tia_res); + hx3695_write_reg(0X45, phase8_ldr1_cur); //LED_DRV1_CUR + hx3695_write_reg(0x70, phase8_ldr2_cur); //ps8--ps1 led_drv2_cur + hx3695_write_reg(0X46, (phase8_pd_sel<<4 | 0x00)); + hx3695_write_reg(0X47, phase8_als_offset_idac); + hx3695_write_reg(0X48, phase8_led_offset_idac); hx3695_write_reg(0X49, phase8_ad_inr_ctrl<<4|phase8_ad_of_idac_ctrl); - hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel); - hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel); - hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4); + hx3695_write_reg(0X4a, phase8_led_drv1_cha_sel); + hx3695_write_reg(0X4b, phase8_led_drv2_cha_sel); + hx3695_write_reg(0X71, phase8_dsp_mov_avg_num | phase8_dsp_iir_lp_coeff<<4); // analog circuit cfg - hx3695_write_reg(0X60, 0x14); // - hx3695_write_reg(0X61, 0xf0); - hx3695_write_reg(0X62, 0x22); - hx3695_write_reg(0X63, 0x15); - - hx3695_write_reg(0X64, 0x08); - hx3695_write_reg(0X65, 0x88); //bug - - hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30 - hx3695_write_reg(0X67, 0x23); - hx3695_write_reg(0X68, 0x46); - hx3695_write_reg(0X69, 0x42); - - hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg - hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable + hx3695_write_reg(0X60, 0x34); // + hx3695_write_reg(0X61, 0xf0); + hx3695_write_reg(0X62, 0x22); + hx3695_write_reg(0X63, 0x15); + + hx3695_write_reg(0X64, 0x08); + hx3695_write_reg(0X65, 0x88); //bug + + hx3695_write_reg(0X66, 0x30); // bits<3>=adc selftest en 0x30 + hx3695_write_reg(0X67, 0x23); + hx3695_write_reg(0X68, 0x46); + hx3695_write_reg(0X69, 0x42); + + hx3695_write_reg(0X39, 0xff); // ofset idac1 phase enable cfg + hx3695_write_reg(0x73, 0xff); //led_offset_idac phase enable hx3695_write_reg(0X6a, 0X0f); - hx3695_write_reg(0X6b, 0X22); - hx3695_write_reg(0X6c, 0X00); - hx3695_write_reg(0X6d, 0X37); - hx3695_write_reg(0X6e, 0X82); - hx3695_write_reg(0X6f, 0X08); + hx3695_write_reg(0X6b, 0X22); + hx3695_write_reg(0X6c, 0X00); + hx3695_write_reg(0X6d, 0X37); + hx3695_write_reg(0X6e, 0X82); + hx3695_write_reg(0X6f, 0X00); /////////FIFO and adc conversion ready config//////// /////////FIFO and adc conversion ready config//////// -#if defined(PPG_INT_MODE) - hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3; - // 0011=p4;0100=p5;0101=p6;0110=p7; - // bits<7> fifo enble - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear - hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int -#elif defined(INT_MODE) //FIFO_ALL_MOST_FULL) - hx3695_write_reg(0X1b, 0x92);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3; - // 0011=p4;0100=p5;0101=p6;0110=p7; - // bits<7> fifo enble - hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark - hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] - hx3695_write_reg(0X33, 0x83); // int width - hx3695_write_reg(0X21, 0x00); // fifo int sel,00=FIFO INT config clear - hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int +#if defined(INT_MODE) //(FIFO_ALL_MOST_FULL) + hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;\ + 0011=p4;0100=p5;0101=p6;0110=p7;\ + bits<7> fifo enble + hx3695_write_reg(0X1c, (fifo_watermark&0xff)); //fifo_watermark + hx3695_write_reg(0X1d, fifo_watermark<<8); //bit<0>=fifo_watermark[8] + hx3695_write_reg(0X33, 0x83); // int width + hx3695_write_reg(0X38, 0x04); // int sel,00=close almost full int,04=enable almost full int #else - hx3695_write_reg(0X1b, 0x92); // bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3; - // 0011=p4;0100=p5;0101=p6;0110=p7; - // bits<7> fifo enble - hx3695_write_reg(0X38, 0x01); // int sel,00=close almost full int,04=enable almost full int - + hx3695_write_reg(0X1b, 0x90);// bits<3:0> fifo data sel, 0000 = p1;0001= p2;0010=p3;0011=p4;0100=p5;0101=p6;0110=p7;bits<7> fifo enble + hx3695_write_reg(0X36, 0x00); //intrupt + + hx3695_write_reg(0X38, 0x00); // int sel,00=close almost full int,01= prf int 04=enable almost full int + #endif - hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); - hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); - hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) ); - hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); + hx3695_write_reg(0X26,(phase1_enable<<3)|(phase1_adc_osr)|(phase2_enable<<7)|(phase2_adc_osr<<4) ); + hx3695_write_reg(0X27,(phase3_enable<<3)|(phase3_adc_osr)|(phase4_enable<<7)|(phase4_adc_osr<<4) ); + hx3695_write_reg(0X28,(phase5_enable<<3)|(phase5_adc_osr)|(phase6_enable<<7)|(phase6_adc_osr<<4) ); + hx3695_write_reg(0X29,(phase7_enable<<3)|(phase7_adc_osr)|(phase8_enable<<7)|(phase8_adc_osr<<4) ); // hx3695_write_reg(0X5c, 0x02);//soft reset - hx3695_delay_ms(5); - hx3695_write_reg(0X5c, 0x00);//release + hx3695_delay_ms(5); + hx3695_write_reg(0X5c, 0x00);//release - + return ; + } bool hx3695_factory_test_read(int32_t *phase_data) { uint8_t databuf[12] = {0}; + uint8_t databuf2[12] = {0}; int32_t P1 = 0, P2 = 0,P3 = 0,P4 = 0; + int32_t P5 = 0, P6 = 0,P7 = 0,P8 = 0; + uint8_t m,k; hx3695_brust_read_reg(0x03, databuf, 12); + hx3695_brust_read_reg(0x0F, databuf2, 12); P1 = ((databuf[0])|(databuf[1]<<8)|(databuf[2]<<16)); P2 = ((databuf[3])|(databuf[4]<<8)|(databuf[5]<<16)); P3 = ((databuf[6])|(databuf[7]<<8)|(databuf[8]<<16)); P4 = ((databuf[9])|(databuf[10]<<8)|(databuf[11]<<16)); - + + P5 = ((databuf2[0])|(databuf2[1]<<8)|(databuf2[2]<<16)); + P6 = ((databuf2[3])|(databuf2[4]<<8)|(databuf2[5]<<16)); + P7 = ((databuf2[6])|(databuf2[7]<<8)|(databuf2[8]<<16)); + P8 = ((databuf2[9])|(databuf2[10]<<8)|(databuf2[11]<<16)); phase_data[0] = P1 ; phase_data[1] = P2 ; phase_data[2] = P3 ; phase_data[3] = P4 ; + phase_data[4] = P5 ; + phase_data[5] = P6 ; + phase_data[6] = P7 ; + phase_data[7] = P8 ; + +// DEBUG_PRINTF("p1,p2,p3,p4,p5,p6,p7 %d %d %d %d %d %d %d\r\n", P1, P2, P3, P4,P5, P6,P7); - DEBUG_PRINTF("p1,p2,p3,p4 %d %d %d %d\r\n", P1, P2, P3, P4); return true; } - int32_t hx3695_sort_cal(int32_t *data) { uint8_t ii,jj; @@ -2613,7 +1976,66 @@ int32_t hx3695_sort_cal(int32_t *data) data_final = (data[1]+data[2])>>1; return data_final; } - +int32_t hx3695_sort_cal_min(int32_t *data) +{ + uint8_t ii,jj; + int32_t data_temp = 0; + int32_t data_final = 0; + for(ii=0; ii<(TEST_NUM-1); ii++) + { + for(jj=0; jj<9-ii; jj++) + { + if(data[jj]>=data[jj+1]) + { + data_temp = data[jj]; + data[jj] = data[jj+1]; + data[jj+1] = data_temp; + } + } + } + data_final = data[0]; + return data_final; +} +int32_t hx3695_sort_cal_mid(int32_t *data) +{ + uint8_t ii,jj; + int32_t data_temp = 0; + int32_t data_final = 0; + for(ii=0; ii<(TEST_NUM-1); ii++) + { + for(jj=0; jj<9-ii; jj++) + { + if(data[jj]>=data[jj+1]) + { + data_temp = data[jj]; + data[jj] = data[jj+1]; + data[jj+1] = data_temp; + } + } + } + data_final = ((data[3]+data[4]+data[5]+data[6]+data[7]+data[8])/6); + return data_final; +} +int32_t hx3695_sort_cal_max(int32_t *data) +{ + uint8_t ii,jj; + int32_t data_temp = 0; + int32_t data_final = 0; + for(ii=0; ii<(TEST_NUM-1); ii++) + { + for(jj=0; jj<9-ii; jj++) + { + if(data[jj]>=data[jj+1]) + { + data_temp = data[jj]; + data[jj] = data[jj+1]; + data[jj+1] = data_temp; + } + } + } + data_final = data[9]; + return data_final; +} bool hx3695_chip_check_id(void) { @@ -2631,290 +2053,595 @@ bool hx3695_chip_check_id(void) return false; } -FT_RESULTS_t hx3695_factory_led_off_get_result(void) +bool hx3695_led_off(void) { - uint8_t ii = 0; - int32_t phase_data[4] = {0,0,0,0}; - int32_t phase1_data[4] = {0,0,0,0}; - int32_t phase2_data[4] = {0,0,0,0}; - int32_t phase3_data[4] = {0,0,0,0}; - int32_t phase4_data[4] = {0,0,0,0}; - int32_t gr_buffer[4] = {0,0,0,0}; - int32_t red_buffer[4] = {0,0,0,0}; - int32_t ir_buffer[4] = {0,0,0,0}; - FT_RESULTS_t ft_result = {0,0,0,0,0,0,0,0,0,0,0,0}; + hx3695_delay_ms(10); + hx3695_write_reg(0x30, 0x00); + hx3695_write_reg(0x72, 0x00); + hx3695_delay_ms(100); + return 1; +} +FT_RESULTS_t hx3695_factory_ft_leak_light_test_get_result(void) +{ + uint8_t ii = 0; + int32_t phase_data[8] = {0,0,0,0,0,0,0,0}; + int32_t ldr0_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + int32_t ldr1_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + int32_t ldr2_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + int32_t ldr3_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + int32_t ldr4_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + int32_t ldr5_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + int32_t ldr0_OFF_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + int32_t ldr1_OFF_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + int32_t ldr2_OFF_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + int32_t ldr3_OFF_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + int32_t ldr4_OFF_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + int32_t ldr5_OFF_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + int32_t ldr0_data_ledoff = 0; + int32_t ldr1_data_ledoff = 0; + int32_t ldr2_data_ledoff = 0; + int32_t ldr3_data_ledoff = 0; + int32_t ldr4_data_ledoff = 0; + int32_t ldr5_data_ledoff = 0; + int32_t ldr0_data_ledon = 0; + int32_t ldr1_data_ledon = 0; + int32_t ldr2_data_ledon = 0; + int32_t ldr3_data_ledon = 0; + int32_t ldr4_data_ledon = 0; + int32_t ldr5_data_ledon = 0; +// uint8_t i,j; + FT_RESULTS_t ft_result = {0}; + + for(ii=0; ii 0) { - ft_result.red_data_final = 0; + ft_result.single_gr_led_judge = ft_result.ldr0_data_final*100/ft_result.ldr0_data_final; } - if(ft_result.ir_data_final < 0) + if(ldr3_buffer[0] == ldr3_buffer[1] && ldr3_buffer[0] == ldr3_buffer[2] && ldr3_buffer[0] == ldr3_buffer[3]) { - ft_result.ir_data_final = 0; + ft_result.ldr3_data_final = 0; + ft_result.ldr4_data_final = 0; + ft_result.ldr5_data_final = 0; + } + if(ft_result.ldr3_data_final < 0) + { + ft_result.ldr3_data_final = 0; + } + if(ft_result.ldr4_data_final < 0) + { + ft_result.ldr4_data_final = 0; + } + if(ft_result.ldr5_data_final < 0) + { + ft_result.ldr5_data_final = 0; } return ft_result; } - -FT_RESULTS_t hx3695_factory_ft_single_check_get_result(void) +FT_RESULTS_t hx3695_factory_ft_aging_test_get_result(void) { uint8_t ii = 0; - int32_t phase_data[4] = {0,0,0,0}; - int32_t gr_buffer[4] = {0,0,0,0}; - int32_t red_buffer[4] = {0,0,0,0}; - int32_t ir_buffer[4] = {0,0,0,0}; - FT_RESULTS_t ft_result = {0,0,0,0,0,0,0,0,0,0,0,0}; - - for(ii=0; ii<4; ii++) + int32_t phase_data[8] = {0,0,0,0,0,0,0,0}; + int32_t ldr0_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + int32_t ldr1_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + int32_t ldr2_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + int32_t ldr3_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + int32_t ldr4_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + int32_t ldr5_buffer[10] = {0,0,0,0,0,0,0,0,0,0}; + + FT_RESULTS_t ft_result = {0}; + + for(ii=0; ii 0) + if(ft_result.ldr3_data_final < 0) { - ft_result.single_gr_led_judge = ft_result.gr_data_high*100/ft_result.gr_data_final; + ft_result.ldr3_data_final = 0; + } + if(ft_result.ldr4_data_final < 0) + { + ft_result.ldr4_data_final = 0; + } + if(ft_result.ldr5_data_final < 0) + { + ft_result.ldr5_data_final = 0; } - return ft_result; } - FT_RESULTS_t hx3695_factroy_test(TEST_MODE_t test_mode) { - FT_RESULTS_t ft_result = {0,0,0,0,0,0,0,0,0,0,0,0}; - //if (hx3695_chip_check_id() == false) - { - // return ft_result; - } + FT_RESULTS_t ft_result = {0}; + switch(test_mode) { - case LED_OFF_TEST: - hx3695_factory_led_off_config(); - hx3695_delay_ms(50); - ft_result = hx3695_factory_led_off_get_result(); - break; - case WEAR_MODE_TEST: - hx3695_factory_wear_mode_config(); - hx3695_delay_ms(50); - ft_result = hx3695_factory_wear_mode_get_result(); - break; + case LEAK_LIGHT_TEST: + hx3695_factory_ft_leak_light_test_config(); hx3695_delay_ms(50); ft_result = hx3695_factory_ft_leak_light_test_get_result(); - factory_green = ft_result.gr_data_final; - factory_red = ft_result.red_data_final; - factory_ir = ft_result.ir_data_final; - printf("factory_green : %d, factory_red:%d, factory_ir:%d\n",factory_green,factory_red,factory_ir); + // hrsresult.leak_ldr0 = ft_result.ldr0_data_final; + // hrsresult.leak_ldr1 = ft_result.ldr1_data_final; + // hrsresult.leak_ldr2 = ft_result.ldr2_data_final; + + factory_green = ft_result.ldr0_data_final; + factory_red = ft_result.ldr1_data_final; + factory_ir = ft_result.ldr2_data_final; + + // TYHX_LOG("leak LDR0=%d\r\n",hrsresult.leak_ldr0); break; + case GRAY_CARD_TEST: + hx3695_factory_ft_card_test_config(); hx3695_delay_ms(50); ft_result = hx3695_factory_ft_card_test_get_result(); - factory_green = ft_result.gr_data_final; - factory_red = ft_result.red_data_final; - factory_ir = ft_result.ir_data_final; + // hrsresult.card_ldr0 = ft_result.ldr0_data_final; + // hrsresult.card_ldr1 = ft_result.ldr1_data_final; + // hrsresult.card_ldr2 = ft_result.ldr2_data_final; + + factory_green = ft_result.ldr0_data_final; + factory_red = ft_result.ldr1_data_final; + factory_ir = ft_result.ldr2_data_final; break; - case FT_INT_TEST: - hx3695_factory_ft_int_test_config(); + case GNOISE_TEST: + hx3695_factory_Gnoise_config(); + hx3695_delay_ms(50); + ft_result = hx3695_factory_Gnoise_result(); break; - case SINGLE_CHECK_TEST: + case SINGLE_CHECK_TEST: hx3695_factory_ft_single_check_config(); hx3695_delay_ms(50); ft_result = hx3695_factory_ft_single_check_get_result(); break; - default: + case AGING_CHECK_TEST: + hx3695_factory_ft_aging_check_config(); + hx3695_delay_ms(50); + ft_result = hx3695_factory_ft_aging_test_get_result(); break; } - //hx3695_ppg_off(); - DEBUG_PRINTF("%d %d %d %d %d %d %d %d %d %d %d %d\r\n", ft_result.phase1_data_avg, ft_result.phase2_data_avg, ft_result.phase3_data_avg, ft_result.phase4_data_avg, \ - ft_result.gr_ps_dif, ft_result.red_ps_dif, ft_result.ir_ps_dif, ft_result.gr_data_final, ft_result.red_data_final, ft_result.ir_data_final, ft_result.gr_data_high, \ - ft_result.single_gr_led_judge); + //hx3695_ppg_off(); +// DEBUG_PRINTF("%d %d %d %d %d %d %d %d %d %d %d %d\r\n", ft_result.phase1_data_avg, ft_result.phase2_data_avg, ft_result.phase3_data_avg, ft_result.phase4_data_avg, \ +// ft_result.ldr0_data_final, ft_result.ldr1_data_final, ft_result.ldr2_data_final, ft_result.ldr0_data_final, ft_result.ldr1_data_final, ft_result.ldr2_data_final, ft_result.ldr0_data_final, \ +// ft_result.single_gr_led_judge); return ft_result; } diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_factory_test.h b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_factory_test.h index 54cef21c3..723a9fc9f 100644 --- a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_factory_test.h +++ b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_factory_test.h @@ -1,24 +1,61 @@ -/* - * @Author: penglei 1624952103@qq.com - * @Date: 2025-05-15 11:28:07 - * @LastEditors: penglei 1624952103@qq.com - * @LastEditTime: 2025-07-31 17:02:23 - * @FilePath: /FD230/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_factory_test.h - * @Description: 这是默认设置,请设置`customMade`, 打开koroFileHeader查看配置 进行设置: https://github.com/OBKoro1/koro1FileHeader/wiki/%E9%85%8D%E7%BD%AE - */ #ifndef _HX3695_FACTORY_TEST_H_ #define _HX3695_FACTORY_TEST_H_ #include #include + +/***********ѡ��*************/ +#define LDR0_FT_SEL 0x50 +#define LDR1_FT_SEL 0x28 +#define LDR2_FT_SEL 0x81 +#define LDR3_FT_SEL 0x81 +#define LDR4_FT_SEL 0x40 +#define LDR5_FT_SEL 0x80 + +/***********Ñ¡PD*************/ +#define LDR0_PD_FT_SEL 0x06 +#define LDR1_PD_FT_SEL 0x06 +#define LDR2_PD_FT_SEL 0x06 +#define LDR3_PD_FT_SEL 0x06 +#define LDR4_PD_FT_SEL 0x0f +#define LDR5_PD_FT_SEL 0x0f +#define ALS_PD_FT_SEL 0x0f + +/***********���õ���*************/ + +#define DRV1_LEAK_CUR 64 //Ĭ������ led driver 1 ����50MA��driver2�����õ��� +#define DRV2_LEAK_CUR 0 + +#define DRV1_GRAD_CUR 32 //Ĭ������ led driver 1 ����25MA��driver2�����õ��� +#define DRV2_GRAD_CUR 0 + +#define DRV1_AGING_CUR 128 //Ĭ������ led driver 1 ����100MA��driver2����100MA���� �ϼ�200mA +#define DRV2_AGING_CUR 128 + +#define DRV1_SINGLE_CUR 64 //Ĭ������ led driver 1 ����50MA��driver2�����õ��� +#define DRV2_SINGLE_CUR 0 + +/***********��������TIA*************/ + +#define PS_LEAK_TIA 5 + +#define PS_GRAD_TIA 1 + +#define PS_AGING_TIA 5 + +#define PS_SINGLE_TIA 3 + +#define PS_Gnoise_TIA 3 + +#define TEST_NUM 6 //���Դ��� +#define LDR_NUM 3 //LDR�ò¿ª¸ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ldr˳�ò¿ª¹ï¿½ typedef enum { LEAK_LIGHT_TEST = 1, GRAY_CARD_TEST = 2, - FT_INT_TEST = 3, - SINGLE_CHECK_TEST = 4, - LED_OFF_TEST = 5, - WEAR_MODE_TEST = 6 + GNOISE_TEST=3, + SINGLE_CHECK_TEST=4, + AGING_CHECK_TEST=5 } TEST_MODE_t; typedef struct { @@ -26,19 +63,31 @@ typedef struct { int32_t phase2_data_avg; int32_t phase3_data_avg; int32_t phase4_data_avg; - int32_t gr_ps_dif; - int32_t red_ps_dif; - int32_t ir_ps_dif; - int32_t gr_data_final; - int32_t red_data_final; - int32_t ir_data_final; - int32_t gr_data_high; + int32_t phase5_data_avg; + int32_t phase6_data_avg; + int32_t phase7_data_avg; + int32_t phase8_data_avg; + int32_t ldr0_ps_dif; + int32_t ldr1_ps_dif; + int32_t ldr2_ps_dif; + int32_t ldr0_data_final; + int32_t ldr1_data_final; + int32_t ldr2_data_final; + int32_t ldr0_data_high; + int32_t ldr3_ps_dif; + int32_t ldr4_ps_dif; + int32_t ldr5_ps_dif; + int32_t ldr3_data_final; + int32_t ldr4_data_final; + int32_t ldr5_data_final; + int32_t ldr3_data_high; int32_t single_gr_led_judge; } FT_RESULTS_t; void hx3695_factory_ft_leak_light_test_config(void); void hx3695_factory_ft_card_test_config(void); void hx3695_factory_ft_int_test_config(void); +void hx3695_factory_new_config_init(void) ; bool hx3695_factory_test_read(int32_t *phase_data); FT_RESULTS_t hx3695_factroy_test(TEST_MODE_t test_mode); diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrs_agc.c b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrs_agc.c index 45936e219..9c63fff23 100644 --- a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrs_agc.c +++ b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrs_agc.c @@ -816,35 +816,35 @@ void hx3695_hrs_set_mode(uint8_t mode_cmd) } } -SENSOR_ERROR_T hx3695_hrs_enable(void) -{ - if (!hx3695_chip_check()) - { - AGC_LOG("hx3695 check id failed!\r\n"); - return SENSOR_OP_FAILED; - } +// SENSOR_ERROR_T hx3695_hrs_enable(void) +// { +// if (!hx3695_chip_check()) +// { +// AGC_LOG("hx3695 check id failed!\r\n"); +// return SENSOR_OP_FAILED; +// } - AGC_LOG("hx3695 check id success!\r\n"); +// AGC_LOG("hx3695 check id success!\r\n"); - if (s_ppg_state) - { - AGC_LOG("ppg already on!\r\n"); - return SENSOR_OP_FAILED; - } - if(!tyhx_hrs_alg_open()) - { - AGC_LOG("hrs alg open fail,or dynamic ram not enough!\r\n"); - } +// if (s_ppg_state) +// { +// AGC_LOG("ppg already on!\r\n"); +// return SENSOR_OP_FAILED; +// } +// if(!tyhx_hrs_alg_open()) +// { +// AGC_LOG("hrs alg open fail,or dynamic ram not enough!\r\n"); +// } - hrs_wear_status = MSG_HRS_NO_WEAR; - hrs_wear_status_pre = MSG_HRS_NO_WEAR; +// hrs_wear_status = MSG_HRS_NO_WEAR; +// hrs_wear_status_pre = MSG_HRS_NO_WEAR; - hx3695_hrs_set_mode(PPG_INIT); +// hx3695_hrs_set_mode(PPG_INIT); - AGC_LOG("hx3695 enable!\r\n"); +// AGC_LOG("hx3695 enable!\r\n"); - return SENSOR_OK; -} +// return SENSOR_OK; +// } void hx3695_hrs_disable(void) { @@ -896,83 +896,83 @@ HRS_CAL_SET_T get_hrs_agc_status(void) return cal; } -uint8_t hx3695_hrs_read(hrs_sensor_data_t * s_dat) -{ - int32_t PPG_src_data, PPG_src_data2; - int32_t Ir_src_data; - bool recal = false; - uint8_t size = 0; - uint8_t data_count = 0; - uint8_t size_byte = 0; - int32_t *PPG_buf = &(s_dat->green_data[0]); - int32_t *ir_buf = &(s_dat->ir_data[0]); - int32_t *s_buf = &(s_dat->s_buf[0]); +// uint8_t hx3695_hrs_read(hrs_sensor_data_t * s_dat) +// { +// int32_t PPG_src_data, PPG_src_data2; +// int32_t Ir_src_data; +// bool recal = false; +// uint8_t size = 0; +// uint8_t data_count = 0; +// uint8_t size_byte = 0; +// int32_t *PPG_buf = &(s_dat->green_data[0]); +// int32_t *ir_buf = &(s_dat->ir_data[0]); +// int32_t *s_buf = &(s_dat->s_buf[0]); - int32_t ps_data[8] = {0}; - int32_t ps_green_data = 0; - s_dat->agc_green = calReg_Hrs.Group1_Cur; - - if (!s_ppg_state || hrs_cal_state) - { -// TYHX_LOG("ppg_state: %d ,hrs_cal_state: %d\r\n",s_ppg_state,hrs_cal_state); - return 0; - } -// TYHX_LOG("ppg_state: %d ,hrs_cal_state: %d\r\n",s_ppg_state,hrs_cal_state); - data_count = hx3695_read_fifo_data(s_buf,hrs_phase_num,1); - - if(data_count > 9) - return 0; - - // PRINT("ppg data size: %d %d\r\n", data_count,hrs_phase_num); -// SEGGER_RTT_printf(0,"af_hx3695_read_fifo_data:::%d %d %d\r\n", hx3695_read_reg(0X2a),hx3695_read_reg(0X2b),hx3695_read_reg(0X2c)); - s_dat->count = data_count; - - read_hrs_data_packet(ps_data); - for (uint8_t i=0; i>1); -// SEGGER_RTT_printf(0,"ps_green_data: %d PS8: %d, PS7: %d\r\n", ps_green_data,ps_data[7],ps_data[6]); - if (ps_green_data<300000 || ps_green_data>800000) - { - recal = true; +// int32_t ps_data[8] = {0}; +// int32_t ps_green_data = 0; +// s_dat->agc_green = calReg_Hrs.Group1_Cur; + +// if (!s_ppg_state || hrs_cal_state) +// { +// // TYHX_LOG("ppg_state: %d ,hrs_cal_state: %d\r\n",s_ppg_state,hrs_cal_state); +// return 0; +// } +// // TYHX_LOG("ppg_state: %d ,hrs_cal_state: %d\r\n",s_ppg_state,hrs_cal_state); +// data_count = hx3695_read_fifo_data(s_buf,hrs_phase_num,1); + +// if(data_count > 9) +// return 0; + +// // PRINT("ppg data size: %d %d\r\n", data_count,hrs_phase_num); +// // SEGGER_RTT_printf(0,"af_hx3695_read_fifo_data:::%d %d %d\r\n", hx3695_read_reg(0X2a),hx3695_read_reg(0X2b),hx3695_read_reg(0X2c)); +// s_dat->count = data_count; + +// read_hrs_data_packet(ps_data); +// for (uint8_t i=0; i>1); +// // SEGGER_RTT_printf(0,"ps_green_data: %d PS8: %d, PS7: %d\r\n", ps_green_data,ps_data[7],ps_data[6]); +// if (ps_green_data<300000 || ps_green_data>800000) +// { +// recal = true; - if(hrs_wear_status==MSG_HRS_NO_WEAR) - { - recal = false; - } - } - if (recal) - //if (0) - { - cal_delay--; - - if (cal_delay <= 0) - { - cal_delay = CAL_DELAY_COUNT; - hx3695_hrs_set_mode(RECAL_INIT); - AGC_LOG("========>>>>LED_IDAC = %d %d %d\r\n",calReg_Hrs.Group1_Ledidac,calReg_Hrs.Group2_Ledidac,calReg_Hrs.Group3_Ledidac); - } - } - else - { - cal_delay = CAL_DELAY_COUNT; - } -// } - return 1; -} +// if(hrs_wear_status==MSG_HRS_NO_WEAR) +// { +// recal = false; +// } +// } +// if (recal) +// //if (0) +// { +// cal_delay--; + +// if (cal_delay <= 0) +// { +// cal_delay = CAL_DELAY_COUNT; +// hx3695_hrs_set_mode(RECAL_INIT); +// AGC_LOG("========>>>>LED_IDAC = %d %d %d\r\n",calReg_Hrs.Group1_Ledidac,calReg_Hrs.Group2_Ledidac,calReg_Hrs.Group3_Ledidac); +// } +// } +// else +// { +// cal_delay = CAL_DELAY_COUNT; +// } +// // } +// return 1; +// } #endif diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrs_agc.h b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrs_agc.h index 91aea996f..d18ec000d 100644 --- a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrs_agc.h +++ b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrs_agc.h @@ -102,10 +102,10 @@ void hx3695_hrs_low_power(void); void hx3695_hrs_normal_power(void); void hx3695_hrs_updata_reg(void); void hx3695_hrs_set_mode(uint8_t mode_cmd); -SENSOR_ERROR_T hx3695_hrs_enable(void); +// SENSOR_ERROR_T hx3695_hrs_enable(void); void hx3695_hrs_disable(void); hrs_wear_msg_code_t hx3695_hrs_get_wear_status(void); -uint8_t hx3695_hrs_read(hrs_sensor_data_t *s_dat); +// uint8_t hx3695_hrs_read(hrs_sensor_data_t *s_dat); bool hx3695_hrs_init(void); hrs_wear_msg_code_t hx3695_hrs_wear_mode_check(WORK_MODE_T mode, int32_t infrared_data); diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrv_agc.c b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrv_agc.c index 1bf291643..4767286b9 100644 --- a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrv_agc.c +++ b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrv_agc.c @@ -1,3 +1,11 @@ +/* + * @Author: penglei 1624952103@qq.com + * @Date: 2025-05-15 11:28:07 + * @LastEditors: penglei 1624952103@qq.com + * @LastEditTime: 2025-10-25 10:14:36 + * @FilePath: /FD230/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrv_agc.c + * @Description: 这是默认设置,请设置`customMade`, 打开koroFileHeader查看配置 进行设置: https://github.com/OBKoro1/koro1FileHeader/wiki/%E9%85%8D%E7%BD%AE + */ #include #include #include @@ -579,35 +587,37 @@ void hx3695_hrv_set_mode(uint8_t mode_cmd) } } -SENSOR_ERROR_T hx3695_hrv_enable(void) -{ - if (!hx3695_chip_check()) - { - AGC_LOG("hx3695 check id failed!\r\n"); - return SENSOR_OP_FAILED; - } +// SENSOR_ERROR_T hx3695_hrv_enable(void) +// { +// if (!hx3695_chip_check()) +// { +// AGC_LOG("hx3695 check id failed!\r\n"); +// return SENSOR_OP_FAILED; +// } - AGC_LOG("hx3695 check id success!\r\n"); +// AGC_LOG("hx3695 check id success!\r\n"); - if (s_ppg_state) - { - AGC_LOG("ppg already on!\r\n"); - return SENSOR_OP_FAILED; - } - if(!tyhx_hrv_alg_open()) - { - AGC_LOG("hrv alg open fail,or dynamic ram not enough!\r\n"); - } +// if (s_ppg_state) +// { +// AGC_LOG("ppg already on!\r\n"); +// return SENSOR_OP_FAILED; +// } +// if(!tyhx_hrv_alg_open()) +// { +// AGC_LOG("hrv alg open fail,or dynamic ram not enough!\r\n"); +// } - hrv_wear_status = MSG_HRV_NO_WEAR; - hrv_wear_status_pre = MSG_HRV_NO_WEAR; +// hrv_wear_status = MSG_HRV_NO_WEAR; +// hrv_wear_status_pre = MSG_HRV_NO_WEAR; - hx3695_hrv_set_mode(PPG_INIT); +// hx3695_hrv_set_mode(PPG_INIT); - AGC_LOG("hx3695 enable!\r\n"); +// AGC_LOG("hx3695 enable!\r\n"); - return SENSOR_OK; -} +// printf("hx3695_hrv_enable!!!\n"); + +// return SENSOR_OK; +// } void hx3695_hrv_disable(void) @@ -710,75 +720,75 @@ HRV_CAL_SET_T get_hrv_agc_status(void) // } //} -uint8_t hx3695_hrv_read(hrv_sensor_data_t *s_dat) -{ - uint8_t i = 0; - int32_t PPG_src_data = 0; - int32_t Ir_src_data = 0; - bool recal = false; - uint8_t size = 0; - uint8_t fifo_out_size = 0; - int32_t *PPG_buf = &(s_dat->green_data[0]); - int32_t *ir_buf = &(s_dat->ir_data[0]); - int32_t *s_buf = &(s_dat->s_buf[0]); - s_dat->green_cur = calReg.LED; - int32_t ps_data[4]; - - if (!s_ppg_state || s_cal_state) - { - DEBUG_PRINTF("ppg state = %d, cal_state = %d\r\n",s_ppg_state,s_cal_state); - return 0; - } -// size = hx3695_read_fifo_size(); -// DEBUG_PRINTF("size = %d\r\n",size); - -// if(size<1) -// { -// return 0; -// } - - hx3695_hrv_read_data_packet(ps_data); - Ir_src_data = ps_data[2]-ps_data[3]; - DEBUG_PRINTF("%d %d \r\n" ,ps_data[2],ps_data[3]); - ir_buf[0] = Ir_src_data; - //DEBUG_PRINTF("111: %d \r\n" ,ir_buf[0] ); - hx3695_hrv_wear_mode_check(Ir_src_data); - -// if ((size) && (size <= 64)) -// { - fifo_out_size = hx3695_read_fifo_data(s_buf,hrv_phase_num,1); - s_dat->count = fifo_out_size; - for (i=0; i750000) - { - recal = true; - - if(hrv_wear_status==MSG_HRV_NO_WEAR) - { - recal = false; - } - } - PPG_buf[i] = PPG_src_data; - //AGC_LOG("%d/%d %d %d %d\r\n" ,1+i,size, s_buf[i],calReg.LED,recal); - } - - if (recal) - { - cal_delay--; - if (cal_delay <= 0) - { - cal_delay = HRV_CAL_DELAY_COUNT; - hx3695_hrv_set_mode(RECAL_INIT); - } - } - else - { - cal_delay = HRV_CAL_DELAY_COUNT; - } -// } - return 1; -} +// uint8_t hx3695_hrv_read(hrv_sensor_data_t *s_dat) +// { +// uint8_t i = 0; +// int32_t PPG_src_data = 0; +// int32_t Ir_src_data = 0; +// bool recal = false; +// uint8_t size = 0; +// uint8_t fifo_out_size = 0; +// int32_t *PPG_buf = &(s_dat->green_data[0]); +// int32_t *ir_buf = &(s_dat->ir_data[0]); +// int32_t *s_buf = &(s_dat->s_buf[0]); +// s_dat->green_cur = calReg.LED; +// int32_t ps_data[4]; + +// if (!s_ppg_state || s_cal_state) +// { +// DEBUG_PRINTF("ppg state = %d, cal_state = %d\r\n",s_ppg_state,s_cal_state); +// return 0; +// } +// // size = hx3695_read_fifo_size(); +// // DEBUG_PRINTF("size = %d\r\n",size); + +// // if(size<1) +// // { +// // return 0; +// // } + +// hx3695_hrv_read_data_packet(ps_data); +// Ir_src_data = ps_data[2]-ps_data[3]; +// DEBUG_PRINTF("%d %d \r\n" ,ps_data[2],ps_data[3]); +// ir_buf[0] = Ir_src_data; +// DEBUG_PRINTF("111: %d \r\n" ,ir_buf[0] ); +// hx3695_hrv_wear_mode_check(Ir_src_data); + +// // if ((size) && (size <= 64)) +// // { +// fifo_out_size = hx3695_read_fifo_data(s_buf,hrv_phase_num,1); +// s_dat->count = fifo_out_size; +// for (i=0; i750000) +// { +// recal = true; + +// if(hrv_wear_status==MSG_HRV_NO_WEAR) +// { +// recal = false; +// } +// } +// PPG_buf[i] = PPG_src_data; +// AGC_LOG("%d/%d %d %d %d\r\n" ,1+i,size, s_buf[i],calReg.LED,recal); +// } + +// if (recal) +// { +// cal_delay--; +// if (cal_delay <= 0) +// { +// cal_delay = HRV_CAL_DELAY_COUNT; +// hx3695_hrv_set_mode(RECAL_INIT); +// } +// } +// else +// { +// cal_delay = HRV_CAL_DELAY_COUNT; +// } +// // } +// return 1; +// } #endif diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrv_agc.h b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrv_agc.h index 3804a5bce..5fa5b0759 100644 --- a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrv_agc.h +++ b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrv_agc.h @@ -1,3 +1,11 @@ +/* + * @Author: penglei 1624952103@qq.com + * @Date: 2025-05-15 11:28:07 + * @LastEditors: penglei 1624952103@qq.com + * @LastEditTime: 2025-10-25 10:13:59 + * @FilePath: /FD230/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_hrv_agc.h + * @Description: 这是默认设置,请设置`customMade`, 打开koroFileHeader查看配置 进行设置: https://github.com/OBKoro1/koro1FileHeader/wiki/%E9%85%8D%E7%BD%AE + */ #ifndef _hx3695_hrv_agc_H_ #define _hx3695_hrv_agc_H_ //#endif @@ -71,10 +79,10 @@ void hx3695_hrv_read_data_packet(int32_t *buf); void hx3695_hrv_low_power(void); void hx3695_hrv_updata_reg(void); void hx3695_hrv_set_mode(uint8_t mode_cmd); -SENSOR_ERROR_T hx3695_hrv_enable(void); +// SENSOR_ERROR_T hx3695_hrv_enable(void); void hx3695_hrv_disable(void); hrv_wear_msg_code_t hx3695_hrv_get_wear_status(void); -uint8_t hx3695_hrv_read(hrv_sensor_data_t * s_dat); +// uint8_t hx3695_hrv_read(hrv_sensor_data_t * s_dat); bool hx3695_hrv_init(void); HRV_CAL_SET_T PPG_hrv_agc(void); hrv_wear_msg_code_t hx3695_hrv_wear_mode_check(int32_t infrared_data); diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_spo2_agc.c b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_spo2_agc.c index 9a230be3f..dc658a1ae 100644 --- a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_spo2_agc.c +++ b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_spo2_agc.c @@ -835,70 +835,70 @@ void hx3695_spo2_set_mode(uint8_t mode_cmd) } } -SENSOR_ERROR_T hx3695_spo2_enable(void) -{ - if (!hx3695_chip_check()) - { - AGC_LOG("hx3695 check id failed!\r\n"); - return SENSOR_OP_FAILED; - } - - AGC_LOG("hx3695 check id success!\r\n"); - - if (s_ppg_state) - { - AGC_LOG("ppg already on!\r\n"); - return SENSOR_OP_FAILED; - } - - if(!tyhx_spo2_alg_open()) - { - AGC_LOG("spo2 alg open fail,or dynamic ram not enough!\r\n"); - return SENSOR_OP_FAILED; - } - spo2_wear_status = MSG_SPO2_NO_WEAR; - spo2_wear_status_pre = MSG_SPO2_NO_WEAR; - hx3695_spo2_set_mode(PPG_INIT); - - AGC_LOG("hx3695 enable!\r\n"); - - return SENSOR_OK; -} - -SENSOR_ERROR_T hx3695_hrspo2_enable(void) -{ - if (!hx3695_chip_check()) - { - AGC_LOG("hx3695 check id failed!\r\n"); - return SENSOR_OP_FAILED; - } - - AGC_LOG("hx3695 check id success!\r\n"); - - if (s_ppg_state) - { - AGC_LOG("ppg already on!\r\n"); - return SENSOR_OP_FAILED; - } - - if(!tyhx_spo2_alg_open()) - { - AGC_LOG("spo2 alg open fail,or dynamic ram not enough!\r\n"); - return SENSOR_OP_FAILED; - } - if(!tyhx_hrs_alg_open()) - { - AGC_LOG("spo2 alg open fail,or dynamic ram not enough!\r\n"); - return SENSOR_OP_FAILED; - } - spo2_wear_status = MSG_SPO2_NO_WEAR; - spo2_wear_status_pre = MSG_SPO2_NO_WEAR; - hx3695_spo2_set_mode(PPG_INIT); - - AGC_LOG("hx3695 enable!\r\n"); - - return SENSOR_OK; -} +// SENSOR_ERROR_T hx3695_spo2_enable(void) +// { +// if (!hx3695_chip_check()) +// { +// AGC_LOG("hx3695 check id failed!\r\n"); +// return SENSOR_OP_FAILED; +// } + +// AGC_LOG("hx3695 check id success!\r\n"); + +// if (s_ppg_state) +// { +// AGC_LOG("ppg already on!\r\n"); +// return SENSOR_OP_FAILED; +// } + +// if(!tyhx_spo2_alg_open()) +// { +// AGC_LOG("spo2 alg open fail,or dynamic ram not enough!\r\n"); +// return SENSOR_OP_FAILED; +// } +// spo2_wear_status = MSG_SPO2_NO_WEAR; +// spo2_wear_status_pre = MSG_SPO2_NO_WEAR; +// hx3695_spo2_set_mode(PPG_INIT); + +// AGC_LOG("hx3695 enable!\r\n"); + +// return SENSOR_OK; +// } + +// SENSOR_ERROR_T hx3695_hrspo2_enable(void) +// { +// if (!hx3695_chip_check()) +// { +// AGC_LOG("hx3695 check id failed!\r\n"); +// return SENSOR_OP_FAILED; +// } + +// AGC_LOG("hx3695 check id success!\r\n"); + +// if (s_ppg_state) +// { +// AGC_LOG("ppg already on!\r\n"); +// return SENSOR_OP_FAILED; +// } + +// if(!tyhx_spo2_alg_open()) +// { +// AGC_LOG("spo2 alg open fail,or dynamic ram not enough!\r\n"); +// return SENSOR_OP_FAILED; +// } +// if(!tyhx_hrs_alg_open()) +// { +// AGC_LOG("spo2 alg open fail,or dynamic ram not enough!\r\n"); +// return SENSOR_OP_FAILED; +// } +// spo2_wear_status = MSG_SPO2_NO_WEAR; +// spo2_wear_status_pre = MSG_SPO2_NO_WEAR; +// hx3695_spo2_set_mode(PPG_INIT); + +// AGC_LOG("hx3695 enable!\r\n"); + +// return SENSOR_OK; +// } void hx3695_spo2_disable(void) { diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_spo2_agc.h b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_spo2_agc.h index db736fff5..b9135a266 100644 --- a/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_spo2_agc.h +++ b/code/sdk/zhihui/drivers/ppg/hx3695/hx3695_spo2_agc.h @@ -117,7 +117,7 @@ void hx3695_spo2_low_power(void); void hx3695_spo2_normal_power(void); void hx3695_spo2_updata_reg(void); void hx3695_spo2_set_mode(uint8_t mode_cmd); -SENSOR_ERROR_T hx3695_spo2_enable(void); +// SENSOR_ERROR_T hx3695_spo2_enable(void); void hx3695_spo2_disable(void); spo2_wear_msg_code_t hx3695_spo2_get_wear_status(void); uint8_t hx3695_spo2_read(spo2_sensor_data_t * s_dat); diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/libHX3697_hs_20240607_3333__02_spo.a b/code/sdk/zhihui/drivers/ppg/hx3695/libHX3697_hs_20240607_3333__02_spo.a new file mode 100644 index 000000000..d72722be8 Binary files /dev/null and b/code/sdk/zhihui/drivers/ppg/hx3695/libHX3697_hs_20240607_3333__02_spo.a differ diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/libHX3697_hs_20241230_103__01_hrv.a b/code/sdk/zhihui/drivers/ppg/hx3695/libHX3697_hs_20241230_103__01_hrv.a new file mode 100644 index 000000000..32ccac46f Binary files /dev/null and b/code/sdk/zhihui/drivers/ppg/hx3695/libHX3697_hs_20241230_103__01_hrv.a differ diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/libHX3697_hs_20241230_3153__01_hrs.a b/code/sdk/zhihui/drivers/ppg/hx3695/libHX3697_hs_20241230_3153__01_hrs.a new file mode 100644 index 000000000..0b8576604 Binary files /dev/null and b/code/sdk/zhihui/drivers/ppg/hx3695/libHX3697_hs_20241230_3153__01_hrs.a differ diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/tyhx_hrs_alg.h b/code/sdk/zhihui/drivers/ppg/hx3695/tyhx_hrs_alg.h index b693581dd..f7eeaf46d 100644 --- a/code/sdk/zhihui/drivers/ppg/hx3695/tyhx_hrs_alg.h +++ b/code/sdk/zhihui/drivers/ppg/hx3695/tyhx_hrs_alg.h @@ -1,22 +1,22 @@ -//vesion3.1.35 +//vesion3.1.53 #ifndef _TYHX_HRS_ALG_H_ #define _TYHX_HRS_ALG_H_ #include -#if 0 -/* portable 8-bit unsigned integer */ -typedef unsigned char uint8_t; -/* portable 8-bit signed integer */ -typedef signed char int8_t; -/* portable 16-bit unsigned integer */ -typedef unsigned short int uint16_t; -/* portable 16-bit signed integer */ -typedef signed short int int16_t; -/* portable 32-bit unsigned integer */ -typedef unsigned int uint32_t; -/* portable 32-bit signed integer */ -typedef signed int int32_t; -#endif + +// /* portable 8-bit unsigned integer */ +// typedef unsigned char uint8_t; +// /* portable 8-bit signed integer */ +// typedef signed char int8_t; +// /* portable 16-bit unsigned integer */ +// typedef unsigned short int uint16_t; +// /* portable 16-bit signed integer */ +// typedef signed short int int16_t; +// /* portable 32-bit unsigned integer */ +// //typedef unsigned int uint32_t; +// /* portable 32-bit signed integer */ +// //typedef signed int int32_t; + #ifndef bool #define bool unsigned char #endif @@ -28,7 +28,25 @@ typedef signed int int32_t; #define false 0 #endif -#ifdef HRS_ALG_LIB + +///////////////////////// config /////////////////////////// +#define BP_CUSTDOWN_ALG_LIB +#define SHARED_RAM +#define NO_MATH_LIB + +//define DEBUG_DATA +////////////////////////////////////////////////////////////// + + +// #ifdef DEBUG_DATA +// #define DEBUG_PRINTF(...) SEGGER_RTT_printf(0,__VA_ARGS__) +// #else +// #define DEBUG_PRINTF(...) +// #endif + +#ifdef SHARED_RAM +extern uint8_t alg_ram[11 * 1024] __attribute__((aligned(4))); +#endif typedef enum { NORMAL_MODE, @@ -36,7 +54,8 @@ typedef enum { WALK_MODE, JUMP_MODE, ALLDAY_HR_MODE, - HIGH_POW_MODE + HIGH_POW_MODE, + CLICK_MODE } hrs_sports_mode_t; typedef enum { @@ -60,6 +79,13 @@ typedef struct { uint16_t cal_result; uint8_t hr_result_qual; uint32_t hr_result_std; + hrs_sports_mode_t hr_mode; + uint8_t stress; + uint8_t breath; + uint32_t rri; + uint32_t rri_num; + uint32_t rri_std; + uint32_t rmssd; } hrs_results_t; #ifdef BP_CUSTDOWN_ALG_LIB @@ -84,7 +110,7 @@ typedef struct { typedef struct { bp_msg_code_t bp_alg_status; uint8_t sbp; - uint8_t dbp; + uint8_t dbp; uint32_t data_cnt; uint8_t hr_result; bool object_flg; @@ -105,7 +131,6 @@ bool tyhx_motion_pedometer(int16_t gsen_data_x, int16_t gsen_data_y, int16_t gse hrs_results_t tyhx_hrs_alg_get_results(void); void tyhx_hrs_set_alg_para(hrs_sports_mode_t sports_mode, uint16_t static_thre_val, uint8_t gsen_fun_lv_val); void tyhx_hrs_set_living(uint8_t mode, uint8_t qu_thre, uint8_t st_thre); -#endif //HRS_ALG_LIB #endif diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/tyhx_hrs_custom.h b/code/sdk/zhihui/drivers/ppg/hx3695/tyhx_hrs_custom.h index d956bbd89..fcab35dab 100644 --- a/code/sdk/zhihui/drivers/ppg/hx3695/tyhx_hrs_custom.h +++ b/code/sdk/zhihui/drivers/ppg/hx3695/tyhx_hrs_custom.h @@ -8,7 +8,7 @@ * @Author: penglei 1624952103@qq.com * @Date: 2024-03-26 20:29:58 * @LastEditors: penglei 1624952103@qq.com - * @LastEditTime: 2024-11-18 17:32:40 + * @LastEditTime: 2025-10-22 17:41:15 * @FilePath: /FD230/code/sdk/drivers/peripheral/ppg/hx3695/tyhx_hrs_custom.h * @Description: * @@ -36,7 +36,8 @@ typedef struct { } FT_CUSTOM_RESULTS_t; extern FT_CUSTOM_RESULTS_t hrsresult; -//#define TYHX_DEBUG + +#define TYHX_DEBUG #ifdef TYHX_DEBUG #define TYHX_LOG(fmt, ...) \ diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/tyhx_hrv_alg.h b/code/sdk/zhihui/drivers/ppg/hx3695/tyhx_hrv_alg.h index 116e27889..1917614f4 100644 --- a/code/sdk/zhihui/drivers/ppg/hx3695/tyhx_hrv_alg.h +++ b/code/sdk/zhihui/drivers/ppg/hx3695/tyhx_hrv_alg.h @@ -1,8 +1,10 @@ +//tyhx_hrv_v1.0.3 + #ifndef _TYHX_HRV_ALG_H_ #define _TYHX_HRV_ALG_H_ -#endif #include + #if 0 /* portable 8-bit unsigned integer */ typedef unsigned char uint8_t; @@ -16,7 +18,7 @@ typedef signed short int int16_t; typedef unsigned int uint32_t; /* portable 32-bit signed integer */ typedef signed int int32_t; -#endif + #ifndef bool #define bool unsigned char #endif @@ -26,11 +28,27 @@ typedef signed int int32_t; #ifndef false #define false 0 #endif +#endif + #define HRV_GLITCH_THRES 20000 #define HRV_GSEN_POW_THRE 150 -#ifdef HRV_ALG_LIB +///////////////////////// config /////////////////////////// +#define SHARED_RAM +//define DEBUG_DATA +////////////////////////////////////////////////////////////// + + +// #ifdef DEBUG_DATA +// #define DEBUG_PRINTF(...) SEGGER_RTT_printf(0,__VA_ARGS__) +// #else +// #define DEBUG_PRINTF(...) +// #endif + +#ifdef SHARED_RAM +extern uint8_t alg_ram[11 * 1024] __attribute__((aligned(4))); +#endif typedef enum { MSG_HRV_ALG_NOT_OPEN, @@ -42,8 +60,10 @@ typedef enum { typedef struct { hrv_alg_msg_code_t hrv_alg_status; uint32_t data_cnt; - uint8_t hrv_result; + uint32_t hrv_result; + uint32_t hr; uint32_t hrv_peak; + uint32_t rri_cnt; uint8_t spirit_pressure; uint8_t p_m; uint8_t screen_up; @@ -60,5 +80,5 @@ void kfft(double *pr,double *pi,int n,int k,double *fr,double *fi); hrv_results_t tyhx_hrv_alg_send_data(int32_t new_raw_data, int32_t green_data_als, int32_t infrared_data); hrv_results_t tyhx_hrv_alg_send_bufdata(int32_t *new_raw_data, uint8_t count, int16_t *gsen_data_x, int16_t *gsen_data_y, int16_t *gsen_data_z); -#endif //HRV_ALG_LIB - + +#endif diff --git a/code/sdk/zhihui/drivers/ppg/hx3695/tyhx_spo2_alg.h b/code/sdk/zhihui/drivers/ppg/hx3695/tyhx_spo2_alg.h index e330cc6f0..56afe77ee 100644 --- a/code/sdk/zhihui/drivers/ppg/hx3695/tyhx_spo2_alg.h +++ b/code/sdk/zhihui/drivers/ppg/hx3695/tyhx_spo2_alg.h @@ -3,24 +3,23 @@ #endif #include -//version:3.3.17 +//version:xiaoche3.3.5 //#include "tyhx_spo2_alg_para.h" -#if 0 -/* portable 8-bit unsigned integer */ -typedef unsigned char uint8_t; -/* portable 8-bit signed integer */ -typedef signed char int8_t; -/* portable 16-bit unsigned integer */ -typedef unsigned short int uint16_t; -/* portable 16-bit signed integer */ -typedef signed short int int16_t; -/* portable 32-bit unsigned integer */ -typedef unsigned int uint32_t; -/* portable 32-bit signed integer */ -typedef signed int int32_t; -#endif + +// /* portable 8-bit unsigned integer */ +// typedef unsigned char uint8_t; +// /* portable 8-bit signed integer */ +// typedef signed char int8_t; +// /* portable 16-bit unsigned integer */ +// typedef unsigned short int uint16_t; +// /* portable 16-bit signed integer */ +// typedef signed short int int16_t; +// /* portable 32-bit unsigned integer */ +// //typedef unsigned int uint32_t; +// /* portable 32-bit signed integer */ +// //typedef signed int int32_t; #ifndef bool #define bool unsigned char @@ -35,7 +34,7 @@ typedef signed int int32_t; #ifdef SPO2_ALG_LIB - +extern uint32_t hr_sqrt(uint32_t x); typedef enum { MSG_SPO2_ALG_NOT_OPEN, MSG_SPO2_ALG_OPEN, @@ -68,10 +67,10 @@ typedef struct { uint8_t screen_up; uint8_t motion; uint8_t poor_signal; - + uint8_t signal_snr; uint32_t signal_std; - + } spo2_results_t; typedef struct { @@ -82,38 +81,29 @@ typedef struct { typedef struct { uint32_t data_cnt; - int32_t red_new_raw_data; - int32_t ir_new_raw_data; - int32_t green_new_raw_data; - int32_t ir_iir_data_filter_out; - int32_t ir_data_smooth; - int32_t red_iir_data_filter_out; - int32_t red_data_smooth; + uint8_t motion; uint8_t ir_offset_50; uint8_t red_offset_50; uint8_t green_offset_50; int32_t ir_dc; int32_t red_dc; int32_t green_dc; - int32_t ir_data_o2_128; - int32_t red_data_o2_128; - int32_t green_data_o2_128; - int16_t red_ir_dc; - int16_t red_green_dc; - int16_t ir_green_dc; - int16_t ir_fft_snr; - int8_t motion_status; - uint8_t xcorr_max; - int16_t COUNT_IN_judge; + int32_t ir_ac; + int32_t red_ac; + int32_t green_ac; + int32_t sa_temp; + int32_t gi_temp; + int32_t sa_final; + uint16_t ir_fft_snr; + uint16_t red_fft_snr; + uint8_t count_block; uint8_t spo2_result; - uint8_t count_block; - int32_t SaO2_data_temp; } spo2_debug_t; typedef struct { uint8_t red_offset_idac; - uint8_t ir_offset_idac; - uint8_t green_offset_idac; + uint8_t ir_offset_idac; + uint8_t green_offset_idac; uint16_t spo2_start_cnt; } spo2_agcpara_t; @@ -161,5 +151,5 @@ bool tyhx_spo2_alg_open_deep(void); spo2_results_t tyhx_spo2_alg_get_results(void); spo2_debug_t tyhx_spo2_alg_debug_results(void); -#endif +#endif diff --git a/code/sdk/zhihui/services/factorytest_service/factorytest_protocol.c b/code/sdk/zhihui/services/factorytest_service/factorytest_protocol.c index 8f6a71ccd..30c8cc0ea 100644 --- a/code/sdk/zhihui/services/factorytest_service/factorytest_protocol.c +++ b/code/sdk/zhihui/services/factorytest_service/factorytest_protocol.c @@ -2,7 +2,7 @@ * @Author: penglei 1624952103@qq.com * @Date: 2024-06-17 14:31:08 * @LastEditors: penglei 1624952103@qq.com - * @LastEditTime: 2025-10-21 11:11:55 + * @LastEditTime: 2025-10-24 17:25:15 * @FilePath: /FD230/code/sdk/application/wearable/service/factorytest_service/factorytest_protocol.c * @Description: * @@ -1622,17 +1622,17 @@ void factorytest_protocol_soft_test_decode(uint8_t submode,uint8_t testitem,uint uint8_t databuf[4] = {0}; #ifdef BOARD_FD230 #ifdef PPG_HX3695 - send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_DO_SINGLE_CHECK_MODE_TEST); - LOS_Msleep(2000); - FT_RESULTS_t ft_result = hx3695_factroy_test(SINGLE_CHECK_TEST); - send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_STOP_PPG_TEST); + // send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_DO_SINGLE_CHECK_MODE_TEST); + // LOS_Msleep(2000); + // FT_RESULTS_t ft_result = ppg_get_factory_data(SINGLE_CHECK_TEST); + // send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_STOP_PPG_TEST); - databuf[0] = (uint8_t)((ft_result.gr_data_final & 0xFF000000) >> 24); - databuf[1] = (uint8_t)((ft_result.gr_data_final & 0x00FF0000) >> 16); - databuf[2] = (uint8_t)((ft_result.gr_data_final & 0x0000FF00) >> 8); - databuf[3] = (uint8_t)((ft_result.gr_data_final & 0x000000FF) >> 0); + // databuf[0] = (uint8_t)((ft_result.gr_data_final & 0xFF000000) >> 24); + // databuf[1] = (uint8_t)((ft_result.gr_data_final & 0x00FF0000) >> 16); + // databuf[2] = (uint8_t)((ft_result.gr_data_final & 0x0000FF00) >> 8); + // databuf[3] = (uint8_t)((ft_result.gr_data_final & 0x000000FF) >> 0); - PRINT("%2X %2X %2X %2X \r\n",databuf[0],databuf[1],databuf[2],databuf[3]); + // PRINT("%2X %2X %2X %2X \r\n",databuf[0],databuf[1],databuf[2],databuf[3]); factorytest_protocol_replymsg(BLE_TEST_CMD_MODE_SOFT_TEST, BLE_TEST_CMD_SOFT_TEST_SUB_MODE_HRS, @@ -1670,15 +1670,15 @@ void factorytest_protocol_soft_test_decode(uint8_t submode,uint8_t testitem,uint uint8_t databuf[4] = {0}; #ifdef BOARD_FD230 #ifdef PPG_HX3695 - send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_DO_SINGLE_CHECK_MODE_TEST); - LOS_Msleep(500); - FT_RESULTS_t ft_result = hx3695_factroy_test(SINGLE_CHECK_TEST); - send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_STOP_PPG_TEST); - - databuf[0] = (uint8_t)((ft_result.red_data_final & 0xFF000000) >> 24); - databuf[1] = (uint8_t)((ft_result.red_data_final & 0x00FF0000) >> 16); - databuf[2] = (uint8_t)((ft_result.red_data_final & 0x0000FF00) >> 8); - databuf[3] = (uint8_t)((ft_result.red_data_final & 0x000000FF) >> 0); + // send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_DO_SINGLE_CHECK_MODE_TEST); + // LOS_Msleep(500); + // FT_RESULTS_t ft_result = hx3695_factroy_test(SINGLE_CHECK_TEST); + // send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_STOP_PPG_TEST); + + // databuf[0] = (uint8_t)((ft_result.red_data_final & 0xFF000000) >> 24); + // databuf[1] = (uint8_t)((ft_result.red_data_final & 0x00FF0000) >> 16); + // databuf[2] = (uint8_t)((ft_result.red_data_final & 0x0000FF00) >> 8); + // databuf[3] = (uint8_t)((ft_result.red_data_final & 0x000000FF) >> 0); #endif #elif defined BOARD_N9 //获取红灯数据 @@ -1712,21 +1712,21 @@ void factorytest_protocol_soft_test_decode(uint8_t submode,uint8_t testitem,uint send_ppg_cmd_msg(PPG_SERVICE_CMD_TYPE_DO_GRAYCARD_TEST); LOS_Msleep(2000); uint8_t databuf[12] = {0}; - FT_RESULTS_t ft_result = hx3695_factroy_test(GRAY_CARD_TEST); - databuf[0] = (uint8_t)((ft_result.gr_data_final & 0xFF000000) >> 24); - databuf[1] = (uint8_t)((ft_result.gr_data_final & 0x00FF0000) >> 16); - databuf[2] = (uint8_t)((ft_result.gr_data_final & 0x0000FF00) >> 8); - databuf[3] = (uint8_t)((ft_result.gr_data_final & 0x000000FF) >> 0); - - databuf[4] = (uint8_t)((ft_result.red_data_final & 0xFF000000) >> 24); - databuf[5] = (uint8_t)((ft_result.red_data_final & 0x00FF0000) >> 16); - databuf[6] = (uint8_t)((ft_result.red_data_final & 0x0000FF00) >> 8); - databuf[7] = (uint8_t)((ft_result.red_data_final & 0x000000FF) >> 0); - - databuf[8] = (uint8_t)((ft_result.ir_data_final & 0xFF000000) >> 24); - databuf[9] = (uint8_t)((ft_result.ir_data_final & 0x00FF0000) >> 16); - databuf[10] = (uint8_t)((ft_result.ir_data_final & 0x0000FF00) >> 8); - databuf[11] = (uint8_t)((ft_result.ir_data_final & 0x000000FF) >> 0); + // FT_RESULTS_t ft_result = hx3695_factroy_test(GRAY_CARD_TEST); + // databuf[0] = (uint8_t)((ft_result.gr_data_final & 0xFF000000) >> 24); + // databuf[1] = (uint8_t)((ft_result.gr_data_final & 0x00FF0000) >> 16); + // databuf[2] = (uint8_t)((ft_result.gr_data_final & 0x0000FF00) >> 8); + // databuf[3] = (uint8_t)((ft_result.gr_data_final & 0x000000FF) >> 0); + + // databuf[4] = (uint8_t)((ft_result.red_data_final & 0xFF000000) >> 24); + // databuf[5] = (uint8_t)((ft_result.red_data_final & 0x00FF0000) >> 16); + // databuf[6] = (uint8_t)((ft_result.red_data_final & 0x0000FF00) >> 8); + // databuf[7] = (uint8_t)((ft_result.red_data_final & 0x000000FF) >> 0); + + // databuf[8] = (uint8_t)((ft_result.ir_data_final & 0xFF000000) >> 24); + // databuf[9] = (uint8_t)((ft_result.ir_data_final & 0x00FF0000) >> 16); + // databuf[10] = (uint8_t)((ft_result.ir_data_final & 0x0000FF00) >> 8); + // databuf[11] = (uint8_t)((ft_result.ir_data_final & 0x000000FF) >> 0); factorytest_protocol_replymsg(BLE_TEST_CMD_MODE_SOFT_TEST, BLE_TEST_CMD_SOFT_TEST_SUB_MODE_HRS,